Applied Surface Science 515 (2020) 145988

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Applied Surface Science

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Full Length Article

Dual-gate crystalline oxide-nanowire field-effect transistors utilizing ion-gel T

gate dielectric
Jaeyoung Kima,1, Woobin Leea,1, Seungbeom Choia, Kyung-Tae Kimb, Jae-Sang Heoc,
⁎ ⁎
Sung Kyu Parkb, , Yong-Hoon Kima,d,
a
SKKU Advanced Institute of Nanotechnology (SAINT), Sungkyunkwan University, Suwon 16419, Republic of Korea
b
School of Electrical and Electronics Engineering, Chung-Ang University, Seoul 06980, Republic of Korea
c
Department of Medicine, University of Connecticut School of Medicine, Farmington, CT 06030, USA
d
School of Advanced Materials Science and Engineering, Sungkyunkwan University, Suwon 16419, Republic of Korea

A R T I C LE I N FO A B S T R A C T

Keywords: Dual-gate structure field-effect transistors (DG FETs) can provide various advantages such as high output cur-
Oxide nanowire rent, enhanced mobility, and tunability of threshold voltage (VTH) by adversely controlling the two channels
Dual-gate formed at both top and bottom gate dielectric interfaces. Here, we present high-mobility DG structure FETs using
Field-effect transistor crystalline Ga-doped In2O3 (IGO) nanowires (NWs) as channel and high-k ion-gel as a top gate dielectric layer.
Ga-doped In2O3
To enhance the electrical properties of IGO NW FETs such as field-effect mobility, on/off ratio, VTH, and sub-
Electrospinning
threshold slope, optimization of electrospinning, Ga doping in In2O3 NWs, and thermal annealing was carried
Ion gel gate dielectric
out. The optimized IGO NW FETs with a single SiO2 gate dielectric exhibited field-effect mobility of ~6.0 cm2/
(V·s), on/off ratio of > 107, subthreshold slope of 0.73 V/decade, and VTH of ~0 V. Also, the IGO NW FETs
showed excellent operation stabilities under positive-gate-bias and negative-bias-illumination stress conditions.
Furthermore, by using a high-k ion-gel film as the second gate dielectric layer, DG IGO NW FETs with field-effect
mobility up to ~35.1 cm2/(V·s) were realized which is comparably higher than those of single-gated IGO NW
FETs (6.0–6.5 cm2/(V·s)).

1. Introduction
Recently, amorphous oxide semiconductor (AOS)-based field-effect
transistors (FETs) have attracted considerable attention in high-density
active-matrix electronics owing to their high carrier mobility, good
uniformity, and reasonable operation stability [1–4]. However, the re-
cent progress in high resolution, high speed, and low-power con-
sumption electronics has led to the development of FETs with superior
performance and stability overwhelming the conventional AOS FETs. In
this regard, several strategies have been devised to improve their per-
formances such as the crystallization of oxide channel layers, doping
with additional metallic atoms, and application of modified device ar-
chitectures. For example, dual-gate (DG) structure oxide FETs have
been reported to enhance the mobility and stability, by utilizing the
extended channel regions formed at both front and back interfaces and
by the reduced vertical electric field, respectively [5]. Here, by using
In–Ga–Zn–O (IGZO) as the channel layer, DG FETs having an apparent
mobility of 20 cm2/(V·s) was demonstrated using SiO2 as the front and
back gate dielectric layers [5].
In addition to the device structure modification, the utilization of
crystalline oxide channel layers was also investigated. Here, instead of
using amorphous oxide channel layer, highly crystalline oxide semi-
conductors such as c-axis-aligned crystalline IGZO or polycrystalline
IGZO was employed as the channel layer. Owing to the highly crys-
talline structure and less defective states of the crystalline IGZO chan-
nels, FETs with improved mobilities and stabilities were realized [6].
Furthermore, oxide semiconductors with nanowire (NW) structures are
also of great interest as they can exhibit high electron mobilities and
good electrical stability [7–17]. Previously, it was demonstrated that
crystalline oxide NWs such as ZnO and In2O3 NWs and their doped
families could exhibit exceptionally high electron mobilities, out-
performing the single-crystalline Si-based FETs. For example, Ju et al.
reported pre-synthesized oxide NW FETs exhibiting a field-effect mo-
bility up to ~514 cm2/(V·s) [7]. Additionally, Zhou et al. demonstrated

⁎
Corresponding authors at: School of Advanced Materials Science and Engineering, Sungkyunkwan University, Suwon 16419, Republic of Korea (Y.-H. Kim).
School of Electrical and Electronics Engineering, Chung-Ang University, Seoul 06980, Republic of Korea (S.K. Park).
E-mail addresses: skpark@cau.ac.kr (S.K. Park), yhkim76@skku.edu (Y.-H. Kim).
1
These authors contributed equally to this work

https://doi.org/10.1016/j.apsusc.2020.145988
Received 23 December 2019; Received in revised form 28 February 2020; Accepted 5 March 2020
Available online 16 March 2020
0169-4332/ © 2020 Elsevier B.V. All rights reserved.
J. Kim, et al.
Fig. 1. (a) The fabrication of dual-gate (DG) IGO NW FETs using the electrospinning process. (b) In-plane SEM, and (c) a cross-sectional TEM images of IGO3 NWs
fabricated on a Si/SiO2 substrate. The topography and conductive atomic force microscope (AFM) images of (d) as-spun, and (e) 450 °C-annealed IGO3 NWs. In each
set, the left panel shows the topography image and the right panel shows the conductive AFM image.
In2O3 NW FETs having a field-effect mobility of 750 cm2/(V·s) which
were fabricated by using the chemical vapor deposition (CVD) method
[8]. Even though these oxide NW FETs using pre-synthesized or CVD-
deposited oxide NW channels are noteworthy [8–10], the relatively
small deposition area, high process temperature, and rather low uni-
formity can hinder their full utilization in large-area electronics. To
resolve such issues, electrospinning method has been suggested to
fabricate the oxide semiconductor NWs since it can cover a relatively
large-area and provide high spatial uniformity [11–17]. For instance,
Park et al. reported electrospun In2O3 NWs for the FET applications
[13]. Here, by using ZrO2 as the passivation layer, In2O3 NW FETs
having field-effect mobility of ~10 cm2/(V·s) were achieved. In addi-
tion, various electrospun In2O3 NW FETs [9,12] and Gd-doped In2O3
FETs [17] were also reported, demonstrating the feasibility of the
electrospinning method for the formation of uniform oxide NW channel
layer. Moreover, it was also reported that one-dimensional IGZO FETs
can be fabricated on a polyimide wire substrate as a basic building
block for a flexible electronic textile system [18].
In this study, to overcome the conventional thin-film type AOS FETs
and realize high-performance and high stability oxide-based FETs, DG
structure FETs having crystalline oxide NWs as the channel layer are
demonstrated. Particularly, crystalline Ga-doped In2O3 (IGO) NW
channels are formed by using electrospinning and subsequent calcina-
tion process and utilized in DG FETs having a high-k ion gel film as the
second top gate dielectric. Firstly, through the optimization of IGO NW
formation and Ga doping in the In2O3 matrix, IGO NW FETs with a
saturation field-effect mobility of ~6.0 cm2/(V·s), on/off ratio larger
than 107, threshold voltage (VTH) of −0.8 ± 1.04 V, and subthreshold
slope (SS) of 0.73 V/decade were obtained, with a single SiO2 gate
dielectric. The IGO NW FETs also exhibited excellent operation stabi-
lities under positive-gate-bias stress (PBS) (ΔVTH = −1.17 V, at 5760 s)
and negative gate-bias illumination stress (NBIS) (ΔVTH = 0.30 V, at
5760 s) conditions possibly due to the crystalline structure of the IGO
channel layer. Furthermore, by using a high-k ion gel film as the second
top gate dielectric, DG oxide NW FETs were fabricated. The IGO NW DG
FETs exhibited an improved apparent field-effect mobility of
~35.1 cm2/(V·s) in an asymmetric operation, which is comparably
higher than those of single-gate (SG) IGO NW FETs (6.0 cm2/(V·s) for
SiO2 and 6.5 cm2/(V·s) for the ion-gel gate dielectric). We provide the
possible operation mechanisms for the IGO NW DG FETs under various
asymmetric operation modes.
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Applied Surface Science 515 (2020) 145988
2. Experimental Section
2.1. Preparation of metal-oxide precursor solutions for electrospinning
For the fabrication of In2O3 and IGO NWs by electrospinning, cor-
responding precursor solutions were prepared by dissolving indium
nitrate hydrate (In(NO3)3·xH2O) and gallium nitrate hydrate (Ga
(NO3)3·xH2O) in N,N-dimethylformamide (DMF) (5 g). To increase the
viscosity of the solution appropriate for the electrospinning process,
0.7 g of polyvinylpyrrolidone (PVP, Mw ~1,300,000) was additionally
dissolved in the solution. The precursor solution was then stirred for
more than 24 h at room temperature before the electrospinning. All the
metallic precursors, PVP and DMF were purchased from Sigma Aldrich
and used without further modification. The total concentration of me-
tallic precursors in the solution was fixed at 0.24 M, while the In:Ga
molar ratio was varied as 10:0, 9:1, 8:2, 7:3 and 6:4. For simplicity,
IGOx is defined, representing the IGO NWs with an In:Ga molar ratio of
(10 – x):x (x = 0, 1, 2, 3 or 4).
2.2. Electrospinning of In2O3 and IGO NWs and FET fabrication
After the preparation of the precursor solutions, electrospinning of
In2O3 and IGO NWs was carried out using an electrospinning/electro-
spray machine (ESR200R2, NanoNC). As a substrate, we used a heavily
doped p-type Si wafer with a 200 nm-thick SiO2 layer, where the Si
wafer and SiO2 layer served as the gate electrode and the gate dielectric
layer, respectively. During electrospinning, an electrical field of 13 kV
was applied to eject the precursor solution from the syringe. The dis-
tance between the needle and substrate was set to 15 cm. After the
electrospinning of the solution, the sample was thermally annealed
(calcined) at 150–450 °C for 2 h. Subsequently, the electrospun NW film
was patterned by photolithography and wet etching. Then, aluminum
(Al) source/drain electrodes with thickness of ~75 nm were deposited
by thermal evaporation and patterned using a metal shadow mask. The
channel length (L) and width (W) of the FET were 100 and 1000 μm,
respectively. Here, the channel width (W) is defined as the contact re-
gion made between the source or drain electrode and the patterned
oxide NW channel (Fig. 1(a)). To form an ion-gel gate dielectric for the
DG FETs, an ion-gel solution consisting of poly(ethylene glycol) dia-
crylate (monomer), 2-hydroxy-2-methyl-propiophenone (photo-
initiator), and 1-ethyl-3-methylimidazolium bis
J. Kim, et al. Applied Surface Science 515 (2020) 145988

Fig. 2. (a) In-plane SEM and microscope images of electrospun In2O3 NWs with different electrospinning time. (b) Optical images of fabricated In2O3 NW FETs. The
channel length and width of the FET were 100 and 1000 μm, respectively. (c) Transfer characteristics of single-gate (SG) In2O3 NW FETs with different electro-
spinning time. (d) Transfer characteristics of SG In2O3 NW FETs with different annealing temperature.

(trifluoromethanesulfonyl)imide (EMIM:TFSI, ionic liquid) in a weight 3. Result and discussion

ratio of 0.08:0.04:0.88 was drop-casted onto the patterned IGO NWs.
Subsequently, the sample was exposed with ultraviolet light for 15 s
through a photomask to pattern the ion-gel gate dielectric. The un-
exposed region of the ion-gel layer was washed away with deionized
water.
2.3. Characterization of the oxide NWs and SG/DG FETs
The microstructure of the electrospun oxide NWs was observed
using field emission scanning electron microscopy (FESEM; JSM-7600F,
JEOL) and high-resolution transmission electron microscopy (HRTEM;
JEM-2100F, JEOL). Topological and conductive atomic force micro-
scopy (AFM; NX-10, Park Systems) analyses were performed to verify
the conversion from as-spun NWs to oxide NWs. The electrical char-
acteristics of the In2O3 and IGO NW FETs were measured by using a
semiconductor parameter analyzer (4155C, Agilent). Capacitance
measurements of gate dielectrics were carried out by using an in-
ductance–capacitance–resistance (LCR) meter (4284A, Agilent). For the
DG FETs, the transfer curves were measured under asymmetric opera-
tion condition by scanning one of the gates while fixing the other gate
bias.
The fabrication of SG and DG oxide NW FETs is illustrated in
Fig. 1(a). At first, electrospinning of oxide precursor solution is carried
out on a Si/SiO2 substrate to form a network of NWs. Then, to derive
the sol–gel reaction for the oxide NW formation as well as to remove the
insulating PVP component, calcination process is carried out
(150–450 °C). After the calcination, the average diameter size (or the
width) of the NWs was decreased from ~383 nm to ~125.3 nm. After
the calcination, Al source/drain electrodes are deposited, constructing a
SG FET with top-contact configuration. For the DG FET fabrication, an
ion-gel gate dielectric is formed on top of the oxide NW channel layer
by the method described in the Experimental Section. Fig. 1(b) and (c)
show the in-plane FESEM and cross-sectional TEM images of IGO3 NWs
fabricated on a Si/SiO2 substrate, respectively. After the calcination, the
oxide NWs showed hemisphere-like morphology as shown in Fig. 1(c).
Accordingly, the thickness was larger at the center region (~8.4 nm)
and decreased along the edge directions. In addition, the oxide NWs
had crystalline structure as shown in Fig. S1 in the Electronic
Supplementary Material (ESM). The formation of semiconducting oxide
NWs was further verified by the conductive AFM measurement.
Fig. 1(d) and (e) show the topography and conductive AFM images of
the as-spun and 450-°C-annealed IGO3 NWs, respectively. The as-spun
NWs exhibited only the topological contrast without any variation in

3
J. Kim, et al.
the current, indicating that the NWs are electrically insulators. On the
other hand, after calcination, a clear contrast in the conductive AFM
image was observed, which supports the claim that the NWs are elec-
trically activated and exhibit either semiconducting or conducting
characteristics. These microscopic analyses show that electrically
functioning oxide NWs can be fabricated by the electrospinning and
subsequent calcinations process. Additionally, during the calcination,
we observed a partial formation of welded junctions between the in-
dividual oxide NWs. Figs. S2a–2d in the ESM show the FESEM images of
IGO3 and IGO4 NWs after calcination (450 °C). At the intersections
between the NWs, physically welded junctions are formed. In parti-
cular, wider junctions and larger diameters of IGO4 NWs up to several
hundreds of nanometers were observed. It is expected that by the for-
mation of physically welded junctions between the oxide NWs, the
carrier transport in the oxide NW channel can be promoted, as illu-
strated in Fig. S2e in the ESM, similar to that observed in silver-NW-
based electrodes [19].
When the electrospun oxide NWs are used as the channel layer, the
areal density of oxide NWs and the annealing temperature are im-
portant as the electrical properties of the transistors can be largely
governed by these factors. First, to optimize the areal density of oxide
NWs for the channel layer, we varied the electrospinning time in the
range of 20–40 s. Here, we used In2O3 NWs as the reference material.
Fig. 2(a) shows the in-plane SEM and optical microscopy images of the
In2O3 NWs electrospun for different times. As expected, a denser net-
work was formed at the increased electrospinning time. Fig. 2(b) and
(c) show the fabricated In2O3 NW FETs and corresponding transfer (ID-
VG) characteristics, respectively (annealing temperature of 450 °C).
Although higher saturation mobility could be achieved with longer
electrospinning time (20 s: 9.3 cm2/(V·s); 30 s: 15.2 cm2/(V·s); 40 s:
19.9 cm2/(V·s)), a large negative VTH shift was simultaneously ob-
served, which is detrimental for typical applications of FETs due to
depletion mode operation. Therefore, we set the electrospinning time to
~20 s in further experiments. Additionally, we investigated the effects
of the annealing temperature on the electrical properties of the In2O3
FETs. Fig. 2(d) shows the transfer characteristics of the In2O3 NW FETs
annealed at different temperatures of 150 °C to 450 °C. Up to 250 °C,
the FET showed negligible current modulation by the gate bias showing
that the channel layer is still in insulating states. This indicates in-
sufficient sol-gel reaction for the oxide formation and/or removal of the
PVP component. When the annealing temperature is increased equal or
higher than 350 °C, the overall current density is increased with a clear
modulation of drain current by the gate bias. The results show that
annealing temperature typically higher than 350 °C is required for the
formation of semiconducting In2O3 NWs using the current precursor
system.
Despite the reasonably high mobility of the In2O3 NW FETs, the
relatively low current on/off ratio (~102) can hinder its practical ap-
plications in active-matrix electronics. Because the low on/off ratio is
typically related to the high carrier concentration of the channel layer,
we adopted a carrier suppressor to control the carrier concentration
[20]. Here, we added Ga in the In2O3 NWs which has high Gibbs energy
of oxidation (−661 kJ/mol) [21]. Fig. 3(a) and (e) show the transfer
and output characteristics of In2O3 and Ga-doped In2O3 (IGO) NW FETs
with different Ga concentrations (IGO1, IGO2, IGO3, and IGO4), re-
spectively, fabricated with the annealing temperature of 450 °C. Also,
Fig. 3(b)–(d) show the saturation field-effect mobility, current on/off
ratio, and VTH as a function of Ga concentration, respectively. Afore-
mentioned, the In2O3 NW FET exhibited a relatively high mobility
(8.2 ± 1.33 cm2/(V·s)). However, the off-state current level was higher
than 10−6 A, which led to a low on/off ratio (102–103). Moreover, VTH
was considerably negative (−14.9 ± 3.62 V), indicating a deep-de-
pletion-mode operation. Upon the increase in Ga concentration, the on/
off ratio and VTH considerably changed. As shown in Fig. 3(c), the on/
off ratio exhibited a steep increase up to 107–108 when the Ga con-
centration was higher than 30% (IGO3 and IGO4). Moreover, the VTH
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Applied Surface Science 515 (2020) 145988
value was gradually increased for IGO3 and IGO4 NW FETs, having
average VTH values of −0.8 ± 1.04 and + 7.2 ± 2.95 V, respectively
(Fig. 3(d)). The increase in on/off ratio and positive VTH shift are at-
tributed to the suppression of oxygen vacancy formation by the Ga
doping and subsequent reduction in carrier concentration [20], in-
dicating that the Ga plays a critical role in controlling the electrical
properties of IGO NW FETs. In addition, the subthreshold character-
istics were also significantly improved by Ga doping as summarized in
Table S1 in the ESM. While the In2O3 NW FET exhibited an SS value of
5.91 V/decade, the IGO3 and IGO4 NW FETs showed SS values of 0.73
and 0.36 V/decade, respectively. The subthreshold characteristics are
closely related with the maximum density of interfacial trap states (Nt)
between the active channel layer and gate dielectric, by the following
equation [22],
SS × log(e ) C
Nt = ⎡ − 1⎤ i ,
⎢
⎣ kT / q ⎥
⎦q (1)
where k is the Boltzmann constant, q is the unit charge, and T is the
temperature. The Nt values of In2O3, IGO3, and IGO4 NW FETs were
1.06 × 1013, 1.22 × 1012, and 5.60 × 1011/(cm2·eV), respectively,
indicating that the density of interfacial trap states was significantly
reduced by the Ga doping. The field-effect mobility is another im-
portant factor determining the performances of the FETs. As the mo-
bility is related with the carrier concentration, it is likely that some
degradation might occur upon the increase in Ga content in the In2O3
NWs. Fig. 3(b) and (f) show the variation and distribution of field-effect
mobility as a function of Ga concentration, respectively. The mobility
tends to decrease with the increase in Ga content, but the decrease was
not substantial. For example, the average saturation mobilities of IGO3
and IGO4 FETs were 6.0 ± 0.63 and 3.1 ± 0.66 cm2/(V·s), respec-
tively, which are slightly lower than that of the pristine In2O3 NW FETs.
Furthermore, compared to that of the conventional film-type IGO3
FETs, the IGO3 NW FETs had reasonably high mobility (Fig. S3 in the
ESM). To conclude, upon the insertion of Ga into In2O3, although the
field-effect mobility could be reduced to some extent, the improvements
in on/off ratio, VTH, and subthreshold characteristics are substantial,
particularly for the IGO3 and IGO4 NW FETs.
In oxide FETs, light-induced instability is one of the critical issues
affecting their operational stabilities, which possibly originates from
the deep states in the bandgap [23]. To investigate the light-induced
instability of the oxide NW FETs, IGO3 and IGO4 NW FETs were sub-
jected to an NBIS test. Figs. 4(a) and S4a in the ESM show the variation
in VTH and transfer curves under the NBIS for stress times up to 5760 s,
respectively (VGS = −30 V, light power intensity = 0.85 mW/cm2).
Relatively good stabilities with ΔVTH of +0.30 V and +2.54 V were
observed in IGO3 and IGO4 NW FETs at a stress time of 5760 s, re-
spectively. The stable operation under the NBIS can be attributed to the
reduced light absorption area of the IGO NW channel compared to that
of the film-type channel layer. The effective channel area of IGO3 NWs
covering the surface was approximately 14.4%, as shown in Fig. S5 in
the ESM. Also, the stabilities under the PBS were evaluated. Figs. 4(b)
and S4b in the ESM show the variations in VTH and transfer curves
under PBS (VGS = +30 V) condition, respectively. The IGO3 and IGO4
NW FETs exhibited ΔVTH of −1.17 V and +0.10 V at the stress time of
5760 s, respectively, showing that the IGO NW FETs are relatively
stable under the continuous bias conditions.
Using the optimized oxide NW channel layer, DG NW FETs were
fabricated by forming a high-k ion-gel film as the top gate dielectric
layer. One of the key aspects of using the ion-gel dielectric is the low-
voltage operation due to its high dielectric constant [24]. In addition,
owing to its simple fabrication and room-temperature processability,
the DG NW FETs can be easily realized by simply forming the ion-gel
film on top of the oxide NW channel layer. Fig. 5(a) shows the sche-
matic device structure and an optical image of DG IGO3 NW FETs. Prior
to the DG operation, we analyzed the electrical characteristics of the
J. Kim, et al.
Fig. 3. (a) Transfer characteristics of SG In2O3 and IGO NW FETs with different Ga concentrations. The variations of (b) saturation field-effect mobility, (c) current
on/off ratio, and (d) VTH as a function of Ga concentration. (e) Output curves of SG In2O3 and IGO NW FETs with different Ga concentrations. (f) Statistical data of
saturation field-effect mobility of SG In2O3 and IGO NW FETs.
Fig. 4. (a) The variation of threshold voltage (VTH) in IGO3 and IGO4 NW FETs
under negative gate-bias illumination stress (NBIS) condition. During the NBIS
test, the light intensity and the gate bias were maintained at 0.85 mW/cm2 and
−30 V, respectively. (b) The variation of VTH in IGO3 and IGO4 NW FETs under
positive bias stress (PBS) condition. During the PBS test, the gate bias was
maintained at +30 V.
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Applied Surface Science 515 (2020) 145988
ion-gel-gated IGO3 NW FETs. Fig. 5(b) shows the capacitance–voltage
characteristics of EMIM:TFSI ion-gel film. The corresponding areal ca-
pacitance was ~1.3 µF/cm2 (at 100 Hz), which is much higher than that
of the SiO2 gate dielectric (17.3 nF/cm2, thickness of 200 nm). Fig. 5(c)
shows the transfer characteristics of ion-gel-gated IGO3 NW FET (VD of
2 V). The IGO NW FET can be operated in the gate bias range of −2 to
+2 V with an on/off ratio of 103–104. The field-effect mobility was
6.5 ± 1.11 cm2/(V·s) (Fig. 5(d)), similar to that of the device operated
with the SiO2 gate dielectric. Fig. 5(d) shows the statistical data of sa-
turation mobility, VTH, and SS of the ion-gel-gated IGO3 NW FETs.
Regarding the DG FET, the control of VTH is possible by the interplay
between the two gate biases (VG1 and VG2) [25]. In addition, an FET
with high apparent mobility can be achieved by utilizing the extended
channels formed at both interfaces with the gate dielectrics [26]. In our
study, the DG FET was operated using the bottom SiO2 and top ion-gel
films as the gate dielectrics. Fig. 6(a) shows the transfer characteristics
of DG IGO3 NW FETs. The bottom gate bias (VG1) was swept in the
range from −30 to +30 V at different top gate biases (VG2 = −2, −1,
0, 1, 2 V). The device did not exhibit current modulation at VG2 of −2
V. However, with the increase in VG2 above −1 V, the on-state
J. Kim, et al.
Fig. 5. (a) A schematic device structure and an optical microscope image of a DG IGO3 NW FET using an EMIM:TFSI ion-gel film as the top gate dielectric. (b) Areal
capacitance-voltage data of the ion-gel gate dielectric film measured at 100 Hz. (c) Transfer characteristics of ion-gel-gated IGO3 NW FETs (single gate mode,
VD = 2 V). The grey color line shows the gate leakage current (IG) of the device. (d) Statistical data of field-effect mobility, VTH, and subthreshold slope (SS) of ion-
gel-gated IGO3 NW FETs.
emerged, showing the modulation of the carrier concentration by the
bottom gate bias. Such behavior can be modeled as illustrated in
Fig. 6(c). When the top gate bias is −2 V, the electron double layer
formed by the ion-gel suppresses the channel formation in the IGO3 NW
layer. As the areal capacitance of the top gate dielectric was con-
siderably larger than that of the bottom layer SiO2, the sweeping of VG1
up to +30 V had a negligible effect on the electron accumulation (no
current modulation). On the other hand, when the top gate was in-
creased higher than −1 V, current modulation is achieved by the in-
terplay between VG1 and VG2. Particularly, at VG2 = +2 V, electrons
started to accumulate in the IGO3 NW channel layer at VG1 > −15 V.
The FET then reached an on-state at VG2 of approximately 0 V. The
apparent mobilities calculated at VG2 of +1 V and +2 V were 32.5 and
35.1 cm2/(V·s), respectively, significantly higher than those of SG IGO3
NW FETs. Fig. 6(b) shows the corresponding variation in VTH as a
function of VG2, where the VTH values were obtained in both forward
(−30 V → +30 V) and reverse (+30 V → −30 V) sweepings. Simi-
larly, Fig. 6(d) shows the transfer characteristics when the asymmetric
operation was carried out by sweeping VG2. In this case, the IGO3 NW
FET did not exhibit current modulation up to VG1 of −15 V. However,
at VG1 ≥ 0 V, a clear current modulation is observed with apparent
field-effect mobilities of 5.6–7.6 cm2/(V·s) and on/off ratio of ~104.
Fig. 6(e) and (f) show the variations in VTH as a function of VG1 and the
operation mechanism, respectively. At negative VG1, in the range of
−30 V ≤ VG1 ≤ −15 V, the electron accumulation by VG2 is inhibited
by the high negative bottom gate bias. Whereas, when VG1 was higher
than 0 V, a sufficient number of electrons are accumulated providing a
VG2-dependent current modulation. In summary, by employing the DG
structure in the IGO NW FETs, significantly enhanced field-effect mo-
bility could be achieved by the utilization of double channels formed at
both interfaces with the gate dielectrics.
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Applied Surface Science 515 (2020) 145988
4. Conclusion
We fabricated high-mobility DG IGO NW-based FETs by using
crystalline IGO3 NW as the channel layer and a high-k ion-gel film as
the top gate dielectric layer. The optimization of oxide NW density,
thermal annealing temperature, and the Ga doping concentration was
carried out to evaluate the influences from each process or material
parameter. The IGO NW FETs with an optimal In:Ga ratio exhibited a
high saturation field-effect mobility, high on/off ratio, low SS, and VTH
of approximately 0 V. Furthermore, the low-voltage operating DG IGO3
NW FETs were successfully realized by using high-k ion-gel film as the
top gate dielectric layer. We believe that these findings can be ex-
tensively utilized in the development of oxide-NW-based electronic
devices and active-matrix electronics.
CRediT authorship contribution statement
Jaeyoung Kim: Conceptualization, Investigation, Writing - original
draft. Woobin Lee: Conceptualization, Investigation, Writing - original
draft, Visualization. Seungbeom Choi: Conceptualization,
Methodology. Kyung-Tae Kim: Investigation. Jae-Sang Heo:
Investigation. Sung Kyu Park: Conceptualization, Methodology,
Investigation, Writing - original draft. Yong-Hoon Kim:
Conceptualization, Methodology, Investigation, Writing - original draft,
Visualization.
Declaration of Competing Interest
The authors declare that they have no known competing financial
interests or personal relationships that could have appeared to influ-
ence the work reported in this paper.
J. Kim, et al. Applied Surface Science 515 (2020) 145988

Fig. 6. (a) Transfer characteristics of DG IGO3 NW FETs when the bottom gate bias (VG1) was swept in the range of −30 V ~ +30 V at different top gate biases
(VG2 = −2, −1, 0, 1, 2 V). (b) The variation of VTH as a function of VG2 bias. The VTH values are obtained in both forward (−30 V → +30 V) and reverse (+30 V →
−30 V) sweep conditions. (c) Corresponding operation mechanism of the DG IGO3 NW FETs (VG1 forward sweep). (d) Transfer characteristics of DG IGO3 NW FETs
when the top gate bias (VG2) was swept in the range of −2 V ~ +2 V at different bottom gate biases (VG1 = −30, −15, 0, 15, 30 V). (e) The variation of VTH as a
function of VG2 bias. The VTH values are obtained in both forward (−2 V → +2 V) and reverse (+2 V → −2 V) sweep conditions. (f) Corresponding operation
mechanism of the DG IGO3 NW FETs (VG2 sweep).

Acknowledgements
J.K. and W.L. contributed equally to this work. This study was
supported by the National Research Foundation (NRF) of Korea, grant-
funded by the Korea Government (Ministry of Science and ICT; NRF-
2017R1E1A1A01077189, NRF‐2019M3F3A1A02071601 and NRF-
2019R1A2C2002447).
Appendix A. Supplementary material
Supplementary data to this article can be found online at https://
doi.org/10.1016/j.apsusc.2020.145988.
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