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use ieee.std_logic_1164.all;
entity disp is port(
clk,reset : in std_logic;
x: in std_logic_vector(1 downto 0);
y: out std_logic; ---Entrega dulce si es
1
z: out std_logic_vector(2 downto 0)); ---Cambio
end disp;
begin
process(ep,x) begin
case ep is
when A => y <= '0'; ---Indica cuando despachara el dulce
if(x="00")then ---No ingreso nada
es <= A;
elsif(x="01")then ----Ingreso 1 peso
es <= B;
end case;
end process;
sec:process(clk,reset)
begin
if(reset='1')then
ep <= A; z <="00";
elsif(clk'event and clk='1')then
ep<=es;
end if;
end process;
end disp;