IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—II: EXPRESS BRIEFS, VOL. 52, NO.

9, SEPTEMBER 2005 591

High-Performance Error Amplifier for Fast

Transient DC–DC Converters
Jeongjin Roh

Abstract—A new error amplifier is presented for fast transient

response of dc–dc converters. The amplifier has low quiescent cur-
rent to achieve high power conversion efficiency, but it can supply
sufficient current during large-signal operation. Two comparators
detect large-signal variations, and turn on extra current supplier if
necessary. The amount of extra current is well controlled, so that
the system stability can be guaranteed in various operating con-
ditions. The simulation results show that the new error amplifier
achieves significant improvement in transient response than the
conventional one.
Index Terms—Boost converter, dc–dc converter, error amplifier,
operational transconductance amplifier (OTA), pulsewidth modu-
lation (PWM), transient response.

I. INTRODUCTION

T HE switch-mode dc–dc converters have been widely used

in power supply systems and are becoming a common
building block in modern VLSI systems [1]. Especially for
the growing number of battery-operated portable systems, the
dc–dc converter is an essential block since the linear voltage
regulator cannot be used because of its low power efficiency.
CMOS controller ICs for dc–dc converters should be
designed for low quiescent current consumption and for rea-
sonably high-speed operation. However, the low-power and
high-speed requirements are contradicting, which make the
circuit design a challenging task.
Fig. 1 illustrates a simplified structure of a current-mode
boost converter [2]. Its main function is to convert input dc
voltage to higher output dc voltage with minimum power loss.
The converter is composed of a power stage and feedback
control circuits. is a battery voltage, which supplies input dc
voltage, and is the boosted output dc voltage. The inductor
, diode , and output capacitor are off-chip components
because of their large sizes. Resistors and sense the
output voltage and generate the scaled output voltage to the
error amplifier. is the load of the dc–dc converter, which
could be any digital or analog systems.
All other blocks are integrated in a single controller IC. The
clock in Fig. 1 generates short pulses at a predetermined pe-
riod, so that the SR latch can be set high by the pulses. The
reset timing of the latch is controlled by the comparator, which
compares the output voltage of the error amplifier with the drain
voltage of M1. The drain voltage of M1 is proportional to the
current flowing, so if the scaled output voltage is lower than
Manuscript received June 16, 2004; revised January 6, 2005. This work was
supported by the Research Fund of Hanyang University (HY-2004-S).
The author is with the Department of Electrical and Computer Engineering,
Hanyang University, 426-791 Ansan, Korea (e-mail: jroh@hanyang.ac.kr).
Digital Object Identifier 10.1109/TCSII.2005.850521
1057-7130/$20.00 © 2005 IEEE
Fig. 1. Block diagram of a dc–dc boost converter.
, then the reset time of the latch will be delayed for more
current to charge the output capacitor . In effect, the latch
generates a pulsewidth modulation (PWM) signal which is con-
trolled by the feedback loop. In general, M1 is implemented as
a very large transistor with its turn-on resistance of less than 1
to reduce power loss of M1 itself. The error amplifier is an im-
portant block for fast and accurate operation of the system. It de-
tects and amplifies the difference between the reference voltage
and the scaled output voltage. Then, the detected error voltage
is processed by the compensator for the stability of the dc–dc
converter [2], [3].
II. STABILITY OF DC–DC CONVERTERS
Since switch-mode dc–dc converters are nonlinear circuits,
linearized small-signal models are required to analyze the sta-
bility of the feedback loop. The current-mode boost converter
has two poles and a right-half plane (RHP) zero [2]. The second
pole is well separated from the dominant pole and is close to
the switching frequency. Therefore, a simple first-order model
with a single pole and a single RHP zero can be used as a
close approximation to the accurate model [2]. We use the ac-
curate model for the computer analysis of stability to decide the
frequency compensation parameters. However, the first-order
model is used for hand calculation because of too much compli-
cation of the accurate model, which does not give much intuition
about the behavior of the circuit. The following equation shows
592 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—II: EXPRESS BRIEFS, VOL. 52, NO. 9, SEPTEMBER 2005

Fig. 2. Control-to-output transfer function, G (s). Fig. 3. Compensated error amplifier, G (s ) .

the first-order model of the control-to-output transfer function
:

(1)

where equals the duration of the low PWM duty cycle [2].
The main advantage of the current-mode converter is its
simpler dynamics. The small-signal control-to-output transfer
function contains one less pole than that of the voltage-
mode converter. Therefore, simple robust output voltage control
can be obtained without the use of a compensator lead network.
The simple proportional-plus-integral (PI) compensation is
commonly used in current-mode converters, which is also
used here.
Fig. 2 shows the Matlab plot of by the accurate model
[2]. It shows that the uncompensated system has its crossover
frequency at 10 kHz. The second pole is at 300 kHz, which is
not represented in the simple first-order model in (1). Fig. 3 is Fig. 4. Total feedback loop, G (s ) .
a frequency response of the PI compensation circuit to
attain a crossover frequency at one-twentieth of the switching
frequency [2].
The frequency characteristic of the compensated error ampli-
fier is combined into the total feedback loop characteristic of
a dc–dc converter. Overall, the locations of the pole and zero
shape the feedback loop characteristic of the dc–dc converter to
achieve a sufficient phase margin [3]. The loop gain equation of
the total feedback loop is shown in
Fig. 5. Compensated OTA.
(2)
Fig. 5 is an example of a compensation circuit [3], which is
and is plotted in Fig. 4. The current sense resistance is in-
used in our circuit design with the proposed error amplifier. The
cluded in the equation because (1) has its input as a control
two off-chip capacitors and a resistor determine the location of
current.
a zero and a pole.
The value of is 0.2 in our circuit design, which is the
turn-on resistance of the nMOS switch, and other circuit param-
eters are summarized in Section IV. The frequency response in III. DESIGN OF THE ERROR AMPLIFIER
Fig. 4 shows the phase margin of 59 , which is very close to the A conventional current mirror operational transconductance
optimal phase margin of 60 . amplifier (OTA) in Fig. 6 is a reasonable candidate for the error
ROH: HIGH-PERFORMANCE ERROR AMPLIFIER FOR FAST TRANSIENT DC–DC CONVERTERS
Fig. 6. Conventional OTA.
amplifier. The design of the circuit is done by using a stan-
dard 0.5- m CMOS process with threshold voltages of 0.9
and 0.7 V for pMOS and nMOS transistors, respectively. The
transistors are implemented by placing multiple unit transis-
tors in parallel for better device matching, rather than making
a device wider. The width and length size of an unit pMOS
transistor is m m and that of a unit nMOS tran-
sistor is m m. The below each transistor name in
Fig. 6 shows the number of multiple unit transistors. For these
transistor sizes, the overdrive voltages of pMOS transistors are
about 200 mV and those of nMOS transistors are about 140 mV.
Since the tail current of the OTA is designed as 1.2 A, the drain
currents of input transistors M1 and M2 are 0.6 A each. Since
the transconductance, which can be represented in the following
equation, is important for better performance of OTA, the widths
of input differential pair and are increased by making
: controlled by the switches M10 and M11, which are driven
(3)
Therefore, the input transistors have a relatively low overdrive
voltage of about 120 mV.
Since the current mirror ratio for the output stage is 20, the
maximum output current is , which is 24 A. This max-
imum current can be increased by higher current mirror ratio,
but it will also increase the quiescent current of the amplifier,
which is not desirable in dc–dc converters.
For high dc gain of the amplifier, the OTA’s output stage can
be modified into a cascode circuit [1], but at the cost of limited
output swing. Cascoding is not used in our circuit to have a
simpler circuit to understand our proposed technique.
The current mirror OTA has a limited output current and, as
a result, low slew rate such as
(4)
where is the current mirror ratio of M4 and M6 and is
the load capacitance. If or is increased, it will directly
violate the requirement of low quiescent current.
593
Fig. 7. New OTA.
Fig. 8. Transconductance of the conventional and new OTA.
In order to increase the performance, a new OTA architecture
is developed as in Fig. 7. Without the transistors M9–M12,
the amplifier is same as the conventional one in Fig. 6. How-
ever, the new OTA has an extra current driving capability
by their respective comparators, PDRIVE and NDRIVE. The
comparators have built-in offset voltages, which make the
switches turned-off in quiescent condition. When the scaled
dc–dc converter output voltage differs significantly from the
desired reference voltage, either PDRIVE or NDRIVE will
activate its respective switch M10 or M11, which have the
width and length size of m m. The activated switch
will enable extra current to flow.
Recently, a similar amplifier architecture was proposed in
[4] and [5] for flat-panel display application, which has about
600-pF load capacitance. Conceptually, their idea is similar to
ours, if M9 and M12 are removed, in the sense that extra cur-
rent is supplied during large-signal operation. However, direct
application of their architecture will lead to instability in dc–dc
converters, as will be explained later.
The simplified voltage–current characteristic of the error am-
plifier is shown in Fig. 8, where its slope is the transconductance
. The dotted line is the characteristic of the conventional
OTA, while the solid line is that of the new OTA. If the input
signal to the error amplifier is small in stable operation, the
transconductance of the error amplifier will be
(5)
594 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—II: EXPRESS BRIEFS, VOL. 52, NO. 9, SEPTEMBER 2005
where the transconductance can be expressed as in (3). The new
OTA has increased transconductance when the input signal is
large. The new transconductance in large-signal operation will
be
(6)
The boundary for in Fig. 8 is determined by the offset
voltage of the comparators PDRIVE and NDRIVE. The
offset voltage is controlled by the built-in mismatch of the input
differential pair of the comparators. For the designed error am-
plifier in Section IV, is set to 30 mV. Since the error ampli-
fier’s input is the scaled output voltage by and in Fig. 1,
which are 500 and 100 k , respectively, the output voltage vari-
ation of the dc–dc converter should be larger than to turn on
the extra current supplier. The architecture of the conventional
OTA is also used for the design of the comparators.
The contribution of this study is twofold. First, the slewing
problem of the error amplifier is solved, and, as a result, the
dc–dc converter has improved large-signal behavior as demon-
strated in next section. As mentioned earlier, the conventional
OTA circuit may cause a slewing problem and lead to slow
transient response. We overcome this problem by employing a
high-performance error amplifier.
Second, the extra current supplier is under complete control
in our amplifier. This is the significant improvement from the
high slew amplifiers in [4] and [5] for the stable operation of
dc–dc converters. That is, if M9 and M12 are removed in Fig. 7,
M10 and M11 will act as a current supplier, which makes the
amplifier similar to that of [4] and [5]. For a simple buffer ap-
plication, the large load capacitance, introduced by flat-panel
display, makes the buffer a single pole system. This enables
the buffer stable even if varies. However, since dc–dc con-
verters have several poles and zeros with complicated compen-
sation, any variation in the compensator gain may affect the
overall feedback stability. For example, if the current supplier
operates in triode region, the transconductance will be
. The value of is critical since
determines the phase margin [3] of the feedback system,
where is the total transconductance of the OTA including
the effect of such as
(7)
In (7), is the gain of the comparators that controls the
current driving transistors. The transconductance in the triode
region heavily depends on , which is same as
for M11 or for M10, if we assume the architecture
of [4] and [5]. Therefore, as the output voltage of the error am-
plifier changes, the overall feedback characteristics will change
as well. Also, since most controllers for dc–dc converters use
the boosted dc–dc output voltage as a power supply of the con-
troller itself, the variation of of a controller would be very
wide depending on wide application of the dc–dc converters.
This observation explains why a stable dc–dc converter in a cer-
tain condition becomes unstable in different conditions, as will
be demonstrated in next section.
Therefore, it becomes mandatory to implement a stable error
amplifier regardless of and variations. Our new OTA
has well controlled extra current, which is determined by the
Fig. 9. Transient response with a conventional OTA.
current mirror ratio M9/M7 and M12/M4 in Fig. 7. Since the
OTA has controlled current capability, the trasconductance of
the amplifier is also controlled by current mirrors. Therefore,
is always well controlled regardless of the variations in
and .
The available output swing of the error amplifier is limited
by the overdrive voltage of the output transistors. In order to
have large output swing, the cascode output stage such as in
[1] is avoided in our design. Instead of using cascode stage,
we increased the length of the output current mirror transistors
– and to increase the output impedance. These large
transistors also increase the parasitic capacitors, which are not
desirable in general designs. However, even a large parasitic ca-
pacitor is negligible in the compensator architecture in Fig. 5
since it already has huge off-chip capacitors.
IV. SIMULATION RESULTS
The HSPICE simulation results are shown in this section with
0.5 m CMOS process parameters. The normal quiescent output
current of the new error amplifier is designed as 14 A, and the
maximum output current can be increased up to 48 A as was
explained in previous section. The dc–dc converter is designed
with H and F at its switching frequency of
500 kHz. The compensation circuit in Fig. 5 has k ,
nF, and pF. The sizes of these passive
components are common values in commercial high-frequency
dc–dc converters.
In order to evaluate the load regulation of the controller, load
current is changed from 100 to 300 mA at 1 ms. For the step
change of load current, the large output capacitor loses its
charge, and therefore its voltage level drops. The error ampli-
fier detects the voltage drop, and increases the compensator
output voltage, which in turn increases the PWM pulse width. In
order to achieve fast transient response, the compensator output
voltage should be increased swiftly.
Fig. 9 is from the simulation with the conventional error am-
plifier in Fig. 6, which is similar to the error amplifier in [1]. We
can observe large dc–dc output voltage drop and slow voltage
ROH: HIGH-PERFORMANCE ERROR AMPLIFIER FOR FAST TRANSIENT DC–DC CONVERTERS
Fig. 10. Transient response with a proposed OTA.
Fig. 11. Line regulation with a proposed OTA.
recovery. When the load current is increased to even larger cur-
rent than 300 mA, the output voltage drop is more significant.
The transient response is also measured with the new error
amplifier for the same step change of load current from 100 to
300 mA at 1 ms. Fig. 10 shows that the output voltage drop is
significantly less than that of the conventional circuit. As the
output voltage variation becomes large, the new error amplifier
supplies extra current for fast settling. After the output voltage
is recovered and as the dc–dc output voltage approaches the
target, the extra current driving circuit turns off. In this case, the
output of the compensator is the charged voltage of the capaci-
tors, which is not high enough yet. Therefore, the dc–dc output
voltage drops slightly because of the PWM duty ratio change.
Then, it settles to the final voltage without the help of the extra
current supplier, as in the conventional circuit.
For the line regulation test, a step input between 2.0 and
2.4 V is applied like the lower trace in Fig. 11 with the dc–dc
595
Fig. 12. Unstable output voltage when too much extra current is supplied.
converter’s load resistance set to 10 . The output voltage,
which is the upper trace in Fig. 11, experiences a sudden change
when the input voltage changes, but it recovers immediately
by the operation of the error amplifier and other feedback
circuitry. As it was emphasized, the maximum extra current
and the transconductance of the error amplifier should be well
controlled for stable operation of the dc–dc converters. The
of the error amplifier shown in Fig. 8 is increased five
times to show the possibility of output voltage oscillation as
in Fig. 12. The output voltage does not stabilize in this case,
and keeps oscillating.
V. CONCLUSION
Fast transient response and low quiescent current are two
important, but contradicting, requirements of the controllers
in dc–dc converters. In order to satisfy both requirements,
an efficient amplifier architecture is developed. The designed
error amplifier effectively increases the supply current for
large-signal variations, while maintains small quiescent current
during normal operation. In order to maintain stability of the
system, the transconductance of the error amplifier is well
controlled in our design. Simulation results prove the fast and
stable operation of a dc–dc converter.
REFERENCES
[1] C. F. Lee and P. K. T. Mok, “A monolithic current-mode CMOS DC-DC
converter with on-chip current-sensing technique,” IEEE J. Solid-State
Circuits, vol. 39, no. 1, pp. 3–14, Jan. 2004.
[2] R. W. Erickson and D. Maksimovic, Fundamentals of Power Elec-
tronics, 2nd ed. Norwell, MA: Kluwer, 2001.
[3] A. I. Pressman, Switching Power Supply Design, 2nd ed. New York:
McGraw-Hill, 1998.
[4] P.-C. Yu and J.-C. Wu, “A class-B output buffer for flat-panel-display
column driver,” IEEE J. Solid-State Circuits, vol. 34, no. 1, pp. 116–119,
Jan. 1999.
[5] C.-W. Lu and C. L. Lee, “A low-power high-speed class-AB buffer am-
plifier for flat-panel-display application,” IEEE Trans. Very Large Scale
Integr. (VLSI) Syst., vol. 10, no. 4, pp. 163–168, Apr. 2002.