Documentos de Académico
Documentos de Profesional
Documentos de Cultura
Microcontroller
CS433
Processor Presentation Series
Prof. Luddy Harrison
z Range of
Performance Products
Data
Processing
V850E2
(under dev.)
Competitors class
32 bit
V850E1
3-4 times the performance of the
microprocessors 50MHZ
z
same frequency when compared to
16-bit Microprocessors compatible with high
end machine class V850 33MHZ
Competitors
z Up to 168K high-speed instruction 16 bit
microprocessors
RAM, as well as 8 KB instruction
cache memory and 8 KB of data V850ES
V850
20MHZ
cache memory.
z Range of Applications:
z Digital consumer applications
z Inverters
z Industrial equipment
z Printers
z fax machines
z Etc… V850E/Mxx
Car
High End Lineup
More powerful, high performance memory
interface
QA
V850E/xxx
V850E1 Core
V850ES/xxx Industry
V850ES/SG2 V850ES/SJ2
CAN
V850E/RS1 V850E/CA2
V850E/CG2
CAN &
V850ES/DG2 V850ES/DJ2
Motor
Control V850E/IA1
Low Power
V850/SA1
V850ES/SA2
Core Package
CPU V850E1 Package Code GM-UEU
Instructions 83 Type LQFP
Internal Bus [bits] 32 Pins 176
External Bus [bits] 16-A ug Pin Pitch[m m ] 0.5
Size 24x24
CPU
Instruction
PC ASTB
R Prefetch
Queue
O (2 words)
OSTB
M 32 bit R/W
Barrel
Shifter Multiplier UBEN
16X16 -> 32
32X32 -> 64 LBEN
System
Registers
WAIT
Bus control
General Unit Add. Bus
R
ALU
Registers MUX ACK
A (32bitsx32)
data bus
M
HLDRQ
HLDAK
Internal Peripheral
Bus
FFFFEFFFH
Internal RAM
z Linear address up to 4 GB
total
4 GB Linear
Internal ROM/PROM/
Flash Memory
00000000H
z External Memory:
The BCU controls a DRAM controller (DRAMC), page ROM controller (ROMC), and DMA controller
(DMAC) and performs external memory access and DMA transfer.
¾ SDRAM controller
¾ SRAM Controller
¾ Page ROM controller (ROMC)
This controller supports accessing ROM that includes the page access function (i.e. Flash)
¾ DMA controller (DMAC)
This controller controls data transfer between memory and I/O instead of the CPU. There are three
bus modes: single transfer, single step transfer, and block transfer.
Time Flow
(State)
System Clock
Instr. 1 IF ID EX MEM WB
Instr. 2 IF ID EX MEM WB
Instr. 3 IF ID EX MEM WB
Instr. 4 IF ID EX MEM WB
Instr. 5 IF ID EX MEM WB
Instr. 6 IF ID EX MEM WB
Instr. 7 IF ID EX MEM WB
Instr. 8 IF ID EX MEM WB
z Data Representation:
¾ Integer
¾ Unsigned Integer
¾ Bit
z Operand address
¾ Register addressing (Register is accessed as operand)
¾ Immediate addressing (Contained directly in instruction)
¾ Based addressing
¾ Bit addressing (accessing 1 bit directly)
SST.W Store Word SHL Shift Logical Left MULHI Multiply Half-Word Immediate
ST.B Store Byte SHR Shift Logical Right DIVH Divide Half-Word
SATSUB Saturated Subtract JARL Jump and Register Link STSR Store System Register
SATSUBI Saturated Subtract Immediate Bcond Branch on Condition Code TRAP Trap
SATSUBR Saturated Subtract Reverse Bit manipulation instructions RETI Return from Trap or Interrupt
z Range of Applications:
z Digital consumer applications
z Inverters
z Industrial equipment
z Printers
z fax machines
z Etc… V850E/Mxx
Car
High End Lineup
More powerful, high performance memory
interface
QA
V850E/xxx
V850E1 Core
V850ES/xxx Industry
z DSP Usage
¾ Barrel shifter, Multiplier Unit, 5 stage pipeline, DMA controller
C-Code:
int main( void )
{
int *p = array_1;
int *q = array_2;
*(p+10)= *(q +0) + *(q +1) + *(q +2) + *(q +3) + *(q +4) + *(q +5) + *(q+6) + *(q +7) + *(p +0) +
*(p +1) + *(p +2) + *(p +3) + *(p +4) + *(p +5) + *(p+6) + *(p +7);
return *(p+11);
}
ASM-Code:
-------------------------
MOVHI hi1(array_2+0-?BREL_BASE-0x8000),gp,r1
MOVEA lw1(array_2+0-?BREL_BASE-0x8000),r1,r1
MOVHI hi1(array_1+0-?BREL_BASE-0x8000),gp,r5
MOVEA lw1(array_1+0-?BREL_BASE-0x8000),r5,r5
LD.W (+0)[r1],r6
LD.W (+4)[r1],r7
CS433 Prof. Luddy Harrison Copyright 2005 University of Illinois 21
V850 & IAR O.S.
z Size optimized FIR Filter
- Loops n times through the mac-code.
- Designed for V850,
- Strategy imposes an instruction time penalty of
- One clock for the compare with n instruction and two (V850) clocks for the discarded pipeline when the branch is taken (n-1 times).
- Implementing a pointer to the sample and another one to the coefficients
z 176-Pin PlasticLQFP
z 0.5 mm pitch
z 24x24 mm
z 1.4 mm thick
z 240-Pin FBGA
z 0.8 mm pitch
z 16x16 mm
z 1.48 mm thick
PCT3 UUWR/UUBE/UUDQM
PCT4 RD
PCT5 WE/WR
PCT7 BCYST
ULDQM Output Output disable/write mask signal output for SDRAM(second byte (D16 to D23))
ULWR Output External data bus write strobe signal output (second byte(D16 to D23))
UUBE Output External data bus byte enable signal output (highest byte(D24 to D31))
UUDQM Output Output disable/write mask signal output for SDRAM(highest byte (D24 to D31))
UUWR Output External data bus write strobe signal output (highest byte(D24 to D31))
z In-circuit emulator
z IE-V850E1-CD-NW
z Compact PC card-type emulator
z Supports flash programmer functions
z IE-V850ESK1-ET, IECUBE
series
z Integrate emulation board into emulator body
z USB I/F for PC (Hi-Speed USB I/F, USB1.1)
z Real-time RAM monitor, time measurement
function, USB_IF
¾http://www.necel.com/micro/english/v850/product/cpucore.html