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Analysis
v3 v2 VS
UES-FIA-EIE-AEL115 Ciclo I-2016
5) Aplicar LCK/KCL a cada Supernodo
del circuito.
Se debe tener en cuenta que pudiese existir
mas de un Supernodo simple, doble, etc.
en el ckto…
6) Resolver el arreglo matricial para
determinar los potenciales respectivos
asociados a cada nodo.
Continuar con el análisis de la red, si
es necesario.
UES-FIA-EIE-AEL115 Ciclo I-2016
Ejemplo: Plantear las ecuaciones de Análisis de Nodos
v2 v2 v1
(1.4) 0
1 5
-v1 6v2 7 (b)
W.H. Hayt, Jr., J.E. Kemmerly, S.M. Durbin, Engineering Circuit Analysis, Sixth Edition.
UES-FIA-EIE-AEL115 Copyright ©2002 McGraw-Hill. All rights reserved. Ciclo I-2016
Reescribiendo las ec. (a) y (b) en forma matricial, se
tiene:
7 2 v1 31
1 6 v 7
2
cuya solución es:
v1 5.0 [V]
v2 2.0 [V]
un método de solución directa es aplicando
el criterio de la matriz inversa, o sea:
a x b x a b
-1
UES-FIA-EIE-AEL115 Ciclo I-2016
Example (Supernode):
(a) The circuit of Example 4.2 with a 22 V source in place of the 7-W resistor.
(b) Expanded view of the region defined as a supernode; KCL requires that all
currents flowing into the region must sum to zero, or we would pile up or run
out of electrons.
W.H. Hayt, Jr., J.E. Kemmerly, S.M. Durbin, Engineering Circuit Analysis, Sixth Edition.
UES-FIA-EIE-AEL115 Copyright ©2002 McGraw-Hill. All rights reserved. Ciclo I-2016
Reescribiendo (a), (b) y (c) como una matriz, se tiene:
7 4 3 v1 132
35 80 27 v 1680
2
0 1 1
v3 22
cuya solución es:
15
v1 1.071 [V]
14
21
v2 10.5 [V]
2
65
v3 32.5 [V]
2
UES-FIA-EIE-AEL115 Ciclo I-2016
Example: Determine the node-to-reference voltages in
the circuit below.
1 0 0 0 v1 12
4 5 1 0 v 28
2
1 10 5 14 v3 0
1 0 5 6 v4 0
Resolviendo la matriz, se obtiene la solución:
v1 12 [V]
v2 4 [V]
v3 0 [V]
v4 2 [V]
W.H. Hayt, Jr., J.E. Kemmerly, S.M. Durbin, Engineering Circuit Analysis, Sixth Edition.
UES-FIA-EIE-AEL115 Copyright ©2002 McGraw-Hill. All rights reserved. Ciclo I-2016
(a) The set of branches identified by the heavy lines is neither a path nor a
loop.
(b) The set of branches here is not a path, since it can be traversed only by
passing through the central node twice.
(c) This path is a loop but not a mesh, since it encloses other loops.
(d) This path is also a loop but not a mesh.
(e, f) Each of these paths is both a loop and a mesh.
W.H. Hayt, Jr., J.E. Kemmerly, S.M. Durbin, Engineering Circuit Analysis, Sixth Edition.
UES-FIA-EIE-AEL115 Copyright ©2002 McGraw-Hill. All rights reserved. Ciclo I-2016
Pasos: Analisis de Mallas:
1) Determinar las mallas formadas en el
circuito y asignar un sentido y dirección
particular a c/u de ellas.
vR iR R (ix iy ) R
UES-FIA-EIE-AEL115 Ciclo I-2016
4) Formar “Supermallas” que
contengan a fuentes de corrientes entre
mallas adyacentes.
Supermalla:
Aquella trayectoria cerrada resultante
luego de abrir las fuentes de corrientes
respectivas que da origen a la supermalla.
De la fuente IS :
i2 i1 I S
De la malla I2 : I2 = -Is
Del circuito: i = I3 – I1
UES-FIA-EIE-AEL115 Ciclo I-2016
Example: Determine the two mesh currents, i1 and i2, in the
circuit below.
i2 i1 6 (2)
De (1) y (2) :
6 14 i1 20
1 1 i2 6
Resolviendo la matriz:
i1 16 / 5 3.2
i2 14 / 5 2.8
UES-FIA-EIE-AEL115 Ciclo I-2016
Example: Find the three mesh currents in the circuit below.
Creating a “supermesh” from meshes 1 and 3: KVL
-7 + 1 ( i1 - i2 ) + 3 ( i3 - i2 ) + 1 i3 = 0 [a]
W.H. Hayt, Jr., J.E. Kemmerly, S.M. Durbin, Engineering Circuit Analysis, Sixth Edition.
UES-FIA-EIE-AEL115 Copyright ©2002 McGraw-Hill. All rights reserved. Ciclo I-2016
Exercise :Find the voltage v3 in the circuit below.
W.H. Hayt, Jr., J.E. Kemmerly, S.M. Durbin, Engineering Circuit Analysis, Sixth Edition.
UES-FIA-EIE-AEL115 Copyright ©2002 McGraw-Hill. All rights reserved. Ciclo I-2016
Ejo. resuelva los ejercicios anteriores aplicando aplicando
análisis de mallas y sus variantes.