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Diseño lógico con VHDL

LÓGICA COMBINACIONAL
Danilo A. García Hansen
Estructura general en VHDL
Módulos o unidades BÁSICAS de diseño
ENTITY (ENTIDAD)
Describe las entradas y salidas al bloque o sistema lógico.

ARQUITECTURE (ARQUITECTURA)
Describe como interactúan las entradas y salidas y como
funciona la lógica interna
ENTITY (ENTIDAD )

Es el bloque elemental de diseño = Son los elementos


electrónicos que lo conforman (Compuertas, sumadores, Flip-
flops, etc...)

Existen diversas formas de representarlo


A nivel de compuertas
Como un diagrama de bloques
Unión de varios bloques funcionales c/u

La Entidad nos permite definir las entradas y salidas del sistema


digital.
Puertos de entrada - salida

▪Modo In
▪Modo Out
▪Modo Inout
▪Modo Buffer
Ejemplos

Se verán algunos ejemplos típicos en la


implementación de sistemas digitales diseñados en
VHDL, con estos ejemplos quedan explícitos los
bloques de ENTIDAD y de ARQUITECTURA; su sintaxis y
varias formas usuales de describir circuitos lógicos.
Funciones Lógicas
----------------------------------------------------------------------------------
---- Design Name: Func_OR
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity funcor is
Port ( X : in STD_LOGIC;
Y : in STD_LOGIC;
Z : out STD_LOGIC);
end funcor;

architecture Arch_OR of funcor is


begin
Z<= X OR Y; -- AND, NAND, NOR, XOR, XNOR, NOT
end Arch_OR;
Funciones Lógicas (ec’s Booleanas)
----------------------------------------------------------------------------------
-- Module Name: FUNCION
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity FUNCION is
Port ( W : in STD_LOGIC;
X : in STD_LOGIC;
Y : in STD_LOGIC;
Z : in STD_LOGIC;
A : out STD_LOGIC;
B : out STD_LOGIC);
end FUNCION;

architecture BOOLEANA of FUNCION is


begin
A<=W AND X;
B<= (X OR Y) NAND Z;
end BOOLEANA;
Funciones Lógicas (if-then-else)
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity FUNCION2 is
Port ( W, X, Y, Z : in STD_LOGIC;
A, B : out STD_LOGIC);
end FUNCION2;

architecture BOOLEANA of FUNCION2 is


Begin

PROCESS (W, X, Y, Z)
BEGIN
IF (W AND X)='1' THEN
A<='1';
ELSE
A<='0';
END IF;

IF ((X OR Y)='1' AND Z='1') THEN


B<='0';
ELSE
B<='1';
END IF;
END PROCESS;

end BOOLEANA;
Tabla de Verdad (1)
----------------------------------------------------------------------------------
-- Module Name: tabla
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity tabla is
Port ( A : in STD_LOGIC_VECTOR (0 to 1);
W : out STD_LOGIC); A(0) A(1) W
end tabla;

architecture Arch_tabla of tabla is


0 0 1
begin
0 1 0
WITH A SELECT
W <= '1' WHEN "00", 1 0 1
'0' WHEN "01",
'1' WHEN "10",
'1' WHEN OTHERS; 1 1 1
end Arch_tabla;
Tabla de Verdad (2)
----------------------------------------------------------------------------------
-- Module Name: tabla
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity tabla2 is
Port ( X, Y : in STD_LOGIC; X Y W
W : out STD_LOGIC);
end tabla2;
0 0 1
architecture Arch_tabla of tabla2 is
begin 0 1 0
W<= ‘1’ WHEN (X=‘0’ AND Y=‘0’) ELSE
‘1’ WHEN (X=‘1’ AND Y=‘0’) ELSE
‘1’ WHEN (X=‘1’ AND Y=‘1’) ELSE
1 0 1
‘0’;
1 1 1
end Arch_tabla;
Tabla de Verdad (3)
----------------------------------------------------------------------------------
-- Module Name: tabla
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity tabla3 is
Port ( X, Y : in STD_LOGIC; X Y W
W : out STD_LOGIC);
end tabla3; 0 0 1
architecture Arch_tabla of tabla3 is
begin 0 1 0
W<= ‘0’ WHEN (X=‘0’ AND Y=‘1’) ELSE ‘1’;
end Arch_tabla; 1 0 1
1 1 1
Multiplexor 2 a 1
---------------------------------------------------------------------------------
-- Design Name: MULTIPLEXOR 2 A 1
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity mux2a1 is
Port ( A : in STD_LOGIC;
B : in STD_LOGIC;
S : in STD_LOGIC;
Y : out STD_LOGIC);
end mux2a1;

architecture Arch_Mux21 of mux2a1 is

Begin

WITH S SELECT
Y<=B WHEN '0',
A WHEN OTHERS;

end Arch_Mux21;
Multiplexor 4 a 1
---------------------------------------------------------------------------------
-- Design Name: MULTIPLEXOR 4 A 1
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity mux4a1 is
Port ( I : in STD_LOGIC_VECTOR (3 downto 0);
S : in STD_LOGIC_VECTOR (1 downto 0);
Y : out STD_LOGIC);
end mux4a1;

architecture arch_mux41 of mux4a1 is


begin
Y <= I(0) WHEN S="00" ELSE
I(1)WHEN S="01" ELSE
I(2)WHEN S="10" ELSE
I(3);
end arch_mux41;
Decodificador 2 a 4
----------------------------------------------------------------------------------
-- Module Name: deco2a4
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity deco2a4 is
Port ( S : in STD_LOGIC_VECTOR (1 downto 0);
Y : out STD_LOGIC_VECTOR (3 downto 0));
end deco2a4;

architecture Arch_deco2a4 of deco2a4 is

begin
Y(0)<= '1' WHEN S="00" ELSE '0';
Y(1)<= '1' WHEN S="01" ELSE '0';
Y(2)<= '1' WHEN S="10" ELSE '0';
Y(3)<= '1' WHEN S="11" ELSE '0';

end Arch_deco2a4;
Decodificador 2 a 4 (Salidas Activas Bajo)
----------------------------------------------------------------------------------
-- Module Name: deco2a4B
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity deco2a4B is
Port ( S : in STD_LOGIC_VECTOR (1 downto 0);
Y : out STD_LOGIC_VECTOR (3 downto 0));
end deco2a4B;

architecture Arch_deco2a4B of deco2a4B is

begin
Y(0)<= '0' WHEN S="00" ELSE '1';
Y(1)<= '0' WHEN S="01" ELSE '1';
Y(2)<= '0' WHEN S="10" ELSE '1';
Y(3)<= '0' WHEN S="11" ELSE '1';

end Arch_deco2a4B;
Comparador de magnitud 4 bits
-- Module Name: comparador - Arch_comp
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity comparador is
Port ( a,b : in STD_LOGIC_VECTOR (3 downto 0);
x, y, z : out STD_LOGIC);
end comparador;

architecture Arch_comp of comparador is

begin
process (a,b)
begin
if (a>b) then
x <= '1';
y <= '0';
z <= '0';
elsif (a=b) then
x <= '0';
y <= '1';
z <= '0';
else
x <= '0';
y <= '0';
z <= '1';
end if;
end process;

end Arch_comp;
Sumador binario de 4 bits (1164)
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity sumador is
Port ( A,B: in STD_LOGIC_VECTOR (3 downto 0);
S : out STD_LOGIC_VECTOR (3 downto 0);
Cout : out STD_LOGIC);
end sumador;

architecture arch_sumador of sumador is


signal C: STD_LOGIC_VECTOR (2 downto 0);
begin
S(0) <= A(0) XOR B(0);
C(0) <= A(0) AND B(0);
S(1) <= A(1) XOR B(1) XOR C(0);
C(1) <= (A(1) AND B(1))OR (C(0) AND (A(1) XOR B(1)) );
S(2) <= A(2) XOR B(2) XOR C(1);
C(2) <= (A(2) AND B(2)) OR (C(1) AND (A(2) XOR B(2)));
S(3) <= A(3) XOR B(3) XOR C(2);
Cout <= (A(3) AND B(3)) OR (C(2) AND (A(3) XOR B(3)));

end arch_sumador;
Sumador binario 4 bits (Std_logic_Arith)
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity SUMADOR is
Port ( A, B : in STD_LOGIC_VECTOR (3 downto 0);
SUMA : out STD_LOGIC_VECTOR (3 downto 0));
end SUMADOR;
architecture ARCH_SUMARITH of SUMADOR is
begin
SUMA <= A + B;
end ARCH_SUMARITH;
Decodificador BCD a 7 segmentos
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity BCD_7_SEG is
Port ( BCD : in STD_LOGIC_VECTOR (3 downto 0);
SAL7SEG : out STD_LOGIC_VECTOR (6 downto 0));
end BCD_7_SEG;

architecture arch_bcd_7_seg of BCD_7_SEG is


begin
process (BCD)
BEGIN
CASE BCD IS
WHEN "0000" => SAL7SEG <= "0000001";
WHEN "0001" => SAL7SEG <= "1001111";
WHEN "0010" => SAL7SEG <= "0010010";
WHEN "0011" => SAL7SEG <= "0000110";
WHEN "0100" => SAL7SEG <= "1001100";
WHEN "0101" => SAL7SEG <= "0100100";
WHEN "0110" => SAL7SEG <= "0100000";
WHEN "0111" => SAL7SEG <= "0001110";
WHEN "1000" => SAL7SEG <= "0000000";
WHEN "1001" => SAL7SEG <= "0000100";
WHEN OTHERS => SAL7SEG <= "1111111";
END CASE;
END PROCESS;
end arch_bcd_7_seg;
Fin parte combinacional

Bibliografía:
VHDL El arte de programar sistemas digitales. David G. Maxinez, Jessica
Alcalá, CECSA- Tec de Monterrey. 2003