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EE539: Analog Integrated Circuit Design; Common mode feedback

circuits
Nagendra Krishnapura (nagendra@iitm.ac.in)

18 April 2006

Vdd

M3 M4
vop + von
CL CL 2
vop common
von mode
detector

M1 M2 Vcm,out

error amplifier

I0

M0

Figure 1: Principle of common mode feedback

• Adjust top current sources (M3,4 ) via feedback to control the bottom current source (M0 ).

• Detected common mode voltage equals Vcm,out in steady state-assuming a large loop gain.

1
2

Vdd Vdd
error amplifier
M3 M4 replaced by a wire M3 M4

CL CL Rcm
CL CL

Rcm Rcm
Rcm
M1 M2 M1 M2

I0 I0

M0 M0

(a) (b)

Figure 2: (a) CMFB circuit using common mode diode connection, (b) redrawn

• Common mode diode connection: output voltage adjusts itself to ensure that I 3 + I4 = I0 .
p
• Resulting common mode equals vcm,out = Vdd − VT − I0 /K3 . Cannot be set independently of
device parameters

• Largest positive output swing = VT , implying a largest differential peak-peak swing of 4VT , indepen-
dent of the supply voltage.

• Common mode detector using resistors: loads the differential amplifier and reduces the gain.
3

Vdd Vdd

M3,4 M3,4
W3,4 = 2W3 W3,4 = 2W3
magnitude
2CL
Vf Vt
gm3 /gds3
cascode connection gm1 /(gds1 + gds3 + Gcm )
Rcm /2 large R Rcm /2
out
2CL differential gain
Vcm,in Vcm,in (no mirror pole)
M1,2 common mode
W1,2 = 2W1 M1,2 loop gain ωu,d = gm1 /CL
W1,2 = 2W1 ω
gds3 /CL ωu,cm = gm3 /CL
(gds1 + gds3 + Gcm )/CL
I0 I0

M0 M0 Gcm /Cgs3

Vf gm3 1
=
Vt gds3 (1 + sCgs3 Rcm )(1 + sCL /gds3 )
(a) (b) (c)

Figure 3: (a) Common mode equivalent ckt., (b) CMFB loop gain calculation, (c) Typical differential gain
and CM loop gain magnitudes

• CMFB loop gain: Dominant pole at the output

• Second pole significant if a large Rcm is used

• Feedback around a single transistor (M3,4 ). Typically stable.

• No mirror pole in the fully differential amplifier’s response


4

Vdd Vdd

M3 M4 M13 M14

CL CL

Rcm Rcm

M1 M2 Vcm,out M11 M12

Vcm ± vi /2

I0 I10

M0 M10

Differential pair Error amplifier

I10 = I0 /α
W10 = W0 /α
W11 = W1 /α
W13 = W3 /α
α > 1 minimize power consumption

Figure 4: CMFB circuit with explicit error amplifier

• A second differential amplifier used as an error amplifier. Its output current is mirrored to the opamp’s
load devices (M3 , M4 )

• To have no systematic error in the output CM voltage, aspect ratios of M 3,4,13,14 are in ratios of
respective currents. i.e. without mismatches, the error amplifier operates with zero input voltage

• Error amplifier current can be scaled down to minimize power consumption.


5

Vdd Vdd

M3,4 M13 M14

2CL

Rcm /2

M1,2 Vcm,out M11 M12

Vcm

I0 I10

M0 M10

Differential pair Error amplifier

Figure 5: CM equivalent

Vdd Vdd
W3,4 = 2W3
M3,4 M13 M14
gm1 Vx

2CL
Vf
gm1 /2αVx gm1 /2αVx
Rcm /2
Cx

M1,2 Vcm,out M11 M12


W1,2 = 2W1
Vcm
Vx

I0 I10

M0 M10

Differential pair Error amplifier


Cx : capacitive loading from the error amplifier
Vf gm1 1 1 1
=
Vt 2gds3 1 + sgds3 /CL 1 + sCx Rcm 1 + sgm3 /αCp3
(Assumed that Rcm Cx << CL /gds3 ; Cp3 is the parasitic capacitance at the drain of M13

Figure 6: CMFB loop gain calculation

• Differential response: Single pole at the output.

• CMFB loop gain: Three poles; Approx. two poles with a small R cm ; Dominant pole at the output.
CL compensates both the common mode and differential loops.

• Using a large α (small current in the error amplifier) results in a lower frequency non dominant pole
in CMFB loop gain.
6

Vdd Vdd

M3 M4 M13 M14

CL CL

M1 M2 Vcm,out M11 M12 M12

Vcm ± vi /2

I0 I10

M0 M10

Differential pair Common mode detector + Error amplifier

I10 = I0 /α
W10 = W0 /α
W11 = W1 /α
W12 = W11 /2
W13 = W3 /α
α > 1 minimize power consumption

Figure 7: CMFB circuit using differential pair CM detector

• Split the transistor in the error amplifier differential pair into two halves and apply vop , von to their
gates. Current summation ensures common mode detection.

• Active CM detector does not load the opamp.

• Resistive CM detector: highly linear

• Active CM detector: Linearity, and consequently, the swing of the output signals, depends on the
linearity of the error amplifier differential pair
7

Vdd Vdd

M3,4 Vt Vf M13 M14

Cascode 2CL
large Rout

M1,2 Vcm,out M11 M12

I0 I10

M0 M10

Figure 8: CMFB loop gain calculation using the common mode equivalent circuit

• Two pole response

Vf gm3 gm11 1 1
=
Vt gds3 2gm14 1 + sCL /gds3 1 + sCx /gm14

• Non dominant pole gm14 /Cx moves to lower frequencies if a very small current is used in the error
amplifier.
8

Vdd

Common mode detector and feedback


M11 M12 Vdd

Rs

M3 M4 Vbias,p
Vbias,p
ID
CL CL

M1 M2 Vdd

Vcm ± vi /2 vop von

Gs
I0 Vbias,p
M0 ID

Differential pair
 
vop + von
Gs = 2Kp − VT
2
(a)
(b)
Vdd Vdd

Common mode detector and feedback


M11 M12 M24 Vcm,out
W12 /L12 (W12 /α)/L12

M3 M4 Vbias,p
M23

CL W3 /L3 W3 /L
C3 L
(W3 /α)/L3

M1 M2

Vcm ± vi /2

I0 /2α
I0

M0

Differential pair replica biasing

(c)

Figure 9: (a) Common mode feedback using transistors in triode region, (b) Degenerated resistor, Degener-
ation using MOS transistors whose resistance depends on the common mode voltage, (c) Replica biasing to
set the output common mode voltage

• Parallel transistors in triode region with vop , von as inputs realize a conductance as a function of the
common mode

• Replica biasing with the gate of M24 at the desired common mode level

• Upper limit of vop , von is Vdd − VT . M13,14 go into saturation region at a voltage slightly below this.
9

CL CL CL CL C2 C1 C1 C2

Ycm = 2sCL Ycm = 0 Ycm = 2sC2


Ydif f = sCL /2 Ydif f = sCL /2 Ydif f = s(C1 + C2 )/2

Figure 10: Differential and common mode loading

• Floating capacitors don’t contribute to common mode loading

• There should be sufficient common mode loading to compensate the CMFB loop
10

Vdd

M3 M4 Vbias,p M13 M14

M6
Cx
M5

Cc Cc Vcm,out
M1 M2 M11 M12
CL Rcm Rcm CL
Vcm ± vi /2

I0 I0 /α

M0 M8 I1 M7 I1 M10

Differential pair
Fully differential two stage opamp Error amplifier

Figure 11: Two stage opamp with common mode feedback

• Output common mode voltage is measured and common mode feedback applied to the first stage load.

• Can use separate common mode feedback for each stage


11

Vdd

M1,4 M13 M14

M5,6
Cx

2Cc Vcm,out
M1,2 Vcm,in M11 M12
2CL Rcm /2

Vf Vt

I0 M7,8 I0 /α

M0 2I1 M10

Figure 12: Common mode equivalent circuit of the two stage opamp

• Common mode feedback: Negative feedback around two stages

• Compensation through Cc

• Differential response

gm1 gm5 1 − sCc /gm5


Ad (s) =
gds1 + gds3 gds5 + gds6 + Gcm (1 + s/p1 )(1 + s/p2 )
gds3
p1 ≈
C3 + Cc (1 + gm5 /gds5 )
gm5 CcC+C
c
3
p2 ≈ Cc CL
CL + Cc +CL

C3 is the parasitic capacitance at the drain of M3 .

• Common mode loop gain

gm3 gm5 gm11 1 − sCc /gm5


Acmloop (s) =
gds3 gds5 + gds6 2gm13 (1 + s/p1 )(1 + s/p2 )(1 + s/p3 )
gds3
p1 ≈
C3 + Cc (1 + gm5 /gds5 )
gm5 CcC+C
c
3
p2 ≈ Cc C3
CL + Cc +C3
gm13
p3 =
Cx
12

Vdd

M3 M4 M13 M14

M6
Cx
M5

M12 M12
Cc Cc Vcm,out
M1 M2 M11 vop von
vop von
CL CL

I0 I0 /α

M0 M8 I1 M7 I1 M10

Fully differential two stage opamp Common mode detector + error amplifier

Figure 13: Two stage fully differential opamp with split transistor common mode detector
13

Rcm
Rcm
Vi Vo Vi Vo

Cload Cload
Ccm

Vo 1 Vo 1 + sRcm Ccm
= =
Vi 1 + sRcm Cload Vi 1 + sRcm (Ccm + Cload )

Figure 14: (a) Resistive common mode detector, (b) Introducing a zero to reduce phase lag

• To minimize loading, increase Rcm .

• Rcm with parasitic capacitance at the input of the error amplifier adds phase lag and degrades stability.

• Use a capacitor across Rcm to introduce phase lead and ensure stability of the common mode feedback
loop.
14

Vcm ± vi /2 Vcm,out ± vo /2

(a)

Vdd Vdd

M3 M4 M3,4
W3,4 = 2W3
Rout ≈ 1/gds0
CL CL much smaller than without differential feedback
V Vt
f

R Rcm Rcm R Rcm /2


R R 2CL
Vcm,in R/2
M1 M2
R/2 M1,2
W1,2 = 2W1

I0 I0

M0 M0

Vf gm3 1
=
Vt (gds3 + gds0 ) (1 + sCgs3 Rcm )(1 + sCL /(gds3 + gds0 ))
(b) (c)

Figure 15: (a) Opamp with differential feedback, (b) Transistor level circuit, (c) Common mode equivalent
circuit

• Differential feedback can change CMFB loop gain.

• CM loop gain needs to be evaluated with differential feedback in place.