EE141

EE141-Fall 2003
Digital Integrated
Circuits

Lecture 6
CMOS Inverter
Voltage Transfer Characteristic
Propagation Delay

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Administrative Stuff
‰ This lecture is pretaped
ƒ Played back in a regular slot
‰ Homework #2 posted last week, due 9/16
‰ Homework #3 posted today, due 9/23

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Last Lecture
‰ Last lecture
ƒ MOS transistor operation and modeling
‰ Today’s lecture
ƒ CMOS inverter
ƒ Voltage transfer characteristic
ƒ Propagation delay

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CMOS Inverter
Voltage Transfer
Characteristic

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The CMOS Inverter

V DD

V in V out

CL

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NMOS Transistor
-4
x 10
2.5

VGS= 2.5 V

VGS= 2.0 V
1.5
ID (A)

VGS= 1.5 V
1

0.5 VGS= 1.0 V

0
0 0.5 1 1.5 2 2.5
VDS (V)

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PMOS Load Lines

IDn
V in = VDD +VGSp
IDn = - IDp
V out = VDD +VDSp

V out

IDp IDn IDn

Vin=0 Vin=0

Vin=1.5 Vin=1.5

V DSp VDSp Vout

VGSp=-1

VGSp=-2.5
Vin = VDD+VGSp Vout = V DD+VDSp
IDn = - IDp

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CMOS Inverter Load Characteristics

I Dn
Vin = 0 Vin = 2.5

PMOS Vin = 0.5 Vin = 2 NMOS

Vin = 1 Vin = 1.5

Vin = 1.5 Vin = 1
Vin = 1.5 Vin = 1
Vin = 2 Vin = 0.5

Vin = 2.5 Vin = 0

Vout
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CMOS Inverter VTC

Vout
NMOS off
PMOS res

2.5
NMOS s at
2 PMOS res

NMOS sat
1.5

PMOS sat
1

NMOS res
PMOS sat NMOS res
0.5

PMOS off

0.5 1 1.5 2 2.5 V in

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Switching Threshold
‰ If both transistors are velocity saturated

‰ VM can be adjusted by changing the “β ratio” Wp/Wn

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Switching Threshold as a Function

of Transistor Ratio
1.8

1.7

1.6

1.5

1.4
V (V)

1.3
M

1.2

1.1

0.9

0.8
0 1
10 10
W /W
p n
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Determining VIH and VIL

Vout

V OH

VM

V in
V OL
V IL V IH

A simplified approach
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Inverter Gain
0

-2

-4

-6

-8
gain

-10

-12

-14

-16

-18
0 0.5 1 1.5 2 2.5
V (V)
in

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Gain as a function of VDD

2.5 0.2

2
0.15

1.5
V out (V)
V out (V)

0.1

0.05
0.5

Gain=-1
0
0 0 0.05 0.1 0.15 0.2
0 0.5 1 1.5 2 2.5
V (V)
V (V) in
in

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Simulated VTC
2.5

1.5
(V)
out
V

0.5

0
0 0.5 1 1.5 2 2.5
V (V)
in

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Impact of Process Variations

2.5

2
Fast PMOS
Slow NMOS
1.5
Vout(V)

Nominal

1
Fast NMOS
Slow PMOS

0.5

0
0 0.5 1 1.5 2 2.5
Vin (V)
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CMOS
Switching

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MOS Transistor as a Switch

Discharging a capacitor

• Can solve: iD = iD (vDS )

dV
iD = C DS
dt
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The Transistor as a Switch

VGS ≥ VT
Ron ID
V GS = VD D
S D
Rmid

R0

V DS
VDD/2 VDD

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MOS Transistor as a Switch

Solving the integral:

Averaging resistances:

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The Transistor as a Switch

5
x 10
7

(Ohm) 5

4
eq

3
R

0
0.5 1 1.5 2 2.5
V (V)
DD

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The Transistor as a Switch

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MOS Capacitances
Dynamic Behavior

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Dynamic Behavior of MOS Transistor

G

CGS CGD

S D

CSB CGB CDB

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The Gate Capacitance

Polysilicon gate

Source Drain
W
Top (layout) view n+ xd xd n+

Gate-bulk
Ld
overlap

Gate oxide
tox
Cross section n+ n+
L

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Gate Capacitance
G G G

CGC CGC CGC

S D S D S D

Cut-off Resistive Saturation

Most important regions in digital design: saturation and cut-off

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Gate Capacitance

CG C
WLC ox WLC ox CG C
2WLC ox
CG CS 3
WLC ox C G CS = CG CD WLC ox
CGC B
2 2 CGCD

VG S 0 VDS /( VG S-VT) 1

Capacitance as a function of VGS Capacitance as a function of the

(with VDS = 0) degree of saturation

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Diffusion Capacitance
Channel-stop implant
NA +

Side wall
Source
W
ND

Bottom

xj Side wall
Channel
LS Substrate NA

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Junction Capacitance

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Linearizing the Junction Capacitance

Replace non-linear capacitance by
large-signal equivalent linear capacitance
which displaces equal charge over voltage swing of interest

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Capacitances in 0.25 µm CMOS

process

In most CMOS processes (in any technology)

Cg ~ Cd ~ 1.5 – 2fF/µm (width)

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.MODEL Parameters MOS1

‰ .MODEL Modname NMOS/PMOS <VTO=VTO...>

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Computing the Capacitances

VDD VDD

M2
Cdb2 Cg4 M4
Cgd12
Vin Vout Vout2

Cdb1 Cw Cg3
M1 M3
Interconnect

Fanout
Vin Vout
Simplified
Model CL

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The Miller Effect

Cgd1 Vout
Vout ∆V
∆V

Vin ∆V
2Cgd1

M1
M1 ∆V
Vin

“A capacitor experiencing identical but opposite voltage swings

at both its terminals can be replaced by a capacitor to ground,
whose value is two times the original value.”

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Computing the Capacitances

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Two Inverters

VDD

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Next Lecture
‰ CMOS Inverter
ƒ Propagation delay
ƒ Second-order effects in MOS transistors

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