Shallow Junctions Slides

Shallow Junctions
&
Contacts
Prof. Krishna Saraswat
Department of Electrical Engineering

Stanford University
Stanford, CA 94305
saraswat@stanford.edu
Stanford University 1 Saraswat / EE311 / Shallow Junctions
Outline
•Junction/contact scaling issues

•Shallow junction technology
•Ohmic contacts
•Technology to form contacts
Page ‹#›
MOS Device Scaling
L Constant E Field Scaling
xox Xj
L All device parameters are scaled by
the same factor.
xox Xj
N+ Na N+ N+ Na N+
lo P
lo
• gate oxide thickness xox ↓
P • channel length L ↓
• source/drain junction depth Xj ↓
• Channel doping ↑
Why do we scale MOS transistors? • Supply voltage VDD ↓
1. Increase device packing density
2. Improve frequency response α 1/L
3. Improve current drive (transconductance gm)
" ID
gm =
"VG VD = const
W Kox
# µn VD for VD < VD SAT , linear region
L to x
W Kox
# µ (VG $ VT ) for VD > VDSAT , saturation region
L n to x
Why do we need to scale junction depth?
Short Channel Effects on Threshold voltage

Ddepletion width in a long channel device
2" (2# F + VBG )
W= Gate
qN A
We can approximate, the bulk charge as L
N+ source Depletion N+ drain
#L + L ' & region
Q B " L = q " N A " W " %% (( L! rj
! $ 2 ' P-Si
By trigonometry, we can write: QB depleted QB depleted
by source by drain
$ ' r
L + L' 2#W j
= 1" && 1 + "1)) #
2L % rj ( L
We can then approximate the threshold voltage as:
Q * $ 2 " W ' rj -
VT = VFB ! 2 " # F ! B " ,1 ! & 1+ ! 1) " /
Cox + % rj ( L.
Threshold voltage is a function of junction depth,
depletion width and channel length?
L. Yau, Solid-State Electronics, vol. 17, pp. 1059, 1974
Page ‹#›
Need for Shallow Source/Drain Junctions
Q * $ 2 " W ' rj -
VT = VFB ! 2 " # F ! B " ,1 ! & 1+ ! 1) " /
Cox rj ( L.
+ %
• Roll-off in threshold voltage as the channel length is reduced and
drain voltage is increased
• To minimimize VT roll-off
•Reduce as junction depth(rj)
•Increase in Cox should increase gate control
Sheet resistance increases as junction depth is reduced
Source/drain Junction Depth
Year 1997 1999 2003 2006 2009 2012

Min Feature Size 0.25! 0.18! 0.13! 0.10! 0.07! 0.05!
Contact xj (nm) 100-200 70-140 50-100 40-80 15-30 10-20
xj at Channel (nm) 50-100 36-72 26-52 20-40 15-30 10-20
From the ITRS roadmap
• Source/drain doping requirements show continuing drive to obtain

shallow junctions.
• How will we form such shallow junctions?
• How will we make low resistance contacts to them?
• How will we minimize the sheet resistance of the junctions?
Page ‹#›
S/D Junction Scaling Trend
Gate Length or SDE Depth [nm]

70 60
2001 ITRS
60 Physical Gate Length 50
Rsd/Rch-ideal [%]
50
Max. Ratio of R sd to Ideal R ch40
40
30
30
20
Lch t ox 20
Rch " ⇒ Scaled with Lg
(V gs ! Vth ) 10 10
(Lch ↓, tox↓) SDE Junction Depth
0 0
2000 2004 2008 2012 2016
1 Year
Rsd ! Rsh ! ⇒ Difficult to scale
N sd X j (Nsd const, Xj↓) Ref: J. Woo (UCLA)
⇒ Rsd/Rch ↑
• As Lg scales down, Rsd becomes comparable to Rch

• Rsd becomes important factor for device current
• Parasitic portion of the device is now playing important role in
device performance and CMOS scaling
Impact of Parasitic Series Resistance

Series Resistance (ohms)
y=0 140
120 NMOS
Scaled by ITRS Roadmap
100
Rov
Sidewall Gate
80
60
Rext
Silicide
Nov(y) x 40 Rdp
Rcsd Rov 20 Rcsd
Rdp Rext
0
30 nm 50 nm 70 nm 100 nm
Physical Gate Length
Next(x)
70
Relative Contribution [%]
60 Rcsd
Problem in junction scaling: NMOS
• Sheet resistance of a junction is a strong 50
function of doping density 40
• Maximum doping density is limited by solid Rext
solubility and it does not scale ! 30
• Silicidation can minimize the impact of 20 Rov
junction sheet resistance 10
• Contact resistance R csd is one of the dominant Rdp
components for future technology 0
32 nm 53 nm 70 nm 100 nm
Source: Jason Woo, UCLA Physical Gate Length
Page ‹#›
Relative Contributions of Resistance
Components: PMOSFETs
70
Relative Contribution [%]

Series Resistance (ohms)
200 PMOS
60
Rcsd PMOS
Scaled by ITRS Roadmap
150 Rov 50
40
100 Rov
Rext 30
50 Rdp 20 Rext
Rcsd Rdp
10
0
30 nm 50 nm 70 nm 100 nm 0
Physical Gate Length 32 nm 53 nm 70 nm 100 nm
Physical Gate Length
• Problem even more serious for PMOS

• Rcsd will be a dominant component for highly scaled nanometer
transistor ( Rcsd/Rseries ↑ >> ~ 60 % for LG < 53 nm)
Source: Jason Woo, UCLA
Outline

•Ohmic contacts
Page ‹#›
Dopant Diffusion
Ion Implant
Gate Stack
Anneal/Diffusion
• Solutions to diffusion equations (Fick's laws) gives bulk diffusivity

_ EO
Di = D io " e k"T
• In shallow junction technologies, numerous effects alter these values

resulting in enhanced diffusion.
• Transient enhanced diffusion
_t
#
D = Di + D o " e
• Diffusion affected by defects, e.g.,oxidation induced point defects
Diffusion Affected by Oxidation Induced

! Point Defects
TSUPREM IV simulations of oxidation enhanced diffusion of boron (OED)
and oxidation retarded diffusion of antimony (ORD) during the growth of a
thermal oxide on the surface of silicon.
!
antimony
boron
Oxidation increases interstitials (CI) and decreases vacancies (CV) from their
equilibrium values. This in turn changes diffusivity.
(Ref: Plummer, et al., Silicon VLSI Technology - Fundamentals, Practice and Models)
Page ‹#›
Diffusion in Polycrystalline Materials
DGB grain boundary diffusion

DL lattice diffusion
Generally DGB >> DL
The worst-case demonstration of the defect enhanced diffusion of dopants is

in polycrystalline silicon, which can be several times faster than diffusion in
bulk Si because of defects at the grain boundaries.
Transient Enhanced Diffusion (TED)
40 keV, 10-14 cm-2 B

750ºC anneal
τ
At lower temperatures, the damage can stay around longer and enhance the dopant
diffusion, while at higher temperatures the damage annihilates faster. Thus the
diffusivity is a function of time during the transient.
% t( # E &
D = Di + Do " exp'# * Where Di = Dio exp%" 0 ( is intrinsic diffusity
& $) $ kT '
Ref: Plummer, et.al.,

! !
Page ‹#›
Effect of TED on Junction Depth
• At lower temperature longer times are needed to anneal the damage

• Transient enhanced dopant diffusion effects are stronger
• Junction depth is larger
• Higher temperature and shorter times are needed to minimize TED
Shallow Junction Formation Technologies

Low Energy Implantation
40 keV As and B implants 12 keV B implants
Concentration (cm-3)
Concentration (cm-3)
Boron
Boron
Arsenic BF2
Depth Depth
As Concentration (cm-3)
1022
as-implanted
20
) 10 5 keV
-3
1 keV
m Ref. Kasnavi, PhD Thesis
c
( 1018 Stanford Univ. 2001
s
A
1016
0 20 40 60 80
Depth (nm)
Page ‹#›
Ion Implantation Damage
Heavy ions (As, P) Light ions (B)

Higher energy Lower energy
• Heavy ions (As, P) cause excessive damage turning implanted

region into amorphous
• Light ions (B) have buried damage
Ion Implantation Damage Anneal

Light ions (B) Heavy ions (As, P)
Lower energy Higher energy
Amorphous
After implant regrowth
Crystalline
SPE
After anneal
fully annealed
Buried damage
• Fully amorphized region can be fully annealed through solid phase regrowth
• Buried damage leaves defects where damage was created as regrowth takes
place both from top and bottom.
Page ‹#›
Pre-amorphization implants
Log concentration (cm-3)

Implanted
10 sec 1000°C RTA

Ge preamorphized
Si preamorphized
Not preamorphized
Depth (nm)
Pre-amorphization implants can reduce the damage and yet get shallow junctions
Solid Source Diffusion

B Concentration (cm-3)
Depth (nm) Depth (nm)
In COSi2 In Si after silicide removal
Boron profiles after diffusion at 950°C of 50 nm COSi2 implanted

with 5 X 1015 cm-2 BF2 (a) and (b)in Si after silicide removal.
Page ‹#›
Gas Immersion Laser Doping (GILD)
Si wafer showing the adsorption of the dopant species onto the clean
silicon surface. The dopant is incorporated into a very shallow region
upon exposure to the excimer laser pulse.
Junction Depth Vs. Sheet Resistance Tradeoff

60
5 keV limit
Roadmap
50
Junction Depth (nm)
Y=2000, L g=180nm
40
1 keV
) limit 2002, 130nm
m 30
n
( 2005, 100nm
j
X
20 2008, 70nm
2011, 50nm
10 1020C
2014, 35nm
spike
0
0 250 500 750 1000
Rs ( ! / )
Ref. Kasnavi, PhD Thesis Stanford Univ. 2001
It will be difficult to meet the ITRS scaling

requirments of junction depth and sheet resistance
Page ‹#›
Solutions to Shallow Junction
Resistance Problem
Extension implants Elevated source/ drain
Silicidation Schottky Source/Drain

Effect of Scaling of Contacts and Junctions
R (total) = Rch + Rparasitic

Rparasitic = Rextension + Rextrinsic
Rextension = Rd’ + Rs’
Rextrinsic = Rd + Rs + 2Rc
Ref: Ohguro, et al., ULSI Science and Technology 1997, Electrochemical Soc. Proc., Vol. 97-3
Silicidation of junctions is necessary to minimize the

impact of junction parasitic resistance
Page ‹#›
Elevated S/D Technology
From A. Hokazono et al (Toshiba), IEDM2000

' &L # !c & q( #
Rcsd = c coth $ con ! LT = ) c ' exp$ b !
LT % LT " R sh ,dp $ N if !
% "
• Elevated S/D structure ⇒ Reduction of Rcsd by increasing Nif &
reducing Rsh,dp underneath silicide
New Structures and Materials for Nanoscale MOSFETs

(From Handout #1)
5 Top Gate
G
3 4
S C D Si Source Drain
2
SiO2
1 Bottom Gate
High µ High-K
Si channel
BULK SOI Double gate
1. Electrostatics - Double Gate
- Retain gate control over channel
- Minimize OFF-state drain-source
leakage
2. Transport - High Mobility Channel
- High mobility/injection velocity
- High drive current for low intrinsic
delay
3. Parasitics - Schottky S/D
- Reduced extrinsic resistance
4. Gate leakage - High-K dielectrics
- Reduced power consumption
5. Gate depletion - Metal gate
Page ‹#›
Effect of Extrinsic Resistance on Double Gate MOSFETs
Id = K⋅
K⋅(Vg–Vth–IdRs)α
1.E+21
GATE
1.E+20
1.E+19
Net Doping (cm-3)
1.E+18
1.E+17
Doping
1.E+16 gradient
5nm/dec
1.E+15 4nm/dec
3nm/dec
2nm/dec
1.E+14
1nm/dec
0.5nm/dec
1.E+13
40 45 50 55 60 65
x (nm)
• Extrinsic resistance reduces gate overdrive ⇒ performance limiter in ballistic FETs

• Ideally need very low specific contact resistivity and hyperabrupt lateral junctions
• For a given doping abruptness:
–Too much underlap ⇒ dopants spill into channel ⇒ worse SCE
–Too little underlap ⇒ large series resistance in extension tip
•Extrinsic (S/D) resistance may limit performance in future ultrathin body DGFETs
Shenoy and Saraswat, IEEE Trans. Nanotechnology, Dec. 2003
Two kinds of transistors

Junction S/D MOSFET Schottky S/D MOSFET
Possible advantages
• Better utilization of the metal/semiconductor interface
Possible option to overcome the higher parasitic resistance
• Modulation of the source barrier by the gate
High Vg ⇒ barrier thin ⇒ tunneling current ⇑ ⇒ ION ⇑
Low Vg ⇒ barrier thick ⇒ tunneling current ⇓ ⇒ IOFF ⇓
• Better immunity from short channel effects
Possible Disadvantage
• Tradeoff between short channel effect vs. ION reduction due to the Schottky barrier
Page ‹#›
Schottky Barrier Source/Drain SOI MOSFET
Lg~20 nm FETs with Complementary
Gate
Silicides PtSi PMOS, ErSi NMOS
Silicide Si Source
ErSi2
BOX
Tilted
Lg + Spacers =27nm
Gate
N+poly, ErSi2
W=25nm
PtSi PMOS ErSi NMOS

Lg 20 nm 15 nm
Tox 4 nm 4 nm
Vg-Vt 1.2 V 1.2 V
Ion 270 uA/um 190 uA/um
1E-3
|V sd| from 0.2V to 1.4V
Swing 100 mV/dec 150 mV/dec
1E-4 in steps of 0.4V
Ion/Ioff 5E5 1E4
Vt -0.7 V -0.1 V 1E-5
|I d| (A/ µm)
1E-6
• Metal S/D reduce extrinsic resistance
1E-7
• But Schottky barrier reduces Ion PMOS NMOS
1E-8
• Need low barrier technology to ensure high Ion T ox = 4nm T ox = 4nm
1E-9 L g = 20nm L g = 15nm
1E-10
-1.5 -1.0 -0.5 0.0 0.5 1.0 1.5
J. Boker et al.- UC Berkeley Vg (V)
Doped vs. Schottky S/D DG Device Comparison Simulations
ION vs. IOFF

CV/I Delay
Source: King/Bokor,U.C. Berkeley Ref: R. Shenoy, PhD Thesis, Stanford 2004
 Low barrier height metal contact required to achieve high ION and low CV/I delay
 Extensive research needed to develop a low barrier technology
Page ‹#›
Outline

•Ohmic contacts
Need to understand the physics of contacts
resistance and develop technology to minmize it
Conduction Mechanisms for

Metal/Semiconductor Contacts
I
Low doping
φB
Ef
V
Schottky
(a) Thermionic emission
Medium doping
(b) Thermionic-field emission
Heavy doping
Ohmic
(c) Field emission.!
Contact resistance strongly depends on barrier height (φB) and doping density
Page ‹#›
Specific Contact Resistivity (ρc)
V = Vbulk + 2Vcontact = I (Rbulk + 2Rcontact)
n+ dVbulk !l
Rbulk = =
dI A
!V
For a uniform current density
!V
dVcontact !c
Rcontact = =
dI A
• Specific contact resistivity and not contact resistance is the fundamental

parameter characterizing a contact
Tunneling - Ohmic Contacts

Fm Jsm Xd =
2 K !o "i
Fs q Nd
When Xd ≤ 2.5 – 5 nm, electrons can “tunnel” through

the barrier. Required doping is:
2 K #o $i
N d min " " 6.2 %10 1 9 cm &3 for X d = 2.5 nm
q X d2
A*T
J sm = F P( E)(1" Fm )dE
Net semiconductor to metal current is k ! s
# 2! " sm * &
B
P(E) is the tunneling probability given by P(E) ~ exp% - (
$ h N '
Current can be shown to be [ *

J s m " exp #2xd 2m (q$ B # qV ) /h
2
]
% *(
2# $ m
Specific contact resistivity is of the form "c = " co exp'' B s ** ohm + cm 2
& h N )
ρc primarily depends upon
• the metal-semiconductor work function, φΒ,
• doping density, N, in the semiconductor and
• the effective mass of the carrier, m*.
Page ‹#›
!
Specific Contact Resistivity to P-type Si
P-type Si
Specific contact resistivity
Specific contact resistivity (Ωcm2)

$ 2" #sm* '
!c = ! co exp && B ) ohm * cm 2
% qh N )(
Specific contact resistivity, ρc ↓

• As doping density N↑
• Barrier height φB ↓
(S. Swirhun, PhD Thesis, Stanford Univ. 1987)

NA (cm-3)
Specific Contact Resistivity to N-type Dopants

Specific contact resistivity (Ωcm2)
• Similar trends for N-type Si
• For a given doping density contact resistance

is higher for n-type Si than p-type.
• This can be attributed to the barrier height

• φBn > φBp
(S. Swirhun, PhD Thesis, Stanford Univ. 1987)
ND (cm-3)
Page ‹#›
Solid Solubility of Dopants in Silicon
• Problem is worse for p-type dopants (B), solid solubility is lower

• Maximum concentration of dopants is limited by solid solubility
PROBLEM: Solid solubility of dopants does not scale !
Barrier Height of Metals and Silicides to Si

Ideal Schottky model
Barrier height to n- and p-type Si
(φ BN hollow symbols and φ BP solid symbols)
Φm < χ Φm > χ
Practical barrier with

Fermi level pinning . (Ref: S. Swirhun, PhD Thesis, Stanford Univ. 1987)
φBN ⇒ 2Eg/3
φBN + φBP = Eg φBP ⇒ Eg/3
Page ‹#›
Strategy for Series Resistance Scaling
S/D Series Resistance [Ωµm]

300
LG = 53 nm Graded Junction
Midgap Silicide
240
Rov
Box Profile
180
Rext
Midgap Silicide Rdp
Box Profile
120 Low-Barrier
Silicide Rcsd
(ΦB = 0.2 eV)
60
0
Source/Drain Engineering
Source: Jason Woo, UCLA
Potential Solutions for S/D Engineering

y=0
• Rdp & Rcsd Scaling (ρc ↓) Sidewall Gate

⇒ Maximize Nif ( Rsh,dp ↓):
- Laser annealing Silicide
- Elevated S/D Nov(y) x
⇒ Minimize ΦB: Rcsd Rov
Rdp Rext
- Dual low-barrier silicide
(ErSi (PtSi2) for N(P)MOS)
• Rov & Rext Scaling Next(x)
⇒ Dopant Profile Control:

ultra-shallow highly-doped box-shaped SDE profile
(e.g., laser annealing, PAI + Laser Annealing)
Page ‹#›
Bandgap Engineering
From M. C. Ozturk et al. (NCSU), IEDM2002

• Si1-xGex S/D & germanosilicide contact
− Assuming metal Fermi level is pinned near midgap
− Similar barrier heights on n- or p-type material
− Smaller bandgap for Si1-xGex
− Reduction of Rcsd with single contact metal
Energy band diagram and charging character of

interface states for the metal-dielectric interface
 Ideal Schottky model: when a metal and
a semiconductor or a dielectric form an
interface, there is no charge transfer
across the interface
 A semiconductor or dielectric surface has
gap states due to the broken surface
bonds. These are spread across the
energy gap.
 The wave functions of electrons in the
metal tail or decay into the
semiconductor in the energy range
where the conduction band of the metal
overlaps the semiconductor band gap.
These resulting states in the forbidden
gap are known as metal-induced gap
states (MIGS) or simply intrinsic states. Yeo, King, and Hu, J. Appl. Phys., 15 Dec. 2002
 The energy level in the band gap at
which the dominant character of the
interface states changes from donorlike
to acceptorlike is called the charge
neutrality level ECNL
Page ‹#›
Fermi Level Pinning
Energy band structure of the Schottky contact and the electron energy
dependence of the charging character of the metal semiconductor interface states.
 The metal work function is pinned near the charge neutrality level.
 The charge neutrality level is defined as the energy level at which the
character of the interface states changes from donor-like to acceptor-like.
 The charge neutrality level is situated at around one-third of the band gap in
the case of silicon ⇒ φbn = 2Eg/3 and φbp = Eg/3
Fermi-level de-pinning
 Can we alter the charge neutrality level? It may be possible to do so by
passivating the interface states. This can be done by modifying the interface.
An issue of current research.
 An example is selenium passivation of Si/Mg interface
the reconstructed Si Se-passivated Si

[001] surface [001] surface
I –V characteristics of Mg
contacts to Si
Band diagram of Mg–Si contacts (a) without
interface states and (b) with interface states. M. Tao et al., APL, 2003
Page ‹#›
Contact Resistance: 3D Model
Contact Majority carrier continuity equation outside
the contact is
#J x #J y #J z
I I !" J = + + =0
#x #y #z
Current density in the semiconductor is
Metal Silicon J = !"E = "#v
I Silicide
Combining these two equations we obtain
Current I ! " #!V = 0
Total current over the contact area is
I tot = " $ J # dA
• Current flow in a contact is highly Solution of the above equations gives
non-uniform information about contact resistance.
• Contact resistance does not scale !
However, calculations are very involved.
with area
Transmission Line Contact Model

A simplified 1D solution of the contacts is
# x &
I(x) = I1 exp % ! ( = I1 exp( ! x lt )
$ " R
c s'
lt = !c Rs
lt is the characteristic length of the

transmission line - the distance at which 63%
of the current has transferred into the metal.
Page ‹#›
Measurement of Contact Resistance
and Specific Contact Resistivity (ρc)
Rs" c
R f = V f /I = coth( d /lt )
w
For a very large value of lt or for d << lt

"c
! Rf !
wd
Rs" c
Re = Ve /I =
w sinh( d /lt )
• Rf gives reasonable assessment of the source/drain contact resistance

including the resistance of the semiconductor under the contact
! ρc, can be calculated by measuring I, Vf or Ve
• Specific contact resistivity,
• Measurement of Rf or Re is not straightforward and needs specialized test
structures
Test Structure to Measure Contact Resistance:

Transmission Line Tap Resistor
V24 = V f + IRSi + V f
R f
V
Rt = 24 = 2R f + Rs ls w
I
Rs ! c
R f = V f / I1 = coth (d / lt ) is a very small number
w
Page ‹#›
Test Structure to Measure Contact Resistance:
Cross-bridge Kelvin Structure
1 2 Metal
. l
l
l
l N+ Diffusion
V V !
Rk = k = 14 = 2c
. Vk
I I23 l
3 4
Metal .
N+ Diffusion I
Contact
Cross-bridge Kelvin structure used to measure an average

contact resistance, called RK in the figure
Error in Specific Contact Resistivity due to 1-D Modeling

1-D model 2-D model
Specific contact resistivity (ρc) Contact resistance
• Specific contact resistivity (ρc) is a fundamental property of the

interface and should be independent of contact area
• 1-D models overestimate the contact resistance (Rc)
• 2-D models give more accurate results and should be used
Page ‹#›
Outline

•Ohmic contacts
Aluminum Contacts to Si
Aluminum
Oxide
Oxide
N+
Silicon
• Silicon has high solubility in Al ~ 0.5% at 450ºC

• Silicon has high diffusivity in Al
• Si diffuses into Al. Voids form in Si which fill
with Al: “Spiking” occurs.
Page ‹#›
Al/Si Alloy Contacts to Si
Al-Si phase diagram
By adding 1-2% Si in Al to satisfy solubility

requirement junction spiking is minimmized
But Si precipitation can occur when cool

down to room temperature
⇒ bad contacts to N+ Si
Silicide Contacts
Barrier
TiW
TiN Aluminum
Oxide
Oxide
N+
TiSi2
Contact Silicon
PtSi
• Silicides like PtSi, TiSi2 make excellent contacts to Si
• However, they react with Al
• A barrier like TiN or TiW prevents this reaction
Page ‹#›
Silicide Contacts
Similar methods are used for other silicides
Interfacial reactions
Integrity of ohmic contacts due to a

physical barrier between Al and silicide
Schottky barrier reduction
due to Al reaction with PtSi
ΦB (eV)
T (°C)
Page ‹#›
Barriers
Structure Failure Failure Mechanism
Temperature (Reaction products)
(˚C)
Al/PtSi/Si 350 Compound formation
(Al2Pt, Si)
Al/TiSi2/Si 400 Diffusion
(Al5Ti7Si12, Si at 550˚C)
Al/NiSi/Si 400 Compound formation
(Al3Ni, Si)
Al/CoSi2/Si 400 Compound formation
Al9Co2, Si)
Al/Ti/PtSi/Si 450 Compound formation
(Al3Ti)
Al/Ti30W70/PtSi/Si 500 Diffusion
(Al2Pt, Al12W at 500˚C)
Al/TiN/TiSi2/Si 550 Compound formation
(AlN, Al3Ti)
• Silicides react with Al at T < 400°C

• A barrier like TiN or TiW prevents this reaction upto T > 500°C
Outline

•Ohmic contacts
Page ‹#›

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Shallow Junctions

Department of Electrical Engineering

Stanford University 1 Saraswat / EE311 / Shallow Junctions

•Junction/contact scaling issues

Stanford University 2 Saraswat / EE311 / Shallow Junctions

Why do we need to scale junction depth?

Stanford University 3 Saraswat / EE311 / Shallow Junctions

Short Channel Effects on Threshold voltage

We can then approximate the threshold voltage as:

L. Yau, Solid-State Electronics, vol. 17, pp. 1059, 1974

Stanford University 4 Saraswat / EE311 / Shallow Junctions

Sheet resistance increases as junction depth is reduced

Stanford University 5 Saraswat / EE311 / Shallow Junctions

Source/drain Junction Depth

Year 1997 1999 2003 2006 2009 2012

• Source/drain doping requirements show continuing drive to obtain

Gate Length or SDE Depth [nm]

• As Lg scales down, Rsd becomes comparable to Rch

Stanford University 7 Saraswat / EE311 / Shallow Junctions

Impact of Parasitic Series Resistance

Relative Contribution [%]

• Problem even more serious for PMOS

Source: Jason Woo, UCLA

Stanford University 9 Saraswat / EE311 / Shallow Junctions

•Junction/contact scaling issues

Stanford University 10 Saraswat / EE311 / Shallow Junctions

• Solutions to diffusion equations (Fick's laws) gives bulk diffusivity

• In shallow junction technologies, numerous effects alter these values

• Diffusion affected by defects, e.g.,oxidation induced point defects

Stanford University 11 Saraswat / EE311 / Shallow Junctions

Diffusion Affected by Oxidation Induced

Stanford University 12 Saraswat / EE311 / Shallow Junctions

DGB grain boundary diffusion

The worst-case demonstration of the defect enhanced diffusion of dopants is

Stanford University 13 Saraswat / EE311 / Shallow Junctions

Transient Enhanced Diffusion (TED)

40 keV, 10-14 cm-2 B

Stanford University 14 Saraswat / EE311 / Shallow Junctions

• At lower temperature longer times are needed to anneal the damage

Stanford University 15 Saraswat / EE311 / Shallow Junctions

Shallow Junction Formation Technologies

Heavy ions (As, P) Light ions (B)

• Heavy ions (As, P) cause excessive damage turning implanted

• Light ions (B) have buried damage

Stanford University 17 Saraswat / EE311 / Shallow Junctions

Ion Implantation Damage Anneal

Stanford University 18 Saraswat / EE311 / Shallow Junctions

Log concentration (cm-3)

10 sec 1000°C RTA

Stanford University 19 Saraswat / EE311 / Shallow Junctions

Solid Source Diffusion

Depth (nm) Depth (nm)

In COSi2 In Si after silicide removal

Boron profiles after diffusion at 950°C of 50 nm COSi2 implanted

Stanford University 20 Saraswat / EE311 / Shallow Junctions

Stanford University 21 Saraswat / EE311 / Shallow Junctions

Junction Depth Vs. Sheet Resistance Tradeoff

It will be difficult to meet the ITRS scaling

Stanford University 22 Saraswat / EE311 / Shallow Junctions

Extension implants Elevated source/ drain

Silicidation Schottky Source/Drain

Effect of Scaling of Contacts and Junctions

R (total) = Rch + Rparasitic