VLSIGURU DFT TRAINING SCAN INSERTION LAB OBSERVATIONS

SCAN INSERTION LAB OBSERVATIONS

Test Case 12a : -
Problem Definition: -
Design has 3 clocks (one +ve , one -ve, one using both edges)
a) use default scan insertion
Inputs: -

 Synthesis Netlist
 Library Model
 Dofile commands
Outputs: -

 Scan inserted Netlist

 ATPG Dofile
 ATPG Testproc
 Scan Def
What is issue?
Ans : No issue its is defult scan insertion

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 VLSIGURU DFT TRAINING SCAN INSERTION LAB OBSERVATIONS

Observations: -

1) Write block diagram with all DFT inputs?

Reset
ProcClk
FastClk

St81

Input Scan channel Output Scan channel

Top Design: Idma
Scan_en
Scan_chain Input1 Scan_out1

Scan_chain Input2 scanout2

Scan_Chain_input3 Scanout3
Scan_Chain_input4 Scan_out4

2) How many clock domains? FastClk, ProcClk, St81

3) How many resets? Reset
4) Number of scan chains 4 scan chains
5) Clock mixing or not clock mixing? Not clock mixing
6) How many Lockup-latches are added during scan insertion? 2
7) Is it top-down or bottom up approach? Bottom up approach
8) How many terminal lockup latches are added? 0
9) Number of scan flops and non-scan flops in the design? 128 scanable flops and 2 non-
scan elements
10) Chain length? 4 (total 128 memory elements)
#chains:1 , 41
#chains:2, 07
#chain:3, 17
#chain:4 , 63
11)Number of DRC violations? No Violation only warning C3(Note),C8,C9,D5,D7

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VLSIGURU DFT TRAINING SCAN INSERTION LAB OBSERVATIONS

12) Log file: - please note your observations from the log file
Top module is Idma
Number of shift registers =0
Number of INV inserted =0
Number of MUX inserted =0
Number of terminal Lockup latch added =0
No of no scan memory element =130
No of non scan memory element converted to scanable =128
Number of new Pins inserted= 9 (4 scan inputs, 4 scan outputs, scan_en )

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