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  • VHDL

    Cargado por

    Hector Kendall
    2 vistas3 páginas
    códigos vcdl

    Título original

    vhdl

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    © © All Rights Reserved

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    códigos vcdl

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    © All Rights Reserved
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    2 vistas3 páginas

    VHDL

    Cargado por

    Hector Kendall
    códigos vcdl

    Copyright:

    © All Rights Reserved
    Descargue como DOCX, PDF, TXT o lea en línea desde Scribd
    Marcar por contenido inapropiado
    de 3

    library ieee;

    use ieee.std_logic_1164.all;
    entity decodificador is port(
    entradas: in std_logic_vector (3 downto 0);
    sal: out std_logic_vector (7 downto 0));
    end decodificador;
    architecture deco of decodificador is begin
    process (entradas) begin
    case entradas is
    when “0000” => sal <= “01111110”;
    when “0001” => sal <= “00110000”;
    when “0010” => sal <= ”01101101”;
    when “0011” => sal <= “01111001”;
    when “0100” => sal <= “00110011”;
    when “0101” => sal <= “01011011”;
    when “0110” => sal <= “00011111”;
    when “0111” => sal <= “01110000”;

    when “1000” => sal <= “01111111”;


    when “1001” => sal <= “01110011”;
    when others => sal <= “00000001”;

    end case;
    end process;
    end deco;

    library ieee;
    use ieee.std_logic_1164.all;
    entity decodificador is port(
    entradas: in std_logic_vector (3 downto 0);
    sal: out std_logic_vector (7 downto 0));
    end decodificador;
    architecture hexa of decodificador is begin
    process (entradas) begin
    case entradas is
    when “0000” => sal <= “01111110”;
    when “0001” => sal <= “00110000”;
    when “0010” => sal <= ”01101101”;
    when “0011” => sal <= “01111001”;
    when “0100” => sal <= “00110011”;
    when “0101” => sal <= “01011011”;
    when “0110” => sal <= “00011111”;
    when “0111” => sal <= “01110000”;

    when “1000” => sal <= “01111111”;


    when “1001” => sal <= “01110011”;
    when “1010” => sal <= “01110111”;
    when “1011” => sal <= “01111111”;
    when “1100” => sal <= “01001110”;
    when “1101” => sal <= “01111110”;
    when “1110” => sal <= “01001111”;
    when “1111” => sal <= “01000111”;

    when others => sal <= “00000001”;


    end case;
    end process;
    end hexa;

    library ieee;
    use ieee.std_logic_1164.all;
    entity decodificador is port(
    entradas: in std_logic_vector (3 downto 0);
    sal: out std_logic_vector (7 downto 0));
    end decodificador;
    architecture octa of decodificador is begin
    process (entradas) begin
    case entradas is
    when “0000” => sal <= “01111110”;
    when “0001” => sal <= “00110000”;
    when “0010” => sal <= ”01101101”;
    when “0011” => sal <= “01111001”;
    when “0100” => sal <= “00110011”;
    when “0101” => sal <= “01011011”;
    when “0110” => sal <= “00011111”;
    when “0111” => sal <= “01110000”;
    when others => sal <= “00000001”;
    end case;
    end process;
    end octa;

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