library IEEE;

USE IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;

entity CONTADOR is

port (CLK_50, RST : in std_logic;

CLK : out std_logic;
SEVENSEG : out std_logic_vector (6 downto 0)
);

end entity;

architecture RTL of CONTADOR is

signal sCLK : std_logic:='0';

signal sBCD : std_logic_vector(3 downto 0);

begin

--DIVISOR DE FRECUENCIA

DIV_FREC : process (CLK_50)

variable vCNT : integer range 0 to 50_000_000;

begin

if rising_edge(CLK_50) then
vCNT := vCNT+1;

if vCNT = 25_000_000 then

sCLK <= not (sCLK);
vCNT :=0;

--vCNT = 25_000_000 then

--sCLK <= '1';
--elsif vCNT = 50_000_000 then
--sCLK <='0';
--vCNT := 0;

end if;
end if;

end process;

CONT_BDC : process (sCLK, RST)

variable vCNT1: integer range 0 to 9;

begin

if RST = '0' then --- Reset asincrono

vCNT1:=0;

elsif rising_edge (sCLK) then

vCNT1 := vCNT1+1;
if vCNT1 =10 then
vCNT1 := 0;
 end if;
end if;

sBCD <= std_logic_vector( to_unsigned (vCNT1, 4)); --conversion de integer

a std

end process;

---ASIGNACION AL BCD 7 SEG

with sBCD select

SEVENSEG <= "1000000" when "0000",

"1111001" when "0001",
"0100100" when "0010",
"0110000" when "0011",
"0011001" when "0100",
"0010010" when "0101",
"0000011" when "0110",
"1111000" when "0111",
"0000000" when "1000",
"0010000" when "1001",
"0000000" when others;

end RTL;