MOSFET Short Channel Effects

CONTENTS

● What are short channel effects?

● Drain-Induced Barrier Lowering (DIBL)
● Surface scattering
● Velocity saturation
○ When does the velocity of charge carriers saturate?
○ What effect has velocity saturation in the drain
current?
● Impact​ ionization
● Hot Carrier Injection (HCI)

What are short channel effects?

The main drives for reducing the size of the transistors, i.e.,their
lengths, is increasing speed and reducing cost. When you make
circuits smaller, their capacitance reduces, thereby increasing
operating speed. In the same token, smaller circuits allow more
of them in the same wafer, dividing the total cost of a single
wafer among more dies.
However, with great reduction come great problems, in this case
in the form of unwanted side effects, the so called short-channel
effects. When the channel of the MOSFET becomes the same
order of magnitude as the depletion layer width of source and
drain, the transistors start behaving differently, which impacts
performance, modeling and reliability.
These effects can be divided among the following:
● Drain-Induced Barrier Lowering (DIBL)
● Surface scattering
● Velocity saturation
● Impact ionization
● Hot Carrier Injection (HCI)

Drain-Induced Barrier Lowering (DIBL)

This effect is better understood when we see the potential barrier
profile that an electron has to overcome to go from source to
drain. Under normal conditions (​VDS​=0 and ​VGS= ​ 0), there is a
potential barrier that stops the electrons from flowing from
source to drain. The gate voltage has the function of lowering
this barrier down to the point where electrons are able to flow
(left side of figure). Ideally, this would be the only voltage that
would affect the barrier. However, as the channel becomes
shorter, a larger ​VD widens the drain depletion region to a point
that reduces the potential barrier (right side of figure). For this
reason, this effect is aptly called Drain Induced Barrier
Lowering (DIBL).
If this a hard concept to grasp, think about it in terms of
depletion regions only. The drain is close enough to the source
to easily form the depletion region normally created by the gate.
That is, the drain depletion region extends to the source, forming
a unique depletion region. This is known as punchthrough.
Therefore, a high drain voltage can open the bottleneck and
contribute to turn on the transistor as a gate would. This is
essentially equivalent to reducing the threshold voltage of the
transistor, which leads to higher leakage current.

Surface Scattering
The velocity of the charge carriers is defined by the mobility of
that carrier times the electric field along the channel. When the
carriers travel along the channel, they are attracted to the surface
by the electric field created by the gate voltage. As a result, they
keep crashing and bouncing against the surface, during their
travel, following a zig-zagging path. This effectively reduces the
surface mobility of the carriers, in comparison with their bulk
mobility. The change in carrier mobility impacts the
current-voltage relationship of the transistor.

Velocity Saturation
The velocity of carriers are supposed to vary linearly with the
applied electric field as the mobility is considered to be a
constant parameter. However, in a short channel, due to
excessive collisions suffered by the carriers, their velocity
saturates after a critical electric field.The velocity of charge
carriers, such as electrons or holes, is proportional to the electric
field that drives them, but that is only valid for small fields. As
the field gets stronger, their velocity tends to saturate. That
means that above a critical electric field, they tend to stabilize
their speed and eventually cannot move faster. Velocity
saturation is specially seen in short-channel MOSFET
transistors, because they have higher electric fields.

When does the velocity of charge carriers saturate?

The critical velocity is defined by the material the charge
carriers are flowing through. In particular, in diffusions it is
defined by their doping concentration. As a first-order
approximation, the carrier velocity is defined as:

Vd=uE/​ {1+(​E/Ec)​ }

where ​u is the carrier mobility, ​E is the electric field and ​Ec is

the critical electric field (the point at which the velocity tends to
saturate).
The velocity saturates when ​E>>Ec​ and it becomes ,

​ ​uEc​=​Vsat
Vd=

when ​E​<<​Ec

Vd=​uE​ as expected

In silicon, for electrons it is ~10​7 cm/s and for holes around

0.6*10​7​ cm/s.

Where E is combination of vertical and lateral electric field.

Evert=Vgs/L

Elat=Vds/L
 So in short channel devices L is getting reduced so Elat
keeps on increasing and when Vds increases Elat also increases.

Impact ionization
As mentioned earlier, short-channel transistors
create strong lateral electric fields, since the distance between
source and drain is very small. This electric field endows the
charge carriers with high velocity, and therefore, high energy.
The carriers that have high enough energy to cause troubles are
called ​"hot" carriers​. These normally appear close to the drain,
where they have the most energy.

Fig: ​ Substrate leakage current

Since they are traveling through a Silicon lattice, there is a
possibility that they collide with an atom of the structure. Given
enough energy, the energy passed to the atom upon collision can
knock out an electron out of the valence band to the conduction
band. This originates an electron-hole pair: the hole is attracted
to the bulk while the generated electron moves on to the drain.
The substrate current is a good way to measure the impact
ionization effect.

​Fig: C
​ reating an electron-hole pair.

In case the generation of electron-hole pairs is very aggressive,

two catastrophic effects can happen. One of them relates to the
parasitic bipolar transistor that is formed by the junctions
between source-bulk-drain. This transistor is normally turned off
because the bulk is biased at the lowest voltage of the circuit.
However, when holes are flowing through the bulk, they are
causing a voltage drop at the parasitic resistance of the bulk
itself. This, in turn, can active the BJT if the base-emitter
(bulk-source) voltage exceeds 0.6-0.7 V. With the transistor on,
electrons start flowing from the source to the bulk and drain,
which can lead to even more generation of electron-hole pairs.
The most catastrophic case happens when the newly generated
electrons become themselves hot carriers and knock out other
atoms of the lattice. This in turn can create an avalanche effect,
eventually leading to an overrun current that the gate voltage
cannot control.

​ oles flowing through the bulk create a voltage drop that

Fig:H
may turn on the parasitic BJT.
How the Impact Ionisation is reduced in FinFET?
As The width of the gate is reduced in Finfet, the resistance
between source and drain is increased. So the electron will not
gain that much energy to knock the electron out of the atom to
create electron hole pair.
Why Impact Ionisation is more prominent in NMOS?
The channel carriers in Nmos are electrons. Since the
electrons have higher mobility than holes, the electron will gain
energy and knock out the electron from its atom and it will
create e-h pairs. So, Impact Ionisation is more prominent in
NMOS.

Hot Carrier Injection

The hot carrier accelerated by the high electric field can have a
different fate as well. The energy it contains may be sufficient to
enter the oxide and get trapped in it. The trapped electrons alter
the transistor response to the gate voltage in the form of
increased threshold voltage. Over time, the accumulation of
electrons in the oxide causes the so called "ageing" of
transistors. Interestingly, FLASH memories use the same effect
to memorize bits: the negative charge stored in the floating gate
through injection of "hot carriers" changes the threshold voltage
and this change is interpreted as a 1 or 0.

To reduce the formation of "hot" carriers and their negative

effects, the electric field is artificially weakened with the
implantation of lightly-doped drains, beside the heavily-doped
drains. The electric field only needs to be weakened at the drain,
but since the drain terminal is only defined by the operating
point, the implant is added to both terminals of the MOSFET.
The reasoning here is that the depletion regions of the
lightly-doped implant are wider. With wider depletion regions
there is a larger distance between different potentials, which
reduces the electric field. The other side of the coin is that the
parasitic resistances of source and drain are increased.
Lightly doped drains help reduce the strength of lateral electric
fields and therefore, reduce the formation of "hot" carriers.