ACTS TECHNO SOLUTIONS Ltd.

Embedded/IT Developers & Consultants

IEEE BASED VLSI Titles

1. Asynchronous computing in sense amplifier-based Pass Transistor logic

2. Asynchronous protocal converter for Two phase Delay insensitive Global communication

3. Design and Implementation of a Field Programmable CRC circuit Architecture

4. Exploitiong ,memory soft Redundancy for joint improvement of Error Tolorance an

access Efficiency

5. Soft error tolorance and Mitigation in asynchronous Burst-mode circuits

6. Design of network OnChip architecture with generic Algoritham base technique

7. Efficient ON Chip ncrosstalk avoidance CODEC design

8. Fast enhancement of validation test sets for improving the Struct at Fault coverage of

RTL circuits

9. Fault Secure encoder and Decoder for Nano Memory Application

10. Fpga Implementation of FFT Algoritham For real time Applications and DSP application

11. FPGA Implementation of veterbi decoder

12. SDRAM controller

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 13. A Fast Hardware Approach For Approximate ,Efficient Logarithm And Antilogarithm

Computations

14. VLSI Design Of Diminished-One Module 2N+1 Adder Using Circular CarrySelection

15. The Design And FPGA Implementation Of Gf(2^128)Multiplier For Ghash

16. Bz-Fad: A Low-Power Low-Area Multiplier Based On Shift-And -Add Architecture

17. A Full-Adder-Based Methodology For The Design Of Scaling Operation In Residue

Number System

18. Desigining Efficient Online Testable Reversible AddersWith New Reversible Gate

19. Novel Area-Efficient FPGA Architecture For Fir Filtering With Symmetric Signal

Extension

20. Spread Spectrum Image Watermarking With Digital Design

21. A VLSI Progressive Coding For Wavelet-Based Image Compression

22. A Generation Of A Fast RNS Conversion For A New 4 Modulus Base

23. Left to Right Serial Multiplier For Large Numbers on FPGA

24. A Compact AES Encryption Core on Xilinx FPGA

25. A Fast VLSI Dessign Of Sms4 Cliper Based On Twisted BDDS-Box Architecture

26. An Improved RC6 Algorithm With the Same Structure Of Encryption and Decryption

27. A Novel Multiplixer Based Truncated Array Multiplier

28. A New Low Power Test Pattern Generator Using A Variable -Length Ring Counter

29. Power Optimization of Linear Feedback Shift Register for low power BIST

30. Deviation-Based LFSR Reseeding For Test-Data Compression

31. Hardware Algorithm For Variable Presion Multiplication On FPGA

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 32. Superscalar Power Efficient Fast Fourier Transform FFTArchitecture

33. A New High-Speed Architecture For Reed-solomon Decoder

34. Low-Power Leading-Zero Counting And Anticipation Logic For High-Speed Floating

Point Unit

35. Cost-Efficient SHA Hardware Accelerators

36. System Architecture And Implementation Of MIMO Sphere Decoders On FPGA

These all are based on VHDL.

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Ph: 040 23590 123, 92483 123 89; mail: info@actstechno.com