Using the Serial Peripheral Interface (SPI) with

AT91SAMxx Devices

1. Introduction AT91 ARM

This application note describes the use of the Serial Peripheral Interface (SPI) imple- Thumb
mented in AT91SAMxx ARM® Thumb®-based devices.
In this application note:
Microcontrollers
• SPI main features are summarized,
• SPI initialization is described, Application Note
• Characteristics that may be difficult to use are detailed.
Additionally, a software example of an interconnection between two SPIs is described.

6229B–ATARM–06-Aug-06
2. SPI Features
• Supports Communication with Serial External Devices
– Four Chip Selects with External Decoder Support Allow Communication with Up to
15 Peripherals
– Serial Memories, such as DataFlash and 3-wire EEPROMs
– Serial Peripherals, such as ADCs, DACs, LCD Controllers, CAN Controllers and
Sensors
– External Co-processors
• Master or Slave Serial Peripheral Bus Interface
– 8- to 16-bit Programmable Data Length Per Chip Select
– Programmable Phase and Polarity Per Chip Select
– Programmable Transfer Delays Between Consecutive Transfers and Between Clock
and Data Per Chip Select
– Programmable Delay Between Consecutive Transfers
– Selectable Mode Fault Detection
• Connection to PDC Channel Optimizes Data Transfers

3. Description of the SPI

The Serial Peripheral Interface (SPI) circuit is a synchronous serial data link that provides com-
munication with external devices in Master or Slave Mode. It also enables communication
between processors if an external processor is connected to the system.
The Serial Peripheral Interface is essentially a shift register that serially transmits data bits to
other SPIs. During a data transfer, one SPI system acts as the “master”' which controls the data
flow, while the other devices act as “slaves'' which have data shifted into and out by the master.
Different CPUs can take turn being masters (Multiple Master Protocol opposite to Single Master
Protocol where one CPU is always the master while all of the others are always slaves) and one
master may simultaneously shift data into multiple slaves. However, only one slave may drive its
output to write data back to the master at any given time.
A slave device is selected when the master asserts its NSS signal. If multiple slave devices
exist, the master generates a separate slave select signal for each slave (NPCS).
The SPI system consists of two data lines and two control lines:
• Master Out Slave In (MOSI): This data line supplies the output data from the master shifted
into the input(s) of the slave(s).
• Master In Slave Out (MISO): This data line supplies the output data from a slave to the input
of the master. There may be no more than one slave transmitting data during any particular
transfer.
• Serial Clock (SPCK): This control line is driven by the master and regulates the flow of the
data bits. The master may transmit data at a variety of baud rates; the SPCK line cycles once
for each bit that is transmitted.
• Slave Select (NSS): This control line allows slaves to be turned on and off by hardware.

2 Application Note
6229B–ATARM–06-Aug-06
 Application Note
4. Interfacing the SPI
The following figure shows two AT91SAMxx devices exchanging data through the SPI bus.

Figure 4-1. Interfacing the SPI

AT91SAMxx AT91SAMxx

SPI Master SPI Slave

SPCK SPCK
MOSI MOSI
MISO MISO

NPCS0
NPCS1 NSS/NPCS0
NPCS2
NPCS3

SPCK waveforms are

PHA = 0 POL = 0 PHA = 1 POL = 0
SPCK SPCK

MOSI MSB MOSI MSB

PHA = 0 POL = 1 PHA = 1 POL = 1

SPCK SPCK
MOSI MSB MOSI MSB

Selection possibilities are

PSDEC = 0 PSDEC = 1
(NPCSx are directly connected to slaves) (NPCSx are connected to a multiplexor)

SLAVE0 SLAVE0

AT91SAMxx AT91SAMxx
SLAVE1

NPCS0 SLAVE2 NPCS0

NPCS1 NPCS1
NPCS2 NPCS2
NPCS3 SLAVE3 NPCS3 SLAVE14

3
6229B–ATARM–06-Aug-06
 Clock (SPCK) and selection signals (NPCS) are provided by the Master.
• The clock has to be compatible with the Slave in terms of waveform (phase and polarity) and
speed.
In the case where the master addresses an AT91SAMxx device the waveform has no restriction
and the maximum operating baud rate is (Slave Master Clock) / 2. (Depending on I/O speeds
and setup constraints.)
• The selection signal can be either one of the four NPCS lines or a decoding of those lines
with an external logic.
– in the first instance, the SPI can address up to four Slaves without external logic.
– in the second instance, the SPI can address up to fifteen Slaves with the addition of
an external decoder.
Furthermore, in order to be compliant with most SPI devices it is possible to configure the delay
before the SPCK (DLYBS), the delay between consecutive transfers (DLYBCT), the state of the
CS line at the end of the transfer, and to avoid bus contention, the delay between two chip
selects (DLYBCS).
Figure 4-2 illustrates the use of DLYBS, BLYBCT and DLYBCS.

4 Application Note
6229B–ATARM–06-Aug-06
 Application Note
Figure 4-2. DLYBS, BLYBCT and DLYBCS

Start transfer DLYBS ! = 0 End transfer

CSAAT = 1
NPCS

SPCK

MOSI MSB LSB

Example N˚1: A delay between the falling edge of the CS and the first clock edge has been programmed (DLYBS ! = 0).
CS remains active at the end of the transfer (CSAAT = 1).
Start transfer DLYBS ! = 0 End transfer CSAAT = 0

NPCS

SPCK

MOSI MSB LSB

Example N˚2: A delay between the falling edge of the CS and the first clock edge has been programmed (DLYBS != 0).
CS becomes inactive at the end of the transfer (CSAAT = 0).
End of data DLYBCT ! = 0 Start of new data

NPCS0

SPCK

MOSI LSB MSB

Example N˚3: A delay between two consecutive transfers has been inserted (DLYBCT != 0)
Change CS
Start of new data
End of data
DLYBCS ! = 0 DLYBS ! = 0

NPCS0 (1)

NPCS0 (2)

NPCS1

SPCK

MOSI LSB MSB

Example N˚4: Two consecutive transfers between two components with DLYBCS and DLYBS ! = 0
(0) NPCS0 is inactive at the end of the transfer (CSAAT = 0).
(1) NPCS0 remains active at the end of the transfer (CSAAT = 1)

5
6229B–ATARM–06-Aug-06
5. Initialization
The flowchart in Figure 5-1 depicts initialization of the SPI in either Master or Salve mode.

Figure 5-1. SPI Initialization

Start Initialization

Configure SPI PIO

Function: AT91F_SPIx_CfgPIO ()

Enable SPI in the PMC

Function: AT91F_SPIx_CfgPMC ()

Slave
Master ?

Configure the SPI

--> Clock Waveform (Phase, Polarity, Data Length and Baud Rate)
CPHA, CPOL, BITS, SCBR
--> NPCS (connected to a slave directly or not)
PSDEC, PCS Configure the SPI
--> Delay Between Chip Select --> Clock Waveform (Phase, Polarity, Data Length)
DLYBCS CPHA, CPOL, BITS
--> Delay Between Consecutive Transfers
DLYBCT
--> Delay Before SPCK
DLYBS

Use SPI interrupt ?

Enable SPI interrupt in the AIC

No Function: AT91F_AIC_ConfigureIt ()

Enable interrupt
SPI register: SPI_IER

Use PDC ?

Initialize PDC
No - Function: AT91F_PDC_SetTx ()
- Function: AT91F_PDC_SetNextTx ()
- Function: AT91F_PDC_SetRx ()
- Function: AT91F_PDC_SetNextRx ()

Enable PDC
- Function: AT91F_PDC_EnableTx ()
- Function: AT91F_PDC_EnableRx ()

END

6 Application Note
6229B–ATARM–06-Aug-06
 Application Note
6. Use of Last Transfer
Last Transfer is used to make the current Chip Select rise under the conditions listed below.
• The data transfer is finished:
– the shift register is empty, no new data has been written in the transmit register and
DLYBCT is finished.
• The current Chip Select is programmed to remain active at the end of the transfer
(CSAAT = 1).
• LASTXFER bits located in the SPI_CR register must be used when CS lines are directly
connected to slaves (PSDEC = 0).
• LASTXFER bits located in the SPI_CSRx registers must be used when CS lines are
connected to an external decoder (PSDEC = 1).
Figure 6-1 gives an example of using LASTXFER.

Figure 6-1. LASTXFER

1 2 3 4 5 6
DLYBCS
+
DLYBS DLYBS
LASTXFER

NPCSa

NPCSb

NPCSc

MOSI LSB MSB LSB MSB LSB

NCPSa configuration is: CSAAT = 0 / BLYBS = 0 / DBYBCT = 0

NCPSb configuration is: CSAAT = 1 / BLYBS != 0 / DBYBCT = 0
NCPSc configuration is: CSAAT = 1 / BLYBS = 0 / DBYBCT = 0

1. NPCSa rises at the end of the transfer, immediately NPCSb falls,

2. The data to transmit on NPCSb starts after DLYBS,
3. NPCSb rises at the end of the transfer because it’s CSAAT = 0 and the data transfer is
finished,
4. NPCSc falls as soon as data is written in it’s TDR and the data is immediately transmit-
ted because DLYBS = 0,
5. The transfer is finished and NPCSc remains low because it’s CSAAT = 1,
6. LASTXFER is set to 1 and NPCSc rises.

7
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7. Software Example
The software example associated with this document describes how to use an SPI in Master or
Slave mode.

7.1 Hardware Settings

It is important to note that the hardware support used to develop this software was an
AT91SAM7S-EK board that includes an AT91SAM7S256.
Atmel.com has more information on the AT91SAM7S-EK.
Figure 7-1 shows the connection between the Master and the Slave.

Figure 7-1. Master and Slave Connection

AT91SAM7S-EK AT91SAM7S-EK
+ +
SAM7S256 SAM7S256

MASTER SPI SLAVE SPI

PA11 / NPCS0 NSS / PA11
PA13 / MOSI MOSI / PA13
PA12 / MISO MISO / PA12
G G
N PA14 / SPCK SPCK / PA14 N
D D

7.2 Software Considerations

• SPI is working under interrupt.
• Software files are organized as follows:

Cstartup.s79
Initialization Cstartup_SAM7.c
main.c / main.h
Interrupt treatment handler.c / handler.h
SPI main features spi_main.c / spi_main.h
SPI master spi_master.c / spi_master.h
SPI slave: spi_slave.c / spi_slave.h

8 Application Note
6229B–ATARM–06-Aug-06
 Application Note
7.3 Software Flowchart
The flowchart shown in Figure 7-2 illustrates the software example.

Figure 7-2. Software Example

Start

Slave Slave
Master/Slave ? Master/Slave ?

Master config is Master config is

Pha = Pol = 0 Pha = Pol = 1
Data length = 8 bits Slave config is Data length = 16 bits Slave config is
SCBR = MCK / 8 Pha = Pol = 0 SCBR = MCK / 16 Pha = Pol = 1
PS = PSDEC = 0 Data length = 8 bits PS = PSDEC = 0 Data length =16 bits
CSAAT = 0 CSAAT = 1
DLYBS = 0 DLYBS = 0xFF
DLYBCT = 0 DLYBCT = 0xFF

Send / receive a data Send / receive a data

Wrong data
Wrong data
Recieved data is ok? Recieved data is ok?

Error_count = Error_count =
Error_count + 1 Error_count + 1

End

9
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Revision History

Change
Doc. Rev Comments Request Ref.
6229A First issue
6229B Remove references to internal documents 3017

10 Application Note
6229B–ATARM–06-Aug-06
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