DIGITAL COMMUNICATION LAB MANUAL

For

VI Semester B.Tech (Electronics Engineering)

Digital Communication Lab

Dept. of Electronics Engineering

IIT (ISM) Dhanbad
 Digital Communication Lab

List of Experiment

1. Generation of pseudo noise random sequence.

2. Recovery of clock from pn sequence.
3. To study Pulse Code Modulation and Demodulation technique.
4. To design a circuit for FSK modulation and demodulation.
5. To analyze the DM and demodulation of DM signal.
6. To design a PSK modulator.
7. Realization of Matched filter.
 Experiment no: 1

Aim: Generation of pseudo noise random sequence.

Apparatus used: IC 74164 (8 bit serial input parallel out shift registers), IC
7486 (XOR Gate), MSO, function generator and connecting wires

Theory: A truly random sequence of binary symbols (ones and zeros, for
simplicity) would be one for which a knowledge of the complete past history of
the sequence would be of no assistance in predicting the next symbol, i.e. the
probability that the next symbol would be a one or zero would still be one-half
even if the complete sequence of previous output were available. Such a
sequence would have to be produced by passing an analog noise source through
a comparator sampled at regular clock intervals or some other scheme such as
tossing a fair coin. Such a sequence is sometime referred to as digital noise.
PN noise sequences are certain binary
sequences of length N=2 -1 that satisfies a linear recurrence given by the
n

corresponding primitive polymers of degree n. For a sequence to be pseudo

noise it should follow basic rules given below:
1. The relative frequency of 0 and 1 are each half.
2. If a PN sequence is shifted by any non zero number of elements the resulting
sequence will have equal number of arguments with respect to the original
sequence.

Procedure:

! A PN sequence can be generated by using the diagram as shown in figure

! Using the circuit shown the generated sequence is
10101111000100110010111000
! The bits are repeated after every 15 bits since 4 registers are used.
! If n registers are used then 2n-1 bit period sequence is formed.
Observation:

TABLE: 1

Input Output
Clear clock A B QA QB ....................................................... QH

L X X X L L ...........................................L
H L X X QA QB ........... .......... .......... .......... .......... . ..Q H
H H H H H QA .......... .......... .......... .......... .......... . QG
H H L X L QA ............... .......... .......... .......... ....... QG
H H X L L QA ........... .......... .......... .......... .......... . QG

Table 2:

Input to XOR Gate Sequence Generated Length of sequence

A B
101011110001001101011 15
QC QD

QA QD 01100100011101011001 15

QA QC 11101001110100 7

QA QB 110110110110 3

QB QC 11100101110010 7

Result:

1. The above sequences are generated.

2. If n registers are used then a PN sequence with 2n-1 bits are generated.
 Experiment no: 2

Aim: Recovery of clock from pn sequence.

Apparatus and components used: IC 74123(Dual monostable multivibrator),

IC 7486, IC 741, Resistors and capacitor, function generator and connecting
wires.

Theory: In spread spectrum system, the signal spreading code is the so called
the pseudo noise(PN) sequence which is generally periodic and consists of a
periodic coded sequence of 1’s and 0’s with certain autocorrelation properties.
These signals are pseudo random is as much as they appear to be unpredictable
to be an outsider, though they appear or can be generated by deterministic
means by the person for whom they are intended. When a shift resister has a
non-zero initial state and the output is fed back to the input, the unit acts as
periodic sequence generation. In general the longest possible sequence from a
resister n stages is N= 2n– 1). The corresponding output is called a maximum
length sequence or PN sequence.
The names pseudo noise comes from the correlation properties of sequence of N,
is very large and Tb is very small, then the PN signal acts essentially like white
noise with small DC component and hence is called Pseudo Noise Sequence.
To generate any sequence of serial bits (here it is PN Sequence) the first step is
to recover the clock from the data and then use it for sampling the data to
extract the individual bits.
In this experiment we perform the first part that is the recovery of clock from
the PN sequence.

Procedure:

An edge detection circuit is required to detect all the 0 to 1 and 1 to 0 transition

of the incoming data. This is similar to the phased lock loop device detecting
phase changes.
The circuit needs to generate a pulse from either 0 to 1 or 1 to 0 transitions of the
incoming data. This function can be seen for this we use IC 74123 that is dual
monostable mutivibrator.
The output at the rising edge and the falling edge are added and then passed
through a band pass filter circuit.

The final clock is obtained by passing through zero detector circuit.

 Input Output

A B CLK Q Q’
H X H L H
X L H L H
L H
H H
X X L L H

Result: The final output is connected to the digital outputs of MSO and clock is
generated
 Experiment no: 3

Aim: To study Pulse Code Modulation and Demodulation technique .

Apparatus and Component Required: IC 7474, IC 7486, IC 741, Resistors and

capacitor, function generator and connecting wires

Theory:

The pulse code modulator technique samples the input signal x(t) at a sampling
frequency. This sampled variable amplitude pulse is then digitalized by the
analog to digital converter. Figure (1) shows the PCM generator.

Figure.(1): PCM modulator

In the PCM generator, the signal is first passed through sampler which is
sampled at a rate of (fs) where:

The output of the sampler x(nTs) which is discrete in time is fed to a q level
quantizer. The quantizer compares the input x(nTs) with it's fixed levels. It
assigns any one of the digital level to x(nTs) that results in minimum distortion
or error. The error is called quantization error, thus the output of the quantizer is
a digital level called q(nTs). The quantized signal level q(nTs) is binary encode.
The encoder converts the input signal to v digits binary word.

Figure.(2) A sampled signal and the quantized levels

Figure.(3) shows the block diagram of the PCM receiver. The
receiver starts by reshaping the received pulses, removes the noise and
then converts the binary bits to analog. The received samples are then
filtered by a low pass filter; the cut off frequency is at fc.
fc= fm
where fm: is the highest frequency component in the original signal.

Figure. (3): PCM demodulator

It is impossible to reconstruct the original signal x(t) because of the
permanent quantization error introduced during quantization at the
transmitter. The quantization error can be reduced by the increasing
quantization levels. This corresponds to the increase of bits per
sample (more information). But increasing bits (v) increases the signaling rate
and requires a large transmission bandwidth. The choice of the
parameter for the number of quantization levels must be acceptable with
the quantization noise (quantization error). Figure.(4) shows the
reconstructed signal

Figure (4): The reconstructed signal

Procedure:

1. The given below circuit is used for 3 bit PCM.

2. In PCM we start with the sampling of input sinusoidal 1 kHz analog
signal. In sampling we multiply input signal with 10 kHz (two times
greater than input signal frequency) square wave signal. Sampling output
is taken from common collector BJT.
3. Use sampling output as one input of comparator and the other input of
comparator is different potential of Vref. For 3 bit PCM 7 comparator is
use. The output of comparator is in digital form which store in D flipflop
using 7474 IC.
4. The digital output is encoded using XOR gates. The composition of XOR
gates is given in encoder circuit. Here 3 outputs are because we encode
each sampled value using 3 bit.
5. In demodulation we convert encoded digital data to analog data. The
output of D/A converter is not smooth. To make it smooth (or accurate)
pass from low pass filter.
Result:

Precaution:

1. The connections should be made properly and tightly.

2. Check all the connections before switching ON the kit.
 Experiment no: 4

AIM: To design a circuit for FSK modulation and demodulation

APPARATUS: Mixed signal oscilloscope (MSO), function generator, BNC

probe
COMPONENT: IC 4016 Quad bilateral switch, 741 op-amps, Diodes,
resistance, capacitor

THEORY:

Frequency Shift Keying is the process generating a modulated signal

from a digital data input. If the incoming bit is 1, a signal with frequency f1 is
sent for the duration of the bit. If the bit is 0, a signal with frequency f2 is sent
for the duration of this bit. This is the basic principle behind FSK modulation.
Mathematically, the FSK signals transmitted for binary ones and binary zeros
are:
s1(t) = A cos(ω1t + θc), 0 < t ≤ T
s2(t) = A cos(ω2t + θc), 0 < t ≤ T
In the modulator circuit a binary sequence which comes from PN
sequence is applied to quad bilateral switch. Depend on the input signal (1/0),
f1/f2 frequency signal comes as an output of switch. We add these two signal
using inverting op-amps and get the final modulated FSK signal.

Functional diagram of 4016 IC:

The 4016 contains 4 analogue bilateral switches, each with an active-high enable
input (A) and two input/outputs (X and Y). When the enable input is high, the X
and Y terminals are connected by low impedance; this is the on condition.
When the enable is low, there is a high impedance path between X and Y, and
the switch is off.
In the demodulator circuit, the FSK modulated signal is applied to two
band pass filter with frequency f1 and f2. This filter passes the selected
frequency and rejects the other. The output is then passed through a Rectifier
circuit and the output is now above zero volts only. It is then passed through a
comparator; if the input to the comparator is greater than threshold value, the
output is 1, else it is 0. This digital output of the comparator is the demodulated
FSK output.

CIRCUIT DIAGRAM:
PROCEDURE:
1. Make connections as shown in the circuit diagram.
2. Set the input signal and carrier signal.
3. Obtain FSK signal
4. Tabulate the output data and draw the graph.
5. Justify the obtained output with theoretical calculation.

RESULT:

The FSK modulator and demodulator circuit has been studied.

PRECAUTION:
1. The connections should be made properly and tightly.
2. Check all the connections before switching ON the kit.
 Experiment no: 5 Understand Circuit

AIM: To analyze the DM and demodulation of DM signal

APPARATUS: DSO, function generator, BNC probe

COMPONENT: IC 7474, IC 741, Resistance, Capacitance, zener diode

THEORY:
Delta Modulation (DM) is a simplified PCM. In some type of signals,
the neighboring samples are closely correlated with each other. Therefore, once
a sample value is known this enables the determination of the following sample
values most probably. Thus, instead of sending the real value of each sample at
each time, differences (variances) between adjacent samples are sent in DM.
The baseband signal m (t) and its quantized approximation m’ (t)
are applied as inputs to a comparator. A comparator simply makes a comparison
between inputs. If signal amplitude has increased, then modulators output is at
logic level 1. If the signal amplitude has decreased, the modulator output is at
logic level 0. Thus the output from the modulator is a series of 0’s and 1’s to
indicate rise and fall of the waveform since the previous value. The comparator
output is then latched into a D flip-flop which is clocked by the transmitter
clock. Thus the output of the flip-flop is a latched 1 or 0 synchronous with the
transmitter clock edge. The binary sequence is transmitted to receive and is also
fed to the unipolar to bipolar converter. This block converts logic 0 to voltage
level of +V and 1 to voltage level of – V. The bipolar output is applied to the
integrator whose output is:
a) Rising linear ramp signal when – V is applied to it
b) Falling linear ramp signal when + V is applied to it.
The integrator output is then connected to the –ve terminal of voltage
comparator. The integrator output is a saw tooth-like waveform. This is
approximation value of base band signal m (t).
In demodulation of DM signals reverse process is taken, the signal
from the integrator, which is a sawtooth approximation to the message, is
adjusted with the amplifier to match it as closely as possible. This is the delta
modulated signal. Lowpass filtering of the sawtooth (from the demodulator)
gives a better approximation to the message. But there will be accompanying
noise and distortion, products of the approximation process at the modulator.
The unwanted products of the modulation process, observed at the receiver, are
of two kinds. These are due to ‘slope overload’, and ‘granularity’.

Slope overload: This occurs when the sawtooth approximation cannot keep up
with the rate-of change of the input signal in the regions of greatest slope.
The step size is reasonable for those sections of the sampled waveform of small
slope, but the approximation is poor elsewhere. This is ‘slope overload’, due to
too small a step.
To reduce the possibility of slope overload the step size can be increased (for
the same sampling rate). The sawtooth is better able to match the message in the
regions of steep slope. An alternative method of slope overload reduction is to
increase the sampling rate. Slope overload is illustrated in below figure

Granular noise: The sawtooth follows the message being sampled quite well in
the regions of small slope. To reduce the slope overload the step size is
increased, and now the match over the regions of small slope has been degraded.
The degradation shows up, at the demodulator, as increased quantizing noise, or
‘granularity’.

CIRCUIT DIAGRAM:
PROCEDURE:
1. Make connections as shown in the circuit diagram.
2. Set the input signal and carrier signal.
3. Obtain DM signal.
4. Justify the obtained output with theoretical calculation

RESULT:

PRECAUTION:

1. The connections should be made properly and tightly.

2. Check all the connections before switching ON the kit.
 Experiment no: 6

AIM: To design a PSK modulator

APPARATUS: MSO, Conneting wires, BNC probes

COMPONENT: IC LM 1496, IC 741

THEORY:

Phase shift keying involves the phase change of the carrier sine wave
between 0 and 180 in accordance with the data stream to be transmitted. PSK is
also known as Phase reversal keying. PSK modulator is shown in figure 1.
Functionally, the PSK modulator is very similar to the ASK modulator. Both
uses balanced modulator to multiply the carrier with the modulating signal. But
in contrast to ASK techniques, the digital signal applied to the modulator input
for PSK generation is bipolar i.e. have equal +ve and –ve voltage levels. The
unipolar – bipolar converter converts the unipolar data stream to bipolar data.
At receiver, the square loop detector circuit is used to demodulate the
transmitted PSK signal. The demodulator is shown in figure 2. The incoming
PSK signal with 0 & 180 phase changes is first fed to the signal square, which
multiplies the input signal by itself. The phase adjust circuit allows the phase of
the digital signal to be adjusted w.r.t the input PSK signal. Also its O/P controls
the closing of an analog switch. When the output is high the switch closes and
the original PSK signal is switched through the detector.

PSK is a digital modulation scheme that conveys data by changing, or

modulating, the phase of a reference signal (the carrier wave). PSK uses a finite
number of phases, each assigned a unique pattern of binary digits. Usually, each
phase encodes an equal number of bits. Each pattern of bits forms the symbol
that is represented by the particular phase. The demodulator, which is designed
specifically for the symbol-set used by the modulator, determines the phase of
the received signal and maps it back to the symbol it represents, thus recovering
the original data. In a coherent binary PSK system, the pair of signal S1(t) and
S2 (t) used to represent binary symbols 1 & 0 are defined by
S1 (t) = √2Eb/ Tb Cos 2πfct
S2 (t) =√2Eb/Tb (2πfct+π) = - √ 2Eb/Tb Cos 2πfct
where 0 ≤ t< Tb and Eb = Transmitted signed energy for bit. The carrier
frequency fc =n/Tb for some fixed integer n.

Basic structural diagram of PSK modulator is given as:

In this experiment, LM1496 is used to implement the balanced modulator as
shown in circuit diagram.
The circuit diagram of 1-bit PSK which the carrier signal and data signal are
single-ended input is given below. In IC LM 1496 Pin 10 is the carrier input and
pin 1 is data signal is passed through the unipolar to bipolar converter. Pin 6 and
12 is the output of balance modulator which is PSK signal. Pin 2 and 3 are use
for gain adjustment so; R26 determines the gain of the circuit. R12 determines
the bias voltage of the circuit.

CIRCUIT DIAGRAM:
PROCEDURE: 1. Make connections as shown in the circuit diagram.
2. Set the input signal and carrier signal.
3. Obtain PSK signal
4. Justify the obtained output with theoretical calculation.

RESULT:

PRECAUTION:
1. The connections should be made properly and tightly.
2. Check all the connections before switching ON the kit.
 Experiment no: 7

AIM: Realization of Matched filter

APPARATUS: MSO, Bread board, Connecting wires, Function generator

COMPONENT: IC 74164, IC 7483, IC 7485

THEORY: The matched filter is the optimal linear filter for maximizing the
signal to noise ratio (SNR) in the presence of additive stochastic noise. If a
signal s(t) gets corrupted by Additive white Gaussian noise(AWGN), the
optimum filter with impulse response matched to s(t)maximize the output SNR.
This optimum filter is therefore called as matched filter. Matched filter can be
explained with the help of block diagram given below:

The filter input x(t) consists of a pulse signal g(t) corrupted by additive channel
noise w(t), given as: .
where T is an arbitrary observation interval. The pulse signal g(t) may represent
a binary symbol 1 or 0 in a digital communication system. The w(t) is the
sample function of a white noise process of zero mean and power spectral
density No/2.The source of uncertainty lies in the noise w(t).The function of the
receiver is to detect the pulse signal g(t) in an optimum manner, given the
received signal x(t).To satisfy this requirement, we have to optimize the design
of the filter so as to minimize the effects of noise at the filter output in some
statistical sense, and thereby enhance the detection of the pulse signal g(t).
Since the filter is linear, the resulting output y(t) may be expressed as
.
where go(t) and n(t) are produced by the signal and noise components of the
input x(t), respectively. A simple way of describing the requirement that the
output signal component go(t) be considerably greater than the output noise
component n(t) is to have the filter make the instantaneous power in the output
signal go(t), measured at time t = T, as large as possible compared with the
average power of the output noise n(t). This is equivalent to maximizing the
peak pulse signal-to-noise ratio.
Basically, matched filter is matched to a known signal s(t), is characterized by
an impulse response h(t) which is a time reversed and delayed version of s(t) i.e.

h(t)=s(T-t). The output SNR of a matched filter depends only on the ratio of the
signal energy to the power spectral density of the white noise at the filter input.
SNR (max) = (2E/No).

In this experiment, firstly a PN sequence is generated parallel by IC 74164. Then

the 7 length PN sequence is added bit by bit with the help of IC 7483.Then the
output B is compared to original sequence A with the help of IC 7485.
Circuit Diagram:
Procedure: 1. Make connections as shown in the circuit diagram.
2. Convert serial PN sequence into shifted parallel PN sequence
using IC 74164.
3. Add bit by bit of the PN sequence (after converting 0’s to 1’s and vice
versa) by IC 7483.
4. Compare the output sequence with the original sequence by using IC
7485.
5. Justify the obtained output with theoretical calculation.

Result:

Precaution:

1. The connections should be made properly and tightly.

2. Check all the connections before switching ON the kit.