Tiduef8 PDF

TI Designs: TIDA-010028
330-W, 95.5% Efficiency and 18-W/in3 Density, Bridgeless

PFC+LLC Reference Design
Description Features
This reference design is a compact, high efficiency, • Full load efficiency at 230 V AC > 95.5% and >94%
bridgeless 330-W, 19.5-V output AC/DC reference at 90 V AC
design. This design consists of a front-end, • High power factor > 0.99, meeting PFC regulations
bidirectional bridgeless boost power factor correction and current THD as per IEC 61000-3- 2 Class A
(PFC) based on the UCC28180A device, achieving • < 0.25-W standby power with burst mode in both
end-to-end peak efficiency of > 94% at 90 V AC input PFC and LLC stages
and > 95.5% at 230 V AC input. The DC/DC is
implemented using the HB-LLC stage implemented • ZCS avoidance feature and OVP sensing feature in
using our UCC256301 device. The design uses the LLC controller improves robustness and protects
UCC24624 device for synchronous rectification at the systems from overcurrent, short circuit, and
secondary side to improve efficiency. overvoltage to ensure safety
• Small 152 mm × 75 mm × 25 mm PCB form factor
Resources
Applications
TIDA-010028 Design Folder
• Consumer AC/DC
UCC28180 Product Folder
• DIN Rail Power Supply
UCC24624 Product Folder • Industrial AC/DC
CSD18533Q5A Product Folder • PC Power Supply
LP2951 Product Folder
ATL431 Product Folder
ASK Our E2E™ Experts
F_VCC
Source
LLC_VCC
Source
310-
400 V
GND
F_VCC
0 …F RET
85V ± 265V
AC UCC5350
UCC24624
Hall 19.5V/17A
Sensor
CSD18532Q5B
UCC27710
PFC_VCC UCC256301 OPTO ATL431

Glue
Logic
LLC_VCC
INA190
LATCH
UCC28180 OPTO
OPA4170 LP339 TMP236
LOWPOWER_MODE ISO_5V
OPTO
PFC_VCC LLC_VCC LM4041
LP2951
TIDUEF8 – December 2018 330-W, 95.5% Efficiency and 18-W/in3 Density, Bridgeless PFC+LLC 1
Submit Documentation Feedback Reference Design
Copyright © 2018, Texas Instruments Incorporated
System Description www.ti.com
An IMPORTANT NOTICE at the end of this TI reference design addresses authorized use, intellectual property matters and other
important disclaimers and information.
1 System Description
This reference design is a 330-W, high-efficiency AC/DC power supply for consumer and industrial
applications. With a growing trend to increase the power density and higher efficiency, the overall losses
in the power supply need to be significantly reduced. This brings out the need to adopt bridgeless PFC
topologies and soft-switched isolated DC/DC power stage. Bridgeless PFC topologies eliminate the
conduction loss in the input diode bridge, which forms a significant portion (up to 2% ) of the losses in the
AC/DC power supply at low input voltages from 90 V - 140 V AC.
This design consists of a bidirectional bridgeless CCM boost PFC which operates from an input voltage
range of 85–265 V AC RMS with efficiencies >97% at 90-V AC input. The second stage is made up of an
isolated half bridge LLC stage which generates a 19.5 V, 17-A nominal output with approximately 97.2%
efficiency. This design demonstrates high efficiency operation in a small form factor (152 × 75 × 25 mm)
and delivers continuous 330 W of power over the entire input operating voltage range from 85- to 265-V
AC. It gives an efficiency of > 95.5% for 230-V AC nominal operation and 94% for 90-V AC nominal
operation. The CCM PFC stage is controlled by the UCC28180 fixed frequency PFC IC. Additional circuits
to implement the bridgeless topology using the UCC28180 have been incorporated. The HB-LLC power
stage is controlled through the stage of the art UCC256301 resonant controller which implements current
mode control for increased control bandwidth. This increased control bandwidth reduces the output
capacitors required to suppress the AC ripple on the output. To achieve high efficiency, the output of the
LLC stage uses synchronous rectification based on the UCC24624 IC and the CSD18533Q5A MOSFET.
1.1 Key System Specifications
Table 1. Key System Specifications

PARAMETER SYMBOL TEST CONDITIONS MIN NOM MAX UNIT
INPUT CONDITIONS
Input voltage VINAC 85 230 265 VAC
Frequency fLINE 47 50 63 Hz
No load power PSB 250 mW
OUTPUT CONDITIONS
Output voltage 19.5 V
Output current 17 A
Line regulation Both current and voltage 0.5 %
Load regulation Both current and voltage 1 %
Output voltage ripple Peak to peak 250 mV
Output power (nominal) Po 330 W
SYSTEM CHARACTERISTICS
Efficiency VIN = 230 V AC RMS 95.5 %
VIN =90 V AC RMS 94 %
Protections Output overcurrent 25 A
Output overvoltage 22 V
Operating ambient Open frame –10 25 55 C
Standards and norms Power Line Harmonics As per EN55011,
EN55022 Class B
Conducted Emissions EN55022 Class B
EFT As per IEC-61000-4-4
Surge As per IEC-61000-4-5
Board form factor (FR4 Length × Breadth × Height 152 × 75 × 25 mm
material, 2 layer)
2 330-W, 95.5% Efficiency and 18-W/in3 Density, Bridgeless PFC+LLC TIDUEF8 – December 2018
Reference Design Submit Documentation Feedback
www.ti.com System Overview
2 System Overview
2.1 Block Diagram
Figure 1. TIDA-010028 Block Diagram

F_VCC
Source
LLC_VCC
Source
310-
400 V
GND
F_VCC
0 …F RET
85V ± 265V
AC UCC5350
UCC24624
Hall 19.5V/17A
Sensor
CSD18532Q5B
UCC27710
PFC_VCC UCC256301 OPTO ATL431

Glue
Logic
LLC_VCC
INA190
LATCH
UCC28180 OPTO
OPA4170 LP339 TMP236
LOWPOWER_MODE ISO_5V
OPTO
PFC_VCC LLC_VCC LM4041
LP2951
2.2 Design Considerations

This design uses as an analog bridgeless PFC topology, followed by an isolated DC/DC LLC power stage
to achieve high efficiency across universal input voltage conditions. The use of the bridgeless PFC power
stage helps eliminate the input diode bridge loss, leading to significant (approximately 2%) efficiency
improvement at full load and the lowest input voltage range of 90 VAC. More details on the component
selection, design equations, and topology descriptions are given in the following section.
2.3 Highlighted Products

The following highlighted products are used in this reference design. Key features for selecting the
devices for this reference design are explained in the following sections . Complete details of the
highlighted devices is referred to in the respective product data sheets.
2.3.1 UCC28180
To implement the high-performance CCM PFC, the UCC28180 is the preferred controller because it offers
a series of benefits to address the next generation needs of low THD norms for power tools. The
UCC28180 is a high-performance, CCM compact, 8-pin programmable frequency PFC controller. Its wide
and programmable operating frequency provides flexibility in design. Its trimmed current loop circuits help
achieve a less than 5% THD from medium-to-full load (50% to 100%). Reduced current sense threshold
helps use a 50% smaller shunt resistor, resulting in lower power dissipation while maintaining low THD.
The UCC28180 also has the following system protection features, which greatly improves reliability and
further simplifies the design:
• Soft overcurrent
• Cycle-by-cycle peak current limit
• Output overvoltage
• Open pin protections (ISENSE, VSENSE
System Overview www.ti.com
In this design, the UCC28180 is used to implement bridgeless CCM PFC with some modifications to the
input current sensing, gate driving and external burst mode logic to further reduce the standby power
consumption.
2.3.2 UCC256301
LLC resonant converters are one of the most widely used topologies for implementing medium-to-high
power isolated DC/DC power stages in industrial power supplies. These converters are popular due to
their ability to achieve soft-switching (ZVS turnon) for the high-voltage MOSFET, improving he overall
efficiency of the system. LLC converters in industrial power supplies do face some specific requirements.
Some industrial power supplies need to support an overload (up to 1.5 times the nominal load) for a short
period of time. The LLC converter must not enter the capacitive (ZCS) region during the overload
operation; otherwise, it can be catastrophic. With its ZCS avoidance feature, the UCC256301 can ensure
that the system does not enter the ZCS region under all operating conditions, keeping the system safe.
The UCC256301 provides a wide operating frequency range from 35 kHz to 1 MHz to make it easier to
design wide output voltage range using an LLC converter. The UCC256301 with its unique hybrid
hysteretic control provides excellent line and load transient response, minimizing the need for output filter
capacitors. Its wide frequency range can be used to reduce the PFC bulk capacitor required to meet the
holdup time requirement in the industrial power supplies. With the integrated high-voltage gate drive, X-
capacitor discharge function, and addition output overvoltage protection, the UCC256301 reduces the
amount of external discreet components required to implement a high-efficiency industrial power supply.
2.3.3 UCC24624
The UCC24624 high-performance synchronous rectifier (SR) controller is dedicated for LLC resonant
converters . Two independent SR control channels with Interlock to Prevent Shoot-Through are integrated
into the single package to minimize the external components and allow for easy PCB layout. With Low
Standby Current of 175 µA and Automatic Standby Mode Detection, this part reduces the overall standby
power consumption of the system.
2.3.4 CSD18533Q5A
The is a 4.7 mΩ, 60 V, SON 5 × 6 mm NexFET power MOSFET with ultra low Qg, designed to minimize
losses in power conversion applications. In this design two MOSFETs are used in parallel to replace each
output diode.
2.4 System Design Theory

This reference design provides a universal AC mains-powered, 330-W nominal output at 19.5 V and 17 A.
This design comprises a front-end AC/DC PFC power stage followed by an isolated DC/DC LLC power
stage. The front end AC/DC stage is a bridgeless CCM PFC to improve the overall efficiency of the
system.
2.4.1 Working and Calculations for the Bidirectional Bridgeless PFC Stage
In this section, the working and design calculations for the UCC28180-based, bridgeless PFC converter
are detailed.
2.4.1.1 Design Parameters
Table 2. PFC Stage Specifications

PARAMETER MIN TYP MAX UNIT
INPUT
VIN Input voltage 85 265 V AC
fLINE Input frequency 47 63 Hz
OUTPUT
VOUT Output voltage 397 VDC
POUT(nom) Output Power 330 W
POUT(max) Output Power 350 W
Line Regulation 5%
Load Regulation 5%
PF Targeted power factor 0.99
η Targeted efficiency 97.2%
FSW Mean Switching Frequency 95 kHz
2.4.1.2 Bidirectional Bridgeless PFC Working

Figure 2 shows the bidirectional bridgeless PFC power stage. Figure 3 shows the power stage for the +Ve
half-cycle and Figure 4 shows the power stage for the –Ve half-cycle.
Figure 2. Bidirectional Bridgeless PFC Power Stage
Q3
D1
Q1 Q2
85V ± 265V DRV 400V DC

AC
D2 Q4
Figure 3. Bidirectional Bridgeless PFC Working in +Ve Half Cycle
Q3
D1
Q1 Q2
85V ± 265V 400V DC

AC
D2 Q4
In the +Ve half-cycle, In the inductor charging phase switch Q1 and Q2 conduct current. In the
freewheeling phase ultra-fast/SiC diode D1 and low freq MOSFET Q4/low speed diode used in its place
conduct the inductor current. Figure 4 shows the detailed working waveform during the +Ve half-cycle.
Figure 4. Bidirectional Bridgeless PFC Working in -Ve Half Cycle
Q3
D1
Q1 Q2
85V ± 265V 400V DC

AC
D2 Q4
When Q1 is the main switch. Q2 turns on and turns off in ZVS. The control signal to Q1, Q2 is the same.
When Q1, Q2 is turned-off, current freewheels through D1 and Q4. The RMS current flowing through the
low freq MOSFET/diode is low as it only conducts during freewheeling phase. Since Q1 or Q2 is hard-
switched (depending on half-cycle), output capacitance limits operating frequency
Figure 5. Key Switching Waveforms in Bidirectional Bridgeless PFC
IL
Vgs1,
Vgs2
Ids1
Id1
Ids4
In the -Ve half-cycle, the inductor charging phase switch Q1 and Q2 conduct current. In the freewheeling
phase ultra-fast/SiC diode D2 and low freq MOSFET Q3/ low speed diode used in its place conduct the
inductor current.
2.4.1.3 Current Calculations

The input fuse, bridge rectifier, and input capacitor are selected based upon the input current calculations.
First, determine the maximum average output current, IOUT(max):
POUT max
I OUT max max
V OUT max
(1)
340
I OUT max 0.90 A
375 (2)
The maximum input RMS line current, IIN_RMS(max), is calculated using the parameters from Table 2 and the
efficiency and power factor initial assumptions:
POUT max
I INrms max
K u V IN min u PF (3)
340
I INrms max 3.925 A
0.97 u 90 u 0.99 (4)
2.4.1.4 Boost Inductor

To dimension the boost inductor, the maximum allowed ripple current is calculated first. The maximum
ripple current is observed at the lowest input voltage and maximum load. Assuming a maximum 40%
ripple in the inductor current, gives us a ripple current:
I INripple max 'ripple u I INrms max
(5)
I INripple max 0.4 u 2 u 3.925 2.21 A
(6)
The duty cycle, DUTY(max), at the peak of the minimum input voltage can be calculated as:
V OUT max V INrms max u 2

DUTYmax
V OUT max (7)
375 1.414 u 90
DUTYmax 0.660
375 (8)
The minimum value of the boost inductor is calculated based upon the acceptable ripple current, , at a
worst case duty cycle of 0.66:
1 DUTY max
L Boost t V OUT max u DUTYmax u
FSW u I RIPPLE max
(9)
375 u 0.66 u 1 0.66
L Boost t 379 PH
100000 u 2.21 (10)
The actual value of the inductor chosen is 380 µH. The required saturation current for the boost inductor is
calculated using Equation 11 for the minimum input voltage and short time maximum overload conditions.
§ POUT max · § 'ripple ·
I L max ¨¨ 2 u ¸¸ u ¨ 1 11.3 A
© VINrms min ¹ © 2 ¸¹ (11)
2.4.1.5 Output Capacitor

The output capacitor, COUT, is sized to meet the holdup requirements of the converter. The holdup time
required by this design, THoldup, is 10 ms. During this time, the minimum voltage that the PFC output can
reach at full load is designed to be VOUT(min) = 250 V. Assuming this condition occurred at right at PFC burst
off time, when the PFC voltage dropped to VOUTburst(min) = 310 V.
THoldup
C OUT t 2 u POUT no min al u 2 2
V OUTburst min
VOUT min (12)
2 u 340 u 10 ms
C OUT t 175 PF
3102 2502 (13)
2.4.1.6 MOSFET Currents and Selection

The drain to source RMS current, IDSrms through PFC MOSFET is calculated as
POUT no min al 16 u VINrms min u 2

I DSrms u 2
2 u VINrms min 3 u S u V OUT max
(14)
340 § 16 u 127 ·
I DSrms u 2 ¨ ¸ 3.18 A
127 © 3S u 370 ¹ (15)
At 330-W output and a minimum input voltage of 90 V AC, the choice of the MOSFET is based on
obtaining reduced conduction loss in the back-to back MOSFET. As a result a 60-mΩ RDS(on), part
IPP60R060P7 is selected in this application.
2.4.1.7 Boost Diode

The output diode should have a blocking voltage that exceeds the output overvoltage of the converter and
average current same as IOUT(max). In CCM PFC topology, the boost diode undergoes hard turn-off and
hence suffers from reverse recovery losses.
One way of reducing the reverse recovery loss is by using a silicon-carbide diode. In this design
c3d04060a is used. The average current through each SiC diode is equal to the IOUT(max).
2.4.1.8 Floating Current Sense Circuit

In this design, since the inductor current cannot be measured through a sense resistor referenced to
ground, a floating current sense arrangement based on hall sensor is used. Since this is a bridgeless PFC
design, it can be seen that the inductor current will follow the input AC voltage in sin, that is, will have both
+Ve and –Ve component, based on the input AC half-cycle. As a result an additional precision full-wave
rectifier current sense circuit is used to convert the inductor current into a form usable by the UCC28180.
Figure 6 shows the circuit.
Figure 6. PFC Floating Current Sense

C77 100pF
R54
R89 R88 R90
49.9k
49.9k 49.9k 49.9k
2
U19B U19D
Iout_hall R91 6 D5 U19C Iout_ZERO R57 13
7 3 BAT54S-7-F 9 14 ISENSE
49.9k B 49.9k D
5 8 R59 49.9k 12
C
10
Iout_ZERO TLV4170IPWR TLV4170IPWR
1 TLV4170IPWR R58
R92
49.9k
49.9k
U28
1 TAB1 PGND
P 10 PFC_CS2
AUX_5V 2 TEST1
PGND
AUX_5V
3 VDD
C87 AUX_5V
4 TEST2
16V Iout_ZERO C62
1uF 0.1uF
5 VSS
R62
Iout_hall 6 49.9k U19A
VOUT U19E
PGND 2 C81 PGND
7 1 0.1uF
TEST3 A 4 11
3 V+ V-
8 TAB2 N 9 PFC_CS1
TLV4170IPWR TLV4170IPWR
AUX_-2.5V
CQ-3300 R79
PGND 49.9k
PGND
2.4.2 LLC Converter Stage Design

Increased demands for high-power-density power supplies have resulted in the increase in switching
frequency of the converters designed. While component sizes tend to decrease with an increase in the
switching frequency, device switching losses (which are proportional to frequency) have significantly
increased contributing to resulting in significant efficiency loss. Resonant converters use soft-switching
techniques to alleviate switching loss problems and attain high efficiencies. Further, soft-switching helps
attain low losses during light load conditions, very low device stress and reduced EMI.
The LLC resonant converter is based on the series resonant converter (SRC). By utilizing the transformer
magnetizing inductor, zero-voltage switching can be achieved over a wide range of input voltage and load.
As a result of multiple resonances, zero-voltage switching can be maintained even when the switching
frequency is higher or lower than the resonant frequency.
In this design, the LLC converter operates at a high nominal switching frequency of around 140 kHz. This
allows to minimize the dimension of the LLC transformer to meet the low profile requirements. The
converter achieves the best efficiency when operated close to its resonant frequency at a nominal input
voltage. As the switching frequency is lowered, the voltage gain is significantly increased. This allows the
converter to maintain regulation when the input voltage falls low. These features make the converter
ideally suited to operate from the output of a high-voltage boost PFC pre-regulator, allowing it to hold up
through brief periods of AC line-voltage dropout.
With its hybrid hysteretic control and ZCS avoidance feature, the UCC256301 LLC controller enables safe
operation of the LLC power stage while minimizing the dimension of the output capacitors. In addition, the
controller delivers complete system protection functions including overcurrent, undervoltage lockout
(UVLO), and overvoltage protection (OVP).
Table 3. LLC Stage Specifications

SYMBOL PARAMETER MIN TYP MAX UNIT
INPUT
VINDC Input voltage 260 350–380 410 VDC
OUTPUT
VOUT Output voltage 19.5 VDC
POUT Max output power 330 W
fswnom Nominal switching frequency 130 kHz
Line regulation 1 %
Load regulation 1 %
η Targeted efficiency 0.97
2.4.3 Design Approach for Wider Input DC Voltage Isolated LLC Converter
The DC/DC stage in a consumer AC/DC converter needs to have high power density and compact form
factor. In this design, the LLC converter is designed to operate from 320 V DC to 390-V DC steady-state
input voltage conditions.
The transformer turns ratio is determined using Equation 16:
§ V DCIN NOM ·
¨ ¸
n Mg u ¨ 2 ¸ 9.1
¨ VO ¸
¨ ¸
© ¹ (16)
2.4.4 Determine Mg_max

Determine the maximum gain required in the LLC tank Mg_max with the following equations:
§ ·
¨ VO ¸
M g _ max nu¨ ¸
¨ V DCIN _ min ¸
¨ ¸
© 2 ¹ (17)
§ ·
¨ 19.6 V ¸
M g _ max 9.1 u ¨ ¸ 1.426
¨ 250 V ¸
© 2 ¹ (18)
The dimensioned Mg_max is increased to 1.1 times the required value to handle component tolerances:
M g _ max 1.1 u 1.426 | 1.6 (19)
2.4.5 Determine Equivalent Load Resistance (Re) of Resonant Network

The equivalent load resistance at nominal and peak load under nominal output voltage and peak output
voltage are derived in this section.
8 u n 2 § VO nom ·
Re u¨ ¸
S2 ¨ IO ¸
© nom ¹ (20)
8 u 9.1 2
§ 19.6 ·
Re u¨ ¸ 77.6 :
S 2
© 17 ¹ (21)
2.4.6 Select Resonant Tank Components

The second resonance point for the LLC converter is set at close to 120-kHz. By choosing a value of Lr =
28 µH and Cr = 66 nF, calculate the value of the resonant frequency as:
1
Fr 120 kHz
2uSu Lr u Cr (22)
The Lm/Lr ratio is chosen as 7.5 as to reduce the magnetizing current in the LLC transformer. A split
magnetic approach of having separate core for the resonant inductance is used. The LLC transformer is
realized on PQ3220 core set and the resonant inductance is realized on a PQ2016 core set.
2.4.7 Determine the Primary-Side Currents

The primary-side RMS load current (Ipri) at full load is determined with the following equations:
S § IO ·
I pri u¨ ¸
2 2 ©n¹ (23)
§ 17 ·
I pri 1.11¨ ¸ 2.07 A
© 9.1 ¹ (24)
The RMS magnetizing current operating at 370-V DC input and switching frequency of 120-kHz can be
determined with Equation 25:
§2 2· § 9.1u 19.6 ·
Im ¨¨ ¸¸ u ¨ ¸ 0.96 A
© S ¹ © 2 u S u 120 kHz u 220 PH ¹ (25)
The resonant tank current Ir is determined by using Equation 26.
Ir I m2 2
I pri (26)
Ir 2.07 2 0.96 2 2.28 A (27)
2.4.8 Select the Primary Side MOSFETs

For LLC power stage working in ZVS, the turn-on losses can be neglected. The choice of the MOSFET
should be based on RDS(on) and Coss. Optimizing the Coss helps in minimizing the dead time required for
achieving ZVS, thereby minimizing duty cycle loss. In this design the IPP60R125P7 MOSFET is used.
2.4.9 Select the Secondary Side SR MOSFET

The output diode rectifier/SR MOSFET voltage rating is determined as
I sec 17 A (28)
The RMS currents through the output SR MOSFET is given with Equation 29.
I sec_ avg 8.5 A (29)

To reduces the losses in the synchronous rectifier, 2 CSD18533Q5A are used in parallel. Coupled with the
synchronous rectifier UCC24624 which maximizes the channel conduction period of the SR MOSFET, the
conduction losses in the LLC output stage can be brought down significantly.
2.4.10 Soft Start—UCC256301

The UCC256301 is configured to provide a maximum 60-ms soft-start period. During start-up the soft-start
capacitor charges using the internal 25-µA current source. The UCC256301 exits soft start when the
closed-loop control takes over or when the voltage on the soft-start capacitor reaches 7 V. Select the
value of the soft-start capacitor using Equation 30:
S
I sec_ rms I sec u 13.345 A
4 (30)
2.4.11 Current Sense Circuit (ISNS Pin)—UCC256301

The overcurrent limit OCP3 is set to trigger at 1.2 times the peak overload capability of the system.
25 PA
C SS C31 60 mS u 0.22 PF
7V (31)
Select the current sense capacitor CISNS = C39 = 150 pF, Equation 32 gives the value of RISNS = R3
OCP3 0.6
VISNSFullload 0.5 V
1.2 1.2 (32)
VISNSFullload 0.5
K ISNS 0.54 :
§ POUT max · § 1 · § 1 ·
340 u ¨
¨ ¸ u ¨¨ ¸¸ ¸
© 370 ¹
© K ¹ © V Bulk ¹ (33)
Ram, the following equations are not used but you have them in your equations file:
C ISNS C39 150 pF (34)
9
Cr 66 u 10
R ISNS R3 K ISNS u 0.54 u 12
237 :
CISNS 150 u 10 (35)
2.4.12 1 Overvoltage Protection (BW Pin)—UCC256301

The BW pin senses the output voltage through the bias winding mounted on the LLC transformer. This pin
can be used to provide an additional OVP in the system. In this reference design, the bias winding has the
same number of turns as the secondary winding. When the OVP voltage is set to 24 V, the bias winding
voltage will be 24 V. After implementing this setting, the BW pin potential divider is configured in such a
way that it reaches 4 V at 24-V output. In this design, the value of resistor R9 and R12 are chosen as 51.1
kΩ and 10 kΩ, respectively.
www.ti.com Hardware, Software, Testing Requirements, and Test Results
3 Hardware, Software, Testing Requirements, and Test Results
3.1 Required Hardware
3.1.1 Test Conditions

For input conditions:
• VIN: 85- to 265-V AC
• IIN: Current limit to 6 A
For output conditions:
• VOUT: 19.5 V
• IOUT: 0 to 17 A (nominal),
3.1.2 Equipment Needed

• Isolated AC source
• Single-phase power analyzer
• Digital oscilloscope
• • Multimeters
• Electronic load
3.1.3 Procedure
• Turn on the 12-V DC fan and set the current to obtain approximately 100 LFM airflow on the board,
roughly 300 mW.
• Connect the input terminals (connector J3) of the reference board to the AC power source
• Connect the output terminals (connector J2) to the electronic load, maintaining correct polarity
• Set the output to approximately 0 W and check the input standby power consumption.
• Observe the startup input current and output voltage waveforms.
• Slowly increase the output load and measure efficiency and other electrical parameters.
• Apply load transient using the electronic load and observe the output voltage transient waveforms.
Hardware, Software, Testing Requirements, and Test Results www.ti.com
3.2 Testing and Results
3.2.1 Test Results

This section contains the TIDA-010028 board test results.
3.2.1.1 Efficiency, Regulation, PF, and iTHD

This section shows the efficiency, power factor, regulation, and iTHD results at 90-V AC, 115-V AC and
230-V AC input. Results are tabulated in Table 4, and Figure 7 through Figure 9.
Table 4. Efficiency, iTHD and PF at Various Input Voltages

POUT (W) Eff at 90 V AC Eff at 230 V AC iTHD at 90 V AC iTHD at 230 V PF at 90 V AC PF at 230 V AC
AC
25 85.01 81.32 22.76 28.3 0.87 0.84
50 88.78 88.53 12.91 18.62 0.94 0.92
100 92.9 92.74 7.68 12.3 0.97 0.95
150 93.89 93.51 6.21 8.81 0.98 0.97
200 94.1 94.8 5.57 7.03 0.98 0.98
250 94.11 95.08 4.63 6.44 0.99 0.98
300 94.08 95.33 5.12 5.92 0.99 0.99
330 94.02 95.46 4.8 6.14 0.99 0.98
Figure 7. POUT (W) vs Efficiency(%)

96
94
92
90
Efficiency (%)
88
86
84
82
Efficiency at 90 V AC
Efficiency at 230 V AC
80
0 50 100 150 200 250 300 350
POUT (W) D001
Figure 8. POUT (W) vs iTHD(%)

30
iTHD at 90 V AC
iTHD at 230 V AC
27
24
21
iTHD (%)
18
15
12
3
0 50 100 150 200 250 300 350
POUT (W) D002
Figure 9. POUT (W) vs PF

1
0.98
0.96
0.94
PF
0.92
0.9
0.88
0.86
PF at 90 V AC
PF at 230 V AC
0.84
0 50 100 150 200 250 300 350
POUT (W) D003
3.2.1.2 PFC Start-Up Waveform

Figure 10 shows the full-load, start-up waveform. The input current reaches the steady-state value in the
first few cycles.
Figure 10. PFC Full-Load, Start-up Waveform
3.2.1.3 PFC Burst Mode Waveform

Figure 11 shows the PFC output voltage and input current during the burst mode at no-load operation and
90-V AC input voltage.
Figure 11. Burst Mode PFC Working Waveform
3.2.1.4 Load Transient Response

Figure 12 shows the load transient response of the system when the 24-V output load current step
changes from 0% to 100% with a slew rate of 1 A/µs.
Figure 12. Load Transient 0 A to 17 A
3.2.1.5 Output Voltage Ripple

Figure 13 shows the output voltage ripple at full load and 230-V AC input.
Figure 13. Output Voltage Ripple at Full Load
3.2.1.6 PFC Working Waveforms

This section shows the PFC input and switching waveforms. Figure 14 shows the input voltage and
current at 90-V AC input and the Figure 15 shows the input voltage and current at 230-V AC input.
Figure 14. 90-V AC Input Voltage and Current
Figure 15. 230-V AC Input Voltage and Current
Figure 16 shows the MOSFET Q1 drain source voltage zoomed out over an entire AC cycle. Figure 17
and Figure 18 show zoomed in turn-on and turn-off waveforms.
Figure 16. 90-V AC Input Voltage and Current Multi-Cycle
Figure 17. PFC MOSFET Turn-On
Figure 18. PFC MOSFET Turn-Off
3.2.1.7 LLC Working Waveform

Figure 19 and Figure 20 show the LLC switching waveforms at 350-V DC and 380-V DC input voltage
(PFC output voltage) conditions. The primary high-voltage MOSFET drain source voltage, gate source
voltage, resonant tank current and SR MOSFET Vgs have been captured.
Figure 19. LLC Working 350 V DC
Figure 20. LLC Working 380 V DC
3.2.1.8 Thermal Image

The Figure 21 and Section 2.4.3 show the full-load thermal image at a 90-V AC input. The thermal image
was recorded after running the board for 20 minutes. This thermal image was recorded using forced air
cooling with a 100-LFM airflow (400-mW fan power).
Figure 21. TIDA-010028 Thermal Image
Design Files www.ti.com
4 Design Files
4.1 Schematics
To download the schematics, see the design files at TIDA-010028.
4.2 Bill of Materials

To download the bill of materials (BOM), see the design files at TIDA-010028.
4.3 PCB Layout Recommendations

Refer to the UCC256301, UCC28180, and UCC24624 data sheets for detailed layout recommendations
4.3.1 Layout Prints

To download the layer plots, see the design files at TIDA-010028.
4.4 Altium Project

To download the Altium Designer® project files, see the design files at TIDA-010028.
4.5 Gerber Files

To download the Gerber files, see the design files at TIDA-010028.
4.6 Assembly Drawings

To download the assembly drawings, see the design files at TIDA-010028.
5 Software Files
To download the software files, see the design files at TIDA-010028.
6 Related Documentation
1. Texas Instruments, UCC28180 Programmable Frequency, Continuous Conduction Mode (CCM), Boost
Power Factor Correction (PFC) Controller Data Sheet
2. Texas Instruments, UCC256301 Hybrid Hysteretic Mode Wide VIN LLC Resonant Controller Enabling
Ultra-Low Standby Power Data Sheet
3. Texas Instruments, UCC24624 Dual-Channel Synchronous Rectifier Controller for LLC Resonant
Converters Data Sheet
4. Texas Instruments, CSD18533Q5A 60 V N-Channel NexFET™ Power MOSFET Data Sheet
6.1 Trademarks
E2E is a trademark of Texas Instruments.
Altium Designer is a registered trademark of Altium LLC or its affiliated companies.
All other trademarks are the property of their respective owners.
IMPORTANT NOTICE AND DISCLAIMER
TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATASHEETS), DESIGN RESOURCES (INCLUDING REFERENCE
DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS”
AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY
IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD
PARTY INTELLECTUAL PROPERTY RIGHTS.
These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate
TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable
standards, and any other safety, security, or other requirements. These resources are subject to change without notice. TI grants you
permission to use these resources only for development of an application that uses the TI products described in the resource. Other
reproduction and display of these resources is prohibited. No license is granted to any other TI intellectual property right or to any third
party intellectual property right. TI disclaims responsibility for, and you will fully indemnify TI and its representatives against, any claims,
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TI’s products are provided subject to TI’s Terms of Sale (www.ti.com/legal/termsofsale.html) or other applicable terms available either on
ti.com or provided in conjunction with such TI products. TI’s provision of these resources does not expand or otherwise alter TI’s applicable
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Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265

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TI Designs: TIDA-010028

330-W, 95.5% Efficiency and 18-W/in3 Density, Bridgeless

ASK Our E2E™ Experts

PFC_VCC UCC256301 OPTO ATL431

1.1 Key System Specifications

Table 1. Key System Specifications

2.1 Block Diagram

Figure 1. TIDA-010028 Block Diagram

PFC_VCC UCC256301 OPTO ATL431

2.2 Design Considerations

2.3 Highlighted Products

2.4 System Design Theory

2.4.1.1 Design Parameters

Table 2. PFC Stage Specifications

2.4.1.2 Bidirectional Bridgeless PFC Working

Figure 2. Bidirectional Bridgeless PFC Power Stage

85V ± 265V DRV 400V DC

Figure 3. Bidirectional Bridgeless PFC Working in +Ve Half Cycle

85V ± 265V 400V DC

Figure 4. Bidirectional Bridgeless PFC Working in -Ve Half Cycle

85V ± 265V 400V DC

Figure 5. Key Switching Waveforms in Bidirectional Bridgeless PFC

2.4.1.3 Current Calculations

2.4.1.4 Boost Inductor

V OUT max V INrms max u 2

2.4.1.5 Output Capacitor

2.4.1.6 MOSFET Currents and Selection

POUT no min al 16 u VINrms min u 2

2.4.1.7 Boost Diode

2.4.1.8 Floating Current Sense Circuit

Figure 6. PFC Floating Current Sense

2.4.2 LLC Converter Stage Design

Table 3. LLC Stage Specifications

2.4.4 Determine Mg_max

2.4.5 Determine Equivalent Load Resistance (Re) of Resonant Network

2.4.6 Select Resonant Tank Components

2.4.7 Determine the Primary-Side Currents

Ir 2.07 2 0.96 2 2.28 A (27)

2.4.8 Select the Primary Side MOSFETs

2.4.9 Select the Secondary Side SR MOSFET

I sec_ avg 8.5 A (29)

2.4.10 Soft Start—UCC256301

2.4.11 Current Sense Circuit (ISNS Pin)—UCC256301

2.4.12 1 Overvoltage Protection (BW Pin)—UCC256301

3 Hardware, Software, Testing Requirements, and Test Results

3.1 Required Hardware

3.1.1 Test Conditions

3.1.2 Equipment Needed

3.2 Testing and Results

3.2.1 Test Results

3.2.1.1 Efficiency, Regulation, PF, and iTHD

Table 4. Efficiency, iTHD and PF at Various Input Voltages

Figure 7. POUT (W) vs Efficiency(%)

Figure 8. POUT (W) vs iTHD(%)

Figure 9. POUT (W) vs PF

3.2.1.2 PFC Start-Up Waveform

Figure 10. PFC Full-Load, Start-up Waveform

3.2.1.3 PFC Burst Mode Waveform

Figure 11. Burst Mode PFC Working Waveform

3.2.1.4 Load Transient Response

Figure 12. Load Transient 0 A to 17 A

3.2.1.5 Output Voltage Ripple

Figure 13. Output Voltage Ripple at Full Load