ARCHITECHTURE or FUNCTIONAL BLOCK DIAGRAM OF 8085 :-

The functional block diagram or architechture of 8085 Microprocessor is very important as it

gives the complete details about a Microprocessor. Fig. shows the Block diagram of a
Microprocessor.
8085 Bus Structure:
Address Bus:
• The address bus is a group of 16 lines generally identified as A0 to A15.
• The address bus is unidirectional: bits flow in one direction-from the MPU to peripheral
devices.
• The MPU uses the address bus to perform the first function: identifying a peripheral or a
memory location.
Data Bus:
• The data bus is a group of eight lines used for data flow.
• These lines are bi-directional - data flow in both directions between the MPU and
memory and peripheral devices.
• The MPU uses the data bus to perform the second function: transferring binary
information.
• The eight data lines enable the MPU to manipulate 8-bit data ranging from 00 to FF (28
= 256 numbers).
• The largest number that can appear on the data bus is 11111111.
Control Bus:
• The control bus carries synchronization signals and providing timing signals.
• The MPU generates specific control signals for every operation it performs. These
signals are used to identify a device type with which the MPU wants to communicate.
Registers of 8085:
• The 8085 have six general-purpose registers to store 8-bit data during program
execution.
• These registers are identified as B, C, D, E, H, and L.
• They can be combined as register pairs-BC, DE, and HL-to perform some 16-bit
operations.

Accumulator (A):
• The accumulator is an 8-bit register that is part of the arithmetic/logic unit (ALU).
• This register is used to store 8-bit data and to perform arithmetic and logical operations.
• The result of an operation is stored in the accumulator.
Flags:
• The ALU includes five flip-flops that are set or reset according to the result of an
operation.
• The microprocessor uses the flags for testing the data conditions.
• They are Zero (Z), Carry (CY), Sign (S), Parity (P), and Auxiliary Carry (AC) flags. The
most commonly used flags are Sign, Zero, and Carry.
The bit position for the flags in flag register is,

1.Sign Flag (S):

After execution of any arithmetic and logical operation, if D7 of the result is 1, the sign
flag is set. Otherwise it is reset.
D7 is reserved for indicating the sign; the remaining is the magnitude of number.
If D7 is 1, the number will be viewed as negative number. If D7 is 0, the number will be
viewed as positive number.
2.Zero Flag (z):
If the result of arithmetic and logical operation is zero, then zero flag is set otherwise it is
reset.
3.Auxiliary Carry Flag (AC):
If D3 generates any carry when doing any arithmetic and logical operation, this flag is set.
Otherwise it is reset.
4.Parity Flag (P):
If the result of arithmetic and logical operation contains even number of 1's then this flag will
be set and if it is odd number of 1's it will be reset.
5.Carry Flag (CY): If any arithmetic and logical operation result any carry then carry flag is set
otherwise it is reset.
Arithmetic and Logic Unit (ALU):
• It is used to perform the arithmetic operations like addition, subtraction, multiplication,
division, increment and decrement and logical operations like AND, OR and EX-OR.
• It receives the data from accumulator and registers.
• According to the result it set or reset the flags.
Program Counter (PC):
• This 16-bit register sequencing the execution of instructions.
• It is a memory pointer. Memory locations have 16-bit addresses, and that is why this is a
16-bit register.
• The function of the program counter is to point to the memory address of the next
instruction to be executed.
• When an opcode is being fetched, the program counter is incremented by one to point to
the next memory location.
Stack Pointer (Sp):
• The stack pointer is also a 16-bit register used as a memory pointer.
• It points to a memory location in R/W memory, called the stack.
• The beginning of the stack is defined by loading a 16-bit address in the stack pointer
(register).
• Temporary Register: It is used to hold the data during the arithmetic and logical
operations.
• Instruction Register: When an instruction is fetched from the memory, it is loaded in the
instruction register.
• Instruction Decoder: It gets the instruction from the instruction register and decodes the
instruction. It identifies the instruction to be performed.

Serial I/O Control: It has two control signals named SID and SOD for serial data transmission.
Timing and Control unit:
• It has three control signals ALE, RD (Active low) and WR (Active low) and three
status signals IO/M(Active low), S0 and S1.
• ALE is used for provide control signal to synchronize the components of
microprocessor and timing for instruction to perform the operation.
• RD (Active low) and WR (Active low) are used to indicate whether the operation is
reading the data from memory or writing the data into memory respectively.
• IO/M(Active low) is used to indicate whether the operation is belongs to the memory
or peripherals.
Interrupt Control Unit:It receives hardware interrupt signals and sends an acknowledgement
for receiving the interrupt signal.

PIN DIAGRAM AND PIN DESCRIPTION OF 8085 :-

• The microprocessor is a clock-driven semiconductor device consisting of electronic logic

circuits manufactured by using either a large-scale integration (LSI) or very-large-scale
integration (VLSI) technique.
• The microprocessor is capable of performing various computing functions and making
decisions to change the sequence of program execution.
• In large computers, a CPU implemented on one or more circuit boards performs these
computing functions.
• The microprocessor is in many ways similar to the CPU, but includes the logic circuitry,
including the control unit, on one chip.
• The microprocessor can be divided into three segments for the sake clarity,
arithmetic/logic unit (ALU), register array, and control unit.
• 8085 is a 40 pin IC, DIP package. The signals from the pins can be grouped as follows
1. Power supply and clock signals
2. Address bus
3. Data bus
4. Control and status signals
5. Interrupts and externally initiated signals
6. Serial I/O ports

1. Power supply and Clock frequency signals:

• Vcc + 5 volt power supply
• Vss Ground
• X1, X2 : Crystal or R/C network or LC network connections to set the frequency of
internal clock generator.
• The frequency is internally divided by two. Since the basic operating timing frequency is
3 MHz, a 6 MHz crystal is connected externally.
• CLK (output)-Clock Output is used as the system clock for peripheral and devices
interfaced with the microprocessor.
2. Address Bus:
• A8 - A15 (output; 3-state)
• It carries the most significant 8 bits of the memory address or the 8 bits of the I/O
address;

3. Multiplexed Address / Data Bus:

• AD0 - AD7 (input/output; 3-state)
• These multiplexed set of lines used to carry the lower order 8 bit address as well as data
bus.
• During the opcode fetch operation, in the first clock cycle, the lines deliver the lower
order address A0 - A7.
• In the subsequent IO / memory, read / write clock cycle the lines are used as data bus.
The CPU may read or write out data through these lines.

Fig (a) - Pin Diagram of 8085 & Fig(b) - logical schematic of Pin diagram.
4. Control and Status signals:
• ALE (output) - Address Latch Enable.
• This signal helps to capture the lower order address presented on the multiplexed
address / data bus.
• RD (output 3-state, active low) - Read memory or IO device.
• This indicates that the selected memory location or I/O device is to be read and that the
data bus is ready for accepting data from the memory or I/O device.
• WR (output 3-state, active low) - Write memory or IO device.
• This indicates that the data on the data bus is to be written into the selected memory
location or I/O device.
• IO/M (output) - Select memory or an IO device.
• This status signal indicates that the read / write operation relates to whether the memory
or I/O device.
• It goes high to indicate an I/O operation.
• It goes low for memory operations.

5. Status Signals:
• It is used to know the type of current operation of the microprocessor.

6. Interrupts and Externally initiated operations:

• They are the signals initiated by an external device to request the microprocessor to do
a particular task or work.
• There are five hardware interrupts called,

• On receipt of an interrupt, the microprocessor acknowledges the interrupt by the active

low INTA (Interrupt Acknowledge) signal.
Reset In (input, active low)
• This signal is used to reset the microprocessor.
• The program counter inside the microprocessor is set to zero.
• The buses are tri-stated.
Reset Out (Output)
• It indicates CPU is being reset.
• Used to reset all the connected devices when the microprocessor is reset.
7. Direct Memory Access (DMA):
Tri state devices:

• 3 output states are high & low states and additionally a high impedance state.
• When enable E is high the gate is enabled and the output Q can be 1 or 0 (if A is 0, Q is
1, otherwise Q is 0). However, when E is low the gate is disabled and the output Q
enters into a high impedance state.

Fig (a) - Pin Diagram of 8085 & Fig(b) - logical schematic of Pin diagram.
 • For both high and low states, the output Q draws a current from the input of the OR gate.
• When E is low, Q enters a high impedance state; high impedance means it is electrically
isolated from the OR gate's input, though it is physically connected. Therefore, it does
not draw any current from the OR gate's input.
• When 2 or more devices are connected to a common bus, to prevent the devices from
interfering with each other, the tristate gates are used to disconnect all devices except
the one that is communicating at a given instant.
• The CPU controls the data transfer operation between memory and I/O device. Direct
Memory Access operation is used for large volume data transfer between memory and
an I/O device directly.
• The CPU is disabled by tri-stating its buses and the transfer is effected directly by
external control circuits.
• HOLD signal is generated by the DMA controller circuit. On receipt of this signal, the
microprocessor acknowledges the request by sending out HLDA signal and leaves out
the control of the buses. After the HLDA signal the DMA controller starts the direct
transfer of data.

READY (input)

• Memory and I/O devices will have slower response compared to microprocessors.
• Before completing the present job such a slow peripheral may not be able to handle
further data or control signal from CPU.
• The processor sets the READY signal after completing the present job to access the
data.
• The microprocessor enters into WAIT state while the READY pin is disabled.

8. Single Bit Serial I/O ports:

• SID (input) - Serial input data line

• SOD (output) - Serial output data line
These signals are used for serial communication.
MEMORY INTERFACING WITH 8085
The memory is made up of semiconductor material used to store the programs and data. Three
types of memory is,
• Process memory
• Primary or main memory
• Secondary memory

TYPICAL EPROM AND STATIC RAM:

• A typical semiconductor memory IC will have n address pins, m data pins (or output
pins).
• Having two power supply pins (one for connecting required supply voltage (V and the
other for connecting ground).
• The control signals needed for static RAM are chip select (chip enable), read control
(output enable) and write control (write enable).
The control signals needed for read operation in EPROM are chip select (chip enable) and read
control (output enable).
 Table - Number of Address Pins and Data Pins in Memory ICs

DECODER:
It is used to select the memory chip of processor during the execution of a program. No of IC's
used for decoder is,
• 2-4 decoder (74LS139)
• 3-8 decoder (74LS138)

Fig - Block diagram and Truth table of 2-4 decoder

 Fig - Block diagram and Truth table of 3-8 decoder

EXAMPLE-1

Consider a system in which the full memory space 64kb is utilized for EPROM memory.
Interface the EPROM with 8085 processor.

• The memory capacity is 64 Kbytes. i.e

• 2^n = 64 x 1000 bytes where n = address lines.
• So, n = 16.
• In this system the entire 16 address lines of the processor are connected to address
input pins of memory IC in order to address the internal locations of memory.
• The chip select (CS) pin of EPROM is permanently tied to logic low (i.e., tied to ground).
• Since the processor is connected to EPROM, the active low RD pin is connected to
active low output enable pin of EPROM.
• The range of address for EPROM is 0000H to FFFFH.
EXAMPLE-2

Consider a system in which the available 64kb memory space is equally divided between
EPROM and RAM. Interface the EPROM and RAM with 8085 processor.

• Implement 32kb memory capacity of EPROM using single IC 27256.

• 32kb RAM capacity is implemented using single IC 62256.
• The 32kb memory requires 15 address lines and so the address lines A0 - A14 of the
processor are connected to 15 address pins of both EPROM and RAM.
• The unused address line A15 is used as to chip select. If A15 is 1, it select RAM and If
A15 is 0, it select EPROM.
• Inverter is used for selecting the memory.
• The memory used is both Ram and EPROM, so the low RD and WR pins of processor
are connected to low WE and OE pins of memory respectively.
• The address range of EPROM will be 0000H to 7FFFH and that of RAM will be 7FFFH
to FFFFH.
 Fig - Interfacing 32Kb EPROM and 32Kb RAM with 8085
EXAMPLE-3

Consider a system in which 32kb memory space is implemented using four numbers of 8kb
memory. Interface the EPROM and RAM with 8085 processor.
• The total memory capacity is 32Kb. So, let two number of 8kb n memory be EPROM and
the remaining two numbers be RAM.
• Each 8kb memory requires 13 address lines and so the address lines A0- A12 of the
processor are connected to 13 address pins of all the memory.
• The address lines and A13 - A14 can be decoded using a 2-to-4 decoder to generate
four chip select signals.
• These four chip select signals can be used to select one of the four memory IC at any
one time.
• The address line A15 is used as enable for decoder.
• The simplified schematic memory organization is shown.

Fig - Interfacing 16Kb EPROM and 16Kb RAM with 8085

 • The address allotted to each memory IC is shown in following table.

EXAMPLE-4

Consider a system in which the 64kb memory space is implemented using eight numbers of 8kb
memory. Interface the EPROM and RAM with 8085 processor.
• The total memory capacity is 64Kb. So, let 4 numbers of 8Kb EPROM and 4 numbers of
8Kb RAM.
• Each 8kb memory requires 13 address lines. So the address line A0 - A12 of the
processor are connected to 13address pins of all the memory lCs.
• The address lines A13, A14 and A]5 are decoded using a 3-to-8 coder to generate eight
chip select signals. These eight chip select signals can be used to select one of the eight
memories at any one time.
• The memory interfacing is shown in following figure.
 Fig - Interfacing 4 no. 8Kb EPROM and 4 no. 8Kb RAM with 8085

• The address allocation for Interfacing 4 no. 8Kb EPROM and 4 no. 8Kb RAM with 8085
Is,
 I/O INTERFACING WITH 8085

I/O STRUCTURE OF A TYPICAL MICROCOMPUTER:

There are three major types of data transfer between the microcomputer and art I/O device.
They are,
• Programmed I/O : In programmed I/O the data transfer is accomplished through an I/O
port and controlled by software.
• Interrupt driven I/O : In interrupt driven I/O, the I/O device will interrupt the processor,
and initiate data transfer.
• Direct memory access (DMA) : In DMA, the data transfer between memory and I/O can
be performed by bypassing the microprocessor.

INTERFACING I/O AND PERIPHERAL DEVICES:

1. For data transfer from input device to processor the following operations are performed.
• The input device will load the data to the port.
• When the port receives a data, it sends message to the processor to read the data.
• The processor will read the data from the port.
• After a data have been read by the processor the input device will load the next data into
the port.
2. For data transfer from processor to output device the following operations are performed.
• The processor will load the data to the port.
• The port will send a message to the output device to read the data.
• The output device will read the data from the port.
• After the data have been read by the output device the processor can load the next data
to the port.
• The various INTEL 110 port devices are 8212, 8155/8156, 8255, 8355 and 8755.
• 8212
• The 8212 is a 24 pin IC.
• It consists of eight number of D-type latches.
• It has 8-input lines DI1 to DI8 and 8-output lines DO1 to DO8
• The 8212 can be used as an input or output device
 • It has two selecting device DS1 (low) and DS2.
If,

8255:
• It has 3 numbers of 8-bit parallel I/O ports (port A, B and C).
• Port-A can be programmed in mode-0 mode-1 or mode-2 as input or output port.
• Port-B can be programmed in mode-1 and mode-2 as 1/Oport.
• When ports A and B are in mode-0, the port-C can be used as I/O port.
• One logic low chip select (CS) pin.
• It requires four internal addresses
There are two types for interfacing I/O devices:
• Memory mapped I/O device.
• Standard I/O mapped I/O device or peripheral mapped I/O device.
Example 1:

A system requires 16kb EPROM and 16kb RAM. Also the system has 2 numbers of 8255, one
number of 8279, one number of 8251 and one number of 8254. (8255 - Programmable
peripheral interface; 8279-Keyboard/display controller, 8251 - USART and 8254 - Timer). Draw
the Interface diagram. Allocate addresses to all the devices. The peripheral IC should be I/O
mapped.

• The I/O devices in the system should be mapped by standard I/O mapping. Hence
separate decoders can be used to generate chip select signals for memory IC and
peripheral IC's.
• For 16kb EPROM, we can provide 2 numbers of 2764(8k x 8) EPROM.
• For 16kb RAM we can provide 2 numbers of 6264 (8k x 8) RAM.
• The 8kb memories require 13 address lines. Hence the address lines A0 - A12 are used
for selecting the memory locations.
• The unused address lines A13, A14 and A15 are used as input to decoder 74LS138 (3-
to-8-deeoder) of memory IC. The logic low enables of this decoder are tied to IO/ M(low)
of 8085, so that this decoder is enabled for memory read/write operation. The other
enable pins of decoder are tied to appropriate logic levels permanently. The 4-outputs of
the decoder are used to select memory lCs and the remaining 4 are kept for future
expansion.
• The EPROM is mapped in the beginning of memory space from 0000H to 3FFF.
• The RAM is mapped at the end of memory space from C000 to FFFFH.
• There are five peripheral IC's to be interfaced to the system. The chip-select signals for
these IC's are given through another 3-to-8 decoder 74LS138 (I/O decoder). The input to
this decoder is A11, A12 and A13
• The address lines A13, A14 and A15 are logically ORed and applied to low enable of I/O
decoder.
• The logic high enable of I/O decoder is tied to IO / M(low) signal of 8085, so that this
decoder is enabled for I/O read/write operation.
Fig - Memory and I/O Port Interfacing with 8085
• The 16 bit address for the memory and 8255 devices are,
Example 2:

A system requires 16kb EPROM and 16kb RAM. Also the system has 2 numbers of 8255, one
number of 8279, one number of 8251 and one number of 8254. (8255 - Programmable
peripheral interface; 8279-Keyboard/display controller, 8251 - USART and 8254 - Timer). Draw
the Interface diagram. Allocate addresses to all the devices. The peripheral IC should be I/O
mapped.

• The I/O devices in the system should be mapped by standard I/O mapping. Hence
separate decoders can be used to generate chip select signals for memory IC and
peripheral IC's.
• For 16kb EPROM, we can provide 2 numbers of 2764(8k x 8) EPROM.
• For 16kb RAM we can provide 2 numbers of 6264 (8k x 8) RAM.
• The 8kb memories require 13 address lines. Hence the address lines A0 - A12 are used
for selecting the memory locations.
• The unused address lines A13, A14 and A15 are used as input to decoder 74LS138 (3-
to-8-deeoder) of memory IC. The logic low enables of this decoder are tied to IO/ M(low)
of 8085, so that this decoder is enabled for memory read/write operation. The other
enable pins of decoder are tied to appropriate logic levels permanently. The 4-outputs of
the decoder are used to select memory lCs and the remaining 4 are kept for future
expansion.
• The EPROM is mapped in the beginning of memory space from 0000H to 3FFF.
• The RAM is mapped at the end of memory space from C000 to FFFFH.
• There are five peripheral IC's to be interfaced to the system. The chip-select signals for
these IC's are given through another 3-to-8 decoder 74LS138 (I/O decoder). The input to
this decoder is A11, A12 and A13
• The address lines A13, A14 and A15 are logically ORed and applied to low enable of I/O
decoder.
• The logic high enable of I/O decoder is tied to IO / M(low) signal of 8085, so that this
decoder is enabled for I/O read/write operation.
Fig - Memory and I/O Port Interfacing with 8085
• The 16 bit address for the memory and IO devices are,
Example 3:

A system requires 8kb EPROM and 8kb RAM. Also the system has 2 numbers of 8155. Draw
the Interface diagram. Allocate addresses to all the devices. The peripheral IC should be I/O
mapped.
• The IC 2764 (8k x 8) is selected for EPROM memory and IC 6264 (8k x 8) is selected for
RAM memory. Both the memory IC has time compatibility with 8085 processor.
• The 8kb memory requires 13 address lines. Hence the address lines A0 - A12 are used
to select memory locations.
• The RAM locations of 8155 are selected by address lines A0 to A7.
• 3-to-8 decoder, 74LS138 is used for generating chip select signals by decoding the
address lines A13, A14 and A15.
• Eight bit addresses are allotted to ports of 8l55 and sixteen bit addresses are allotted to
RAM memory locations of 8155.

Fig - Memory and I/O Port Interfacing with 8085

• The 16 bit address for the memory and IO devices are,

 TIMING DIAGRAM

Timing Diagram is a graphical representation. It represents the execution time taken by each
instruction in a graphical format. The execution time is represented in T-states.

Instruction Cycle:
The time required to execute an instruction is called instruction cycle.
Machine Cycle:
The time required to access the memory or input/output devices is called machine cycle.
T-State:
• The machine cycle and instruction cycle takes multiple clock periods.
• A portion of an operation carried out in one system clock period is called as T-state.

MACHINE CYCLES OF 8085:

The 8085 microprocessor has 5 (seven) basic machine cycles. They are

1. Opcode fetch cycle (4T)

2. Memory read cycle (3 T)
3. Memory write cycle (3 T)
4. I/O read cycle (3 T)
5. I/O write cycle (3 T)

• Each instruction of the 8085 processor consists of one to five machine cycles, i.e., when
the 8085 processor executes an instruction, it will execute some of the machine cycles in
a specific order.

• The processor takes a definite time to execute the machine cycles. The time taken by
the processor to execute a machine cycle is expressed in T-states.

• One T-state is equal to the time period of the internal clock signal of the processor.

• The T-state starts at the falling edge of a clock.

Opcode fetch machine cycle of 8085 :

• Each instruction of the processor has one byte opcode.

• The opcodes are stored in memory. So, the processor executes the opcode fetch
machine cycle to fetch the opcode from memory.
• Hence, every instruction starts with opcode fetch machine cycle.
• The time taken by the processor to execute the opcode fetch cycle is 4T.
• In this time, the first, 3 T-states are used for fetching the opcode from memory and the
remaining T-states are used for internal operations by the processor.

Fig - Timing Diagram for Opcode Fetch Machine Cycle

Memory Read Machine Cycle of 8085:

• The memory read machine cycle is executed by the processor to read a data byte from
memory.
• The processor takes 3T states to execute this cycle.
• The instructions which have more than one byte word size will use the machine cycle
after the opcode fetch machine cycle.

Fig - Timing Diagram for Memory Read Machine Cycle

Memory Write Machine Cycle of 8085:

• The memory write machine cycle is executed by the processor to write a data byte in a
memory location.
• The processor takes, 3T states to execute this machine cycle.
 Fig - Timing Diagram for Memory Write Machine Cycle

I/O Read Cycle of 8085:

• The I/O Read cycle is executed by the processor to read a data byte from I/O port or
from the peripheral, which is I/O, mapped in the system.
• The processor takes 3T states to execute this machine cycle.
• The IN instruction uses this machine cycle during the execution.

Fig - Timing Diagram for I/O Read Machine Cycle

I/O Write Cycle of 8085:

• The I/O write machine cycle is executed by the processor to write a data byte in the I/O
port or to a peripheral, which is I/O, mapped in the system.
• The processor takes, 3T states to execute this machine cycle.

Fig - Timing Diagram for I/O Write Machine Cycle

TIMING DIAGRAM OF 8085 INSTRUCTIONS

• The 8085 instructions consist of one to five machine cycles.

• Actually the execution of an instruction is the execution of the machine cycles of that
instruction in the predefined order.
• The timing diagram of an instruction ate obtained by drawing the timing diagrams of the
machine cycles of that instruction, one by one in the order of execution.
Timing diagram for STA 526AH.
• STA means Store Accumulator -The contents of the accumulator is stored in the
specified address(526A).
• The opcode of the STA instruction is said to be 32H. It is fetched from the memory
41FFH(see fig). - OF machine cycle
• Then the lower order memory address is read(6A). - Memory Read Machine Cycle
• Read the higher order memory address (52).- Memory Read Machine Cycle
• The combination of both the addresses are considered and the content from
accumulator is written in 526A. - Memory Write Machine Cycle
• Assume the memory address for the instruction and let the content of accumulator is
C7H. So, C7H from accumulator is now stored in 526A.
Timing diagram for IN C0H.

• Fetching the Opcode DBH from the memory 4125H.

• Read the port address C0H from 4126H.
• Read the content of port C0H and send it to the accumulator.
• Let the content of port is 5EH.
Timing diagram for INR M :

• Fetching the Opcode 34H from the memory 4105H. (OF cycle)
• Let the memory address (M) be 4250H. (MR cycle -To read Memory address and data)
• Let the content of that memory is 12H.
• Increment the memory content from 12H to 13H. (MW machine cycle)
Timing diagram for MVI B, 43H.

• Fetching the Opcode 06H from the memory 2000H. (OF machine cycle)
• Read (move) the data 43H from memory 2001H. (memory read)
 8085 INSTRUCTION SET CLASSIFICATION

The 8085 instruction set can be classified into the following five functional headings.

1. DATA TRANSFER INSTRUCTIONS:

It includes the instructions that move (copies) data between registers or between memory
locations and registers. In all data transfer operations the content of source register is not
altered. Hence the data transfer is copying operation.
Ex: (1) Mov A,B (2) MVI C,45H

2. ARITHMETIC INSTRUCTIONS:
Includes the instructions, which performs the addition, subtraction, increment or decrement
operations. The flag conditions are altered after execution of an instruction in this group.
Ex: (1) ADD A,B (2) SUI B,05H

3. LOGICAL INSTRUCTIONS:
The instructions which performs the logical operations like AND, OR, EXCLUSIVE- OR,
complement, compare and rotate instructions are grouped under this heading. The flag
conditions are altered after execution of an instruction in this group.
Ex: (1) ORA A (2) ANI B, 01H

4. BRANCHING INSTRUCTIONS:
The instructions that are used to transfer the program control from one memory location to
another memory location are grouped under this heading.
Ex: (1) CALL (2) JMP 4100

5. MACHINE CONTROL INSTRUCTIONS:

It includes the instructions related to interrupts and the instruction used to stop the program
execution.
Ex: (1) NOP (2) END
 ADDRESSING MODES OF 8085

• Every instruction of a program has to operate on a data.

• The method of specifying the data to be operated by the instruction is called Addressing.
• The 8085 has the following 5 different types of addressing.

1. Immediate Addressing
2. Direct Addressing
3. Register Addressing
4. Register Indirect Addressing
5. Implied Addressing

1. Immediate Addressing:

In immediate addressing mode, the data is specified in the instruction itself. The data will be a
part of the program instruction.
EX. MVI B, 3EH - Move the data 3EH given in the instruction to B register; LXI SP, 2700H.

2. Direct Addressing:

In direct addressing mode, the address of the data is specified in the instruction. The data will
be in memory. In this addressing mode, the program instructions and data can be stored in
different memory.
EX. LDA 1050H - Load the data available in memory location 1050H in to accumulator; SHLD
3000H

3. Register Addressing:

In register addressing mode, the instruction specifies the name of the register in which the data
is available.
EX. MOV A, B - Move the content of B register to A register; SPHL; ADD C.

4. Register Indirect Addressing:

In register indirect addressing mode, the instruction specifies the name of the register in which
the address of the data is available. Here the data will be in memory and the address will be in
the register pair.
EX. MOV A, M - The memory data addressed by H L pair is moved to A register. LDAX B.

5. Implied Addressing:

In implied addressing mode, the instruction itself specifies the data to be operated.
EX. CMA - Complement the content of accumulator; RAL
 The STACK

The stack is one of the most important things you must know when programming. Think of the
stack as a deck of cards. When you put a card on the deck, it will be the top card. Then you put
another card, then another. When you remove the cards, you remove them backwards, the last
card first and so on. The stack works the same way, you put (push) words (addresses or
register pairs) on the stack and then remove (pop) them backwards. That's called LIFO, Last In
First Out.

The 8085 uses a 16 bit register to know where the stack top is located, and that register is
called the SP (Stack Pointer). There are instructions that allow you to modify it’s contents but
you should NOT change the contents of that register if you don't know what you're doing!

PUSH & POP :

As you may have guessed, push and pop “pushes” bytes on the stack and then takes them off.
When you push something, the stack counter will decrease with 2 (the stack "grows" down, from
higher addresses to lower) and then the register pair is loaded onto the stack. When you pop,
the register pair is first lifted of the stack, and then SP increases by 2.

N.B: Push and Pop only operate on words (2 bytes ie: 16 bits).

You can push (and pop) all register pairs: BC, DE, HL and PSW (Register A and Flags). When
you pop PSW, remember that all flags may be changed. You can't push an immediate value. If
you want, you'll have to load a register pair with the value and then push it. Perhaps it's worth
noting that when you push something, the contents of the registers will still be the same; they
won't be erased or something. Also, if you push DE, you can pop it back as HL (you don't have
to pop it back to the same register where you got it from).

The stack is also updated when you CALL and RETurn from subroutines. The PC (program
counter which points at the next instruction to be executed) is pushed to the stack and the
calling address is loaded into PC. When returning, the PC is loaded with the word popped from
the top of the stack (TOS).

So, when is this useful? It's almost always used when you call subroutines. For example, you
have an often used value stored in HL. You have to call a subroutine that you know will destroy
HL (with destroy I mean that HL will be changed to another value, which you perhaps don't
know). Instead of first saving HL in a memory location and then loading it back after the
subroutine, you can push HL before calling and directly after the calling pop it back. Of course,
it's often better to use the pushes and pops inside the subroutine. All registers you know will be
changed are often pushed in the beginning of a subroutine and then popped at the end, in
reverse order! Don't forget - last in first out. If you want to only push one 8 bit register, you
still have to push it's "friend". Therefore, be aware that if you want to store away D with pushing
and popping, remember that E will also be changed back to what it was before. In those cases,
if you don't want that to happen, you should try first to change register (try to store the
information in E in another register if you can) or else you have to store it in a temporary
variable.

Before executing a program, you should keep track of your pushes and pops, since they are
responsible for 99% of all computer crashes! For example, if you push HL and then forget to
pop it back, the next RET instruction will cause a jump to HL, which can be anywhere in the
ROM/RAM and the ccomputer will crash. Note however, it’s also a way to jump to the location
stored in HL, but then you should really use the JMP instruction, to do the same thing.

Push and pop doesn't change any flags, so you can use them between a compare and jump
instructions, depending on a condition, which is often very useful.
 INTERRUPT

• Interrupt is signals send by an external device to the processor, to request the processor
to perform a particular task or work.
• Mainly in the microprocessor based system the interrupts are used for data transfer
between the peripheral and the microprocessor.
• The processor will check the interrupts always at the 2nd T-state of last machine cycle.
• If there is any interrupt it accept the interrupt and send the INTA (active low) signal to the
peripheral.
• The vectored address of particular interrupt is stored in program counter.
• The processor executes an interrupt service routine (ISR) addressed in program
counter.
• It returned to main program by RET instruction.
Types of Interrupts:
It supports two types of interrupts.
• Software
• Hardware
Software interrupts:
• The software interrupts are program instructions. These instructions are inserted at
desired locations in a program.
• The 8085 has eight software interrupts from RST 0 to RST 7. The vector address for
these interrupts can be calculated as follows.
• Interrupt number * 8 = vector address
• For RST 5,5 * 8 = 40 = 28H
• Vector address for interrupt RST 5 is 0028H
The Table shows the vector addresses of all interrupts.

Hardware Interrupts:

• An external device initiates the hardware interrupts and placing an appropriate signal at
the interrupt pin of the processor.
• If the interrupt is accepted then the processor executes an interrupt service routine.
• The 8085 has five hardware interrupts
(1) TRAP (2) RST 7.5 (3) RST 6.5 (4) RST 5.5 (5) INTR
TRAP:
• This interrupt is a non-maskable interrupt. It is unaffected by any mask or interrupt
enable.
• TRAP bas the highest priority and vectored interrupt.
• TRAP interrupt is edge and level triggered. This means hat the TRAP must go high and
remain high until it is acknowledged.
• In sudden power failure, it executes a ISR and send the data from main memory to
backup memory.
• The signal, which overrides the TRAP, is HOLD signal. (i.e., If the processor receives
HOLD and TRAP at the same time then HOLD is recognized first and then TRAP is
recognized).
• There are two ways to clear TRAP interrupt.
1.By resetting microprocessor (External signal)
2.By giving a high TRAP ACKNOWLEDGE (Internal signal)
RST 7.5:

• The RST 7.5 interrupt is a maskable interrupt.

• It has the second highest priority.
• It is edge sensitive. ie. Input goes to high and no need to maintain high state until it
recognized.
• Maskable interrupt. It is disabled by,
1.DI instruction
2.System or processor reset.
3.After reorganization of interrupt.
• Enabled by EI instruction.
RST 6.5 and 5.5:
• The RST 6.5 and RST 5.5 both are level triggered. . ie. Input goes to high and stay high
until it recognized.
• Maskable interrupt. It is disabled by,
1.DI, SIM instruction
2.System or processor reset.
3.After reorganization of interrupt.
• Enabled by EI instruction.
• The RST 6.5 has the third priority whereas RST 5.5 has the fourth priority.
INTR:
• INTR is a maskable interrupt. It is disabled by,
1.DI, SIM instruction
2.System or processor reset.
3.After reorganization of interrupt.
 • Enabled by EI instruction.
• Non- vectored interrupt. After receiving INTA (active low) signal, it has to supply the
address of ISR.
• It has lowest priority.
• It is a level sensitive interrupts. ie. Input goes to high and it is necessary to maintain
high state until it recognized.
• The following sequence of events occurs when INTR signal goes high.

1. The 8085 checks the status of INTR signal during execution of each instruction.

2. If INTR signal is high, then 8085 complete its current instruction and sends active low
interrupt acknowledge signal, if the interrupt is enabled.

3. In response to the acknowledge signal, external logic places an instruction OPCODE on the
data bus. In the case of multibyte instruction, additional interrupt acknowledge machine cycles
are generated by the 8085 to transfer the additional bytes into the microprocessor.

4. On receiving the instruction, the 8085 save the address of next instruction on stack and
execute received instruction.

SIM and RIM for interrupts:

SIM:

• The 8085 provide additional masking facility for RST 7.5, RST 6.5 and RST 5.5 using
SIM instruction.
• The status of these interrupts can be read by executing RIM instruction.
• The masking or unmasking of RST 7.5, RST 6.5 and RST 5.5 interrupts can be
performed by moving an 8-bit data to accumulator and then executing SIM instruction.
• The format of the 8-bit data is shown below.
RIM :

• The status of pending interrupts can be read from accumulator after executing RIM
instruction.
• When RIM instruction is executed an 8-bit data is loaded in accumulator, which can be
interpreted as shown in fig.
 PROGRAMMABLE PERIPHERAL INTERFACE - INTEL 8255

Pins, Signals and internal block diagram of 8255:

• It has 40 pins and requires a single +5V supply.

PIN DESCRIPTION - INTEL 8255 :

Block diagram of 8255:
• The internal block diagram of 8255 is shown in fig:

• The INTEL 8255 is a device used to parallel data transfer between processor and slow
peripheral devices like ADC, DAC, keyboard, 7-segment display, LCD, etc.
 • The 8255 has three ports: Port-A, Port-B and Port-C.

• Port-A can be programmed to work in any one of the three operating modes mode-0,
mode-1 and mode-2 as input or output port.

• Port-B can be programmed to work either in mode-0 or mode-1 as input or output port.
• Port-C (8-pins) has different assignments depending on the mode of port-A and port-B.

• If port-A and B are programmed in mode-0, then the port-C can perform any one of the
following functions.

• As 8-bit parallel port in mode-0 for input or output.

• As two numbers of 4-bit parallel ports in mode-0 for input or output.

• The individual pins of port-C can be set or reset for various control applications.

• If port-A is programmed in mode- 1/mode-2 and port-B is programmed in mode-1 then

some of the pins of port-C are used for handshake signals and the remaining pins can
be used as input/ output lines or individually set/reset for control applications.

• The read/write control logic requires six control signals. These signals are given below.
1. RD (low): This control signal enables the read operation. When this signal is low, the
microprocessor reads data from a selected I/O port of the 8255A.
2. WR (low): This control signal enables the write operation. When this signal goes low,
the microprocessor writes into a selected I/O port or the control register.
3. RESET: This is an active high signal. It clears the control register and set all ports in
the input mode.
4. CS (low), A0 and A1: These are device select signals. They are,

Interfacing of 8255 with 8085 processor:

• A simple schematic for interfacing the 8255 with 8085 processor is shown in fig.
• The 8255 can be either memory mapped or I/O mapped in the system. In the schematic
shown in above is I/O mapped in the system.

• Using a 3-to-8 decoder generates the chip select signals for I/O mapped devices.

• The address lines A4, A5 and A6 are decoded to generate eight chip select signals
(IOCS-0 to IOCS-7) and in this, the chip select IOCS- 1 is used to select 8255.

• The address line A7 and the control signal IO/M (low) are used as enable for the
decoder.

• The address line A0 of 8085 is connected to A0 of 8255 and A1 of 8085 is connected to

A1 of 8255 to provide the internal addresses.

• The data lines D0-D7 are connected to D0-D7 of the processor to achieve parallel data
transfer.

• The I/O addresses allotted to the internal devices of 8255 are listed in table.
 PROGRAMMABLE DMA CONTROLLER - INTEL 8257

It is a device to transfer the data directly between IO device and memory without through the
CPU. So it performs a high-speed data transfer between memory and I/O device.
The features of 8257 is,
• The 8257 has four channels and so it can be used to provide DMA to four I/O devices
• Each channel can be independently programmable to transfer up to 64kb of data by
DMA.
• Each channel can be independently perform read transfer, write transfer and verify
transfer.
• It is a 40 pin IC and the pin diagram is,
Functional Block Diagram of 8257 :-

• The functional blocks of 8257 are data bus buffer, read/write logic, control logic, priority
resolver and four numbers of DMA channels.

The functional block diagram of 8257 is shown in fig.

OPERATING MODES OF INTEL 8257 :-
• Each channel of 8257 Block diagram has two programmable 16-bit registers named as
address register and count register.
• Address register is used to store the starting address of memory location for DMA data
transfer.
• The address in the address register is automatically incremented after every
read/write/verify transfer.
• The count register is used to count the number of byte or word transferred by DMA. The
format of count register is,
• 14-bits B0-B13 is used to count value and a 2-bits is used for indicate the type of DMA
transfer (Read/Write/Veri1 transfer).
• In read transfer the data is transferred from memory to I/O device.
• In write transfer the data is transferred from I/O device to memory.
• Verification operations generate the DMA addresses without generating the DMA
memory and I/O control signals.
• The 8257 has two eight bit registers called mode set register and status register. The
format of mode set register is,

• The use of mode set register is,

1. Enable/disable a channel.

2. Fixed/rotating priority

3. Stop DMA on terminal count.

4.Extended/normal write time.

5. Auto reloading of channel-2.

• The bits B0, B1, B2, and B3 of mode set register are used to enable/disable channel -0,
1, 2 and 3 respectively. A one in these bit position will enable a particular channel and a
zero will disable it.
• If the bit B4 is set to one, then the channels will have rotating priority and if it zero then
the channels wilt have fixed priority.
1. In rotating priority after servicing a channel its priority is made as lowest.
2. In fixed priority the channel-0 has highest priority and channel-2 has lowest priority.
• If the bit B5 is set to one, then the timing of low write signals (MEMW and IOW) will be
extended.
• If the bit B6 is set to one then the DMA operation is stopped at the terminal count.
• The bit B7 is used to select the auto load feature for DMA channel-2.
• When bit B7 is set to one, then the content of channel-3 count and address registers are
loaded in channel-2 count and address registers respectively whenever the channel-2
reaches terminal count. When this mode is activated the number of channels available
for DMA reduces from four to three.
• The format of status register of 8257 is shown in fig.

• The bit B0, B1, B2, and B3 of status register indicates the terminal count status of
channel-0, 1,2 and 3 respectively. A one in these bit positions indicates that the
particular channel has reached terminal count.
• These status bits are cleared after a read operation by microprocessor.
• The bit B4 of status register is called update flag and a one in this bit position indicates
that the channel-2 register has been reloaded from channel-3 registers in the auto load
mode of operation.
• The internal addresses of the registers of 8257 are listed in table.
 INTERFACING OF DMA 8257 WITH 8085 :-

• A simple schematic for interfacing the 8257 with 8085 processor is shown.
• The 8257 can be either memory mapped or I/O mapped in the system.
• In the schematic shown in figure is I/O mapped in the system.
• Using a 3-to-8 decoder generates the chip select signals for I/O mapped devices.
• The address lines A4, A5 and A6 are decoded to generate eight chip select signals
(IOCS-0 to IOCS-7) and in this the chip select signal IOCS-6 is used to select 8257.
• The address line A7 and the control signal IO/M (low) are used as enable for decoder.
• The D0-D7 lines of 8257 are connected to data bus lines D0-D7 for data transfer with
processor during programming mode.
• These lines (D0-D7) are also used by 8257 to supply the memory address A8-A15
during the DMA mode.
• The 8257 also supply two control signals ADSTB and AEN to latch the address supplied
by it during DMA mode on external latches.
• Two 8-bit latches are provided to hold the 16-bit memory address during DMA mode.
During DMA mode, the AEN signal is also used to disable the buffers and latches used
for address, data and control signals of the processor.
• The 8257 provide separate read and write control signals for memory and I/O devices
during DMA.
• Therefore the RD (low), WR (low) and IO/M (low) of the 8085 processor are decoded by
a suitable logic circuit to generate separate read and write control signals f memory and
I/O devices.
• The output clock of 8085 processor should be inverted and supplied to 8257 clock input
for proper operation.
• The HRQ output of 8257 is connected to HOLD input of 8085 in order to make a HOLD
request to the processor.
• The HLDA output of 8085 is connected to HLDA input of 8257, in order to receive the
acknowledge signal from the processor once the HOLD request is accepted.
• The RESET OUT of 8085 processor is connected to RESET of 8257.
The I/O addresses of the internal registers of 8257 are listed in table: