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ELECTRONIC CIRCUITS
The P- Type semiconductor has more holes and less electrons. The N-type semiconductor has
more electrons and less holes. Therefore at the junction, the electrons in the N-side have tendency to
move towards the P-side. Similarly the holes on the P-side have tendency to move towards the N-side.
According to that, the electrons and holes recombine with each other, to form a region at the junction. It is
called “Depletion Region”. These two charges, on either sides, make a potential across the depletion
region called “barrier potential”.
If the applied potential is greater than barrier potential, the majority carriers on both regions move
towards the junction. It makes current flow through the junction.
The VI characteristics of a PN junction diode under forward bias condition is shown in fig.
(ii)Reverse biasing
In reverse biasing, the positive terminal of the battery is connected to the N-type and the negative
terminal of the battery is connected to the P-type materials of the diode, shown in fig.
Under reverse bias condition, the majority carriers with P and N regions are moved towards the
battery respectively. The holes in P-type and the electrons in N type regions move to the negative and
positive terminals of the battery respectively. Hence the width of the depletion region is increased.
Fig PN junction under reverse bias
When the applied voltage is slowly increased, the minority carriers(electrons) in P-region and the
minority carriers(holes) in N-region makes a small amount of current flow through the junction. This
current is called reverse saturation current shown in fig
In forward characteristics, it is seen initially forward current is small as long as the bias voltage is
less than the barrier potential. At a certain voltage close to barrier potential, current increases rapidly. The
voltage at which diode current starts increasing rapidly is called as cut in voltage. It is denoted by Vγ.
Below this voltage, current is less than 1% of maximum rated value of diode current. The cut in voltage
for germanium is about 0.3V while for silicon it is 0.7V.
It is important to note that the breakdown voltage is much higher and practically diodes are not
operated in the breakdown condition. The voltage at which breakdown occurs is called reverse
breakdown voltage denoted as VBR.
The complete Vi characteristics of a typical Ge and Si diodes are shown in fig 4.1.1.,As
mentioned earlier, the barrier potential for germanium (Ge) diode is about 0.3V while for silicon (Si) diode
is about 0.7V.
The reverse saturation current in a germanium diode is higher than reverse saturation current of a
silicon diode. The reverse breakdown voltage for Si diode is higher than that of the Ge diode of a
comparable rating.
Fig 4.1.1 Characteristic of typical Ge and Si diode
RECTIFIERS:
Definition: The process of a.c to d.c conversion is known as rectification .A circuit which is used for
rectification is called as rectifier.
A rectifier is a circuit which is used to convert a.c voltage into pulsating d.c voltage .It can be classified as
follows.
Rectifier
4.2.1 Definition: In half wave rectification, the rectifier conducts current only during positive half –cycles
of input a.c supply.
1 2𝜋
Idc= ∫ 𝑖𝑑𝜃
2𝜋 0
1 𝜋 1 2𝜋
= ∫ 𝑖𝑑𝜃
2𝜋 0
+ ∫ 𝑖𝑑𝜃
2𝜋 𝜋
In the above equation the current that flows through the load is zero during the period from 𝜋 𝑡𝑜 2𝜋.
1 𝜋
Idc= ∫ 𝑖𝑑𝜃
2𝜋 0
1 𝜋
= ∫ Im sin 𝜃 𝑑𝜃
2𝜋 0
Im
= [− cos 𝜃]
2𝜋
Im
= [−(cos 𝜋 − cos 0)]
2𝜋
Im
= [−(−1 − 1)]
2𝜋
Im
=
𝜋
Im
Idc =
𝜋
D.C Voltage:
ImRL
= Vm= Im RL
𝜋
Vm
Vdc =
𝜋
1 𝜋 2 1 2𝜋
= ∫ 𝑖 𝑑𝜃+ 2𝜋 ∫𝜋 𝑖 2 𝑑𝜃
2𝜋 0
1 2𝜋 2
I2rms = ∫ 𝑖 𝑑𝜃
2𝜋 0
1 𝜋
= ∫ (Im sin 𝜃)2
2𝜋 0
𝑑𝜃
Im2 𝜋 1−cos 2𝜃
=
2𝜋
∫0 [ 2
] 𝑑𝜃
Im2
= [∫ 𝑑𝜃 − ∫ cos 2𝜃 𝑑𝜃]
4𝜋
Im2 sin 2𝜃 𝜋
= [𝜃 − ]
4𝜋 2 0
Im2
= [𝜋 − 0]
4𝜋
Im2
I2rms =
4
Im
Irms =
2
Vrms = IrmsRL
ImRL
= Since Vm= Im RL
2
Vm
Vrms =
2
Im
= ( )2 RL
𝜋
Im
Pdc =( )2 RL
𝜋
Im2
= ( rf + RL)
4
Im2
Pac = ( rf + RL)
4
Rectifier Efficiency:
Pdc
%𝜂 = x 100%
Pac
Im 2
( ) RL
𝜋
= Im2
x 100%
( rf + RL)
4
I𝑚2 ×RL ×4
= × 100%
𝜋 ×I2
2
m ×(rf +RL )
4 RL
= ( )%
𝜋2 rf +RL
RL
= 40.6( )%
rf +RL
𝜂 = 40.6%
Ripple Factor:
I 2
Ripple Factor = √( rms) − 1
Idc
Im⁄ 2
= √(Im 2 ) − 1
⁄𝜋
𝜋2
=√ −1
4
= 1.21
Ripple Frequency:
The frequency of the pulsating load voltage is known as ripple frequency. It is equal to the
frequency of supply voltage in the halfwave rectifier.
f = fs
4.2.8 Advantages:
1.Simple Circuit
2.Low Cost
Output of half wave rectifier is not a constant DC voltage. From the output diagram that it’s a
pulsating dc voltage with ac ripples.
In real life applications, we need a power supply with smooth wave forms. In other words, we
desire a DC power supply with constant output voltage.
A constant output voltage from the DC power supply is very important as it directly impacts the
reliability of the electronic device we connect to the power supply.
The output of half wave rectifier smooth by using a filter (a capacitor filter or an inductor filter)
across the diode.
In some cases an resistor-capacitor coupled filter (RC) is also used. The circuit diagram below
shows a half wave rectifier with capacitor filter.
Fig 4.3.1 Half Wave Rectifier with Capacitor Filter – Circuit Diagram & Output Waveform
Definition: In full wave rectifier circuit current flows through the load in the same direction for both half-
cycles(full wave) of input a.c voltage.
In a.c supply voltage, there are two half cycle, one is positive half cycle the other is negative half
cycle.
During the positive half cycles of the input voltage, terminal A is positive and B is negative with
respect to terminal O.
The diode D1 conducts in forward bias and diode D2 conducts in reverse bias.
The current I1 flows from the terminal A to the load through diode D1.
No current flows through the diode D2.
4.4.5 Duration of Negative half cycle:
1 2𝜋
Idc= ∫ 𝑖𝑑𝜃
2𝜋 0
1 𝜋 1 2𝜋
= ∫ 𝑖𝑑𝜃
2𝜋 0
+ ∫ 𝑖𝑑𝜃
2𝜋 𝜋
1 𝜋 1 𝜋
Idc = ∫ 𝑖𝑑𝜃
2𝜋 0
+ ∫ 𝑖𝑑𝜃
2𝜋 0
1 𝜋
= × 2[ ∫0 𝑖𝑑𝜃 ]
2𝜋
1 𝜋
= ∫0 Im sin 𝜃 𝑑𝜃
𝜋
Im
= [− cos 𝜃]
𝜋
Im
= [−(cos 𝜋 − cos 0)]
𝜋
Im
= [−(−1 − 1)]
𝜋
2Im
=
𝜋
2Im
Idc =
𝜋
D.C Voltage:
2ImRL
= using Vm= Im RL
𝜋
2Vm
Vdc =
𝜋
1 𝜋 2 1 2𝜋
= ∫ 𝑖 𝑑𝜃+ 2𝜋 ∫𝜋 𝑖 2 𝑑𝜃
2𝜋 0
The variation between 0 and 𝜋 is equal to 𝜋 and 2𝜋.
1 𝜋 2 1 𝜋
I2rms = ∫ 𝑖 𝑑𝜃+ 2𝜋 ∫0 𝑖 2 𝑑𝜃
2𝜋 0
1 𝜋
= × 2 ∫0 𝑖 2 𝑑𝜃
2𝜋
1 𝜋
= ∫0 (Im sin 𝜃)2 𝑑𝜃
𝜋
Im2 𝜋 1−cos 2𝜃
=
𝜋
∫0 [ 2
] 𝑑𝜃
Im2
= [∫ 𝑑𝜃 − ∫ cos 2𝜃 𝑑𝜃]
2𝜋
Im2 sin 2𝜃
= [𝜃 − ]
2𝜋 2
Im2
= [𝜋 − 0]
2𝜋
Im2
I2rms =
2
Im
Irms =
√2
Vrms = IrmsRL
ImRL
= Vm= Im RL
2
Vm
Vrms =
√2
2Im 2
=( ) RL
𝜋
4Im2
Pdc = RL
𝜋2
Im2
= ( rf + RL)
2
Im2
Pac = ( rf + RL)
2
Rectifier Efficiency:
Pdc
% 𝜂 = x 100%
Pac
2Im 2
( ) RL
𝜋
= Im2
x 100%
( rf + RL )
2
4×I𝑚2 ×RL ×2
= × 100%
𝜋2 ×I2
m ×(rf +RL )
8 RL
= ( )%
𝜋2 rf +RL
RL
= 81.2( )%
rf +RL
If rf<<RL
𝜂 = 81.2%
Ripple Factor:
I 2
Ripple Factor= √( rms) − 1
Idc
Im 2
⁄
= √(2Im√2) − 1
⁄𝜋
𝜋
=√( )2 − 1
2√2
= 0.483
Ripple Frequency:
The frequency of the pulsating load voltage is known as ripple frequency. It is equal to the
frequency of supply voltage in the halfwave rectifier.
f = fs
4.4.8 Advantages:
1.The output voltage and transformer efficiency are higher.
2.Low ripple factor
3.High transformer Utilization factor.
4.4.9 Disadvantages:
1.Usage of additional diode and bulky transformer is needed, and hence increase in cost.
2.The peak inverse voltage of diode is high.
4.5 Full Wave Bridge Rectifier:
4.5.1 Definition:In full wave rectifier circuit current flows through the load in the same direction for both
half-cycles(full wave) of input a.c voltage.
In a.c supply voltage, there are two half cycle, one is positive half cycle the other is negative half
cycle.
During the positive cycle of the input signal terminal A is positive with respect terminal B.
This will provide a forward biasing the diodes D1 and D3 where as diodes D2 and D4 are reverse
biased.
The current flows through D1,D3 and load resistance RL.
The diodes D2 and D4 are not conducting.
During Negative half cycle of the input signal terminal B is positive with respect to terminal A.
This will provide a forward biasing the diodes D2 and D4 where as diodes D1 and D3 are reverse
biased.
The current flows through D2, D4 and load resistance RL.
The diodes D1 and D3 are not conducting.
During both half cycles, the current flows through the load resistor R L in same direction.
The analysis of the bridge rectifier is same as for the full wave with centre transformer rectifier
circuit.
The PIV of this circuit is equal to the maximum value of the supply voltage i.e, Vm.
TUF=81.1%
Note: PIV is equal to Vm.
1.This circuit is suitable for high voltage applications because PIV is less ie equal to Vm.
2.Core saturation does not take place.
3. RMS current Im Im Im
2 √2 √2
4. PIV Vm 2Vm Vm
1. DC motor drives.
2. Welding power supplies.
3. Uninterruptible power supplies (UPS).
4. Industrial systems that require dc voltage.
A transistor in which two layer of P type semiconductor are separated by thin layer of N type
semiconductor is known as PNP transistor it is shown in fig.4.7.2
The transistor has three terminals, namely Emitter Base and collector.
1.Emitter: The region of a transistor that supplies charge carriers (in case NPN transistor
electrons or in case of PNP transistor holes) is called the emitter.
The emitter is always forward biased with respect to base so that it can supply large number of majority
carriers.
2. Base: The middle section of transistor is called base It is very thin and lightly doped
region.The base-emitter junction is forward biased allowing low resistance for the emitter circuit. The base
–collector junction is reverse biased offers high resistance for the collector circuit.
3.Collector : The other side that collects the charges is called the collector.The collector is
always reverse biased. The doping level of collector is between the heavy doping of emitter and light
doping of base.
Fig 4.9.4 (a) & 4.9.4 (b) shows the symbols of transistor.
Arrow is always placed on the emitter terminal and direction of arrow indicates the direction of current
flow.
Fig 4.9.4(a) Symbol of NPN Fig 4.9.4(b) Symbol of PNP
The method of applying external voltages to a transistor is called transistor biasing. The transistor
operations in three different regions based on the biasing of transistor.
Table 4.9.1
Causes Emitter base Collector base Region of operation
Junction Junction
1. Forward – biased Reverse – biased Active
2. Forward – biased Forward – biased Saturation.
3. Reverse – biased Reverse – biased Cut-off
1.Active Region: In this case the emitter base junction is forward biased and the collector –base junction
is reverse biased . In this region, the transistor is used for amplifications. The collector current is
dependent upon the base current.
2.Saturation Region: In this case, both junction are forward bias In this region of operation, the collector
current becomes independent of the base current. Now the transistor acts like a closed switch.
3. Cut off Region: In this case both junctions are reverse biased ,In this region the transistor has zero
current, because the emitter does not emit charge carriers, into base and no charge carriers are collected
by the collector .Now the transistor acts like a open switch.
∆Vi
Input impedance = / at constant Vo
∆Ii
∆Vo
Output impedance = / at constant Ii
∆Io
Fig CE Configuration
In this configuration, base is an input terminal, collector is an output terminal and emitter is the
common terminal. This is also called Grounded emitter configuration. The circuit of CE configuration, to
find out their characteristics is shown in the fig.
∆VBE
Input impedance =
∆IB
∆VCE
Output impedance =
∆IC
(i)Input characteristics
To determine the input characteristics, the reading will be taken between base to emitter voltage
(VBE) and base current (IB) at different constant levels of collector to emitter voltage(V CE). The fig shows
the input characteristics of CE mode.
IB
In this configuration, emitter is the input terminal, collector is the output terminal and base is the
common terminal. The circuit of CB configuration, to find out their characteristics is shown in the fig
Fig. CB configuration
∆VEB
Input impedance =
∆IE
∆VCB
Output impedance =
∆IC
The Biasing arrangement, makes the emitter-base junction forward biased and collector-base
junction reverse biased. So that the transistor operates only in the active region. This is achieved by
selecting the operating point (quiescent point or Q-point) properly. The zero signal values of Ic and VCE
are known as the operating point.
A simple CE amplifier circuit using fixed bias arrangement with battery is shown in fig.4.8.1. The
battery VBB is known as bias battery which keeps the emitter-base junction forward biased regardless of
the polarity of the input signal. The capacitors Ci and C0 are used for blocking the dc signal.
During the positive half cycle of the input signal, the forward bias across the emitter-base junction
is increased. Therefore more collector current flows through R c. However during the negative half cycle of
the input signal, the forward bias across the base-emitter junction is decreased. Therefore less collector
current flows through Rc. Hence an amplified output is obtained across the load (R c).
When no signal is applied, the input circuit is forward biased by the battery V BB. Therefore a DC
collector current flows in the collector circuit. This is called zero signal collector current (ICQ) . For more
signal amplifications, the zero signal collector current (I CQ) is fixed at (1/2) IC (max) level, by choosing
proper bias voltage.
One of the methods can be used to plot the output characteristics and determine the proper
collector current and collector-emitter voltage. However, a more convenient method, known as load line
method can be used to select the proper operating point. This method is quite easy and frequently used
in the analysis of transistor applications. The circuits used for getting the desired and proper operating
point are known as biasing circuits.
S.No Characteristics CB CE CC
1. Input impedance Low Medium High
2. Output impedance High Medium Low
3. Current gain Low High High
4. Voltage gain High High Unity
5. Power gain Medium High Low
6. Phase reversal No Yes No
7. Application AF amplifiers Voltage and Power Impedance
Amplifiers matching
When the supply is turned ON, the capacitor ‘C’ is charged. When this capacitor is fully charged,
it discharges through the coils L1 and L2, setting up an oscillation. The output voltage of the amplifier
appears across L1 and the feedback voltage appears across L 2. The voltage across L2 is 1800 out of
phase with the output voltage.it is the feedback signal. A phase shift of another 180 0 is produced by CE
amplifier. Hence the total phase shift between input and output is 180 0 + 1800 = 3600. This results in
positive feedback which makes the oscillation as continuous undamped.
The frequency of the oscillation is given by,
1
F=
2𝜋√𝐿𝐶
Where, L = L1 + L2
When the supply is switched ON, the random variations of base current caused by noise
variations in the transistor and voltage variations in the power source produce oscillation. This variation is
amplified by the CE amplifier.
The feedback network consists of three stages of RC networks. The three stages are identical.
The feedback section provides 180o phase shift because each RC network provides 60o phase shift
(3X60o = 180o). The CE amplifier provides another 180o phase shift. Hence the total phase shift is 360o,
which provides positive feedback. Therefore, continuous undamped oscillation is produced.
4.13.2 Advantages:
4.13.3 Disadvantages:
The source is a terminal, where majority carriers enter the bar. The drain is a terminal where
majority carriers leave the bar. The region between source and drain is called channel. The majority
carriers move from source to drain through this channel. The gate terminal controls the flow of majority
carriers from source to drain.
The N-channel JFET is normally biased by applying negative potential(V GS) to the gate with
respect to source. A positive potential (VDS) is applied to the drain terminal with respect to source. The
drain characteristics are obtained by taking the readings in between V DS and ID, with a constant variation
of VGS.
Fig 4.14.2 Operation of N-channel JFET
When VGS=0, the two P-N junctions established a very thin and uniform depletion layer. Thus a
large amount of electrons will flow from drain to source through a wide channel, in between the depletion
region. This constitutes drain current ID.
When the reverse voltage VGS is increased, it increases the width of the depletion region. This
reduces the width of the channel. So the current (I D) flow is also reduced. The channel width is larger in
the source region than the drain region.
Thus the current flowing through the channel is controlled by the reverse potential applied to the
gate terminal. The circuit diagram to determine the characteristics of N-channel JFET is shown in
fig.4.14.3
Fig 4.14.4 Drain characteristics of N-Channel JFET
This circuit diagram is used to find out the drain and source characteristics of the JFET. The graph
drawn between VDS and ID is known as drain characteristics or output characteristics. Three regions are
formed in the drain characteristics, they are linear region, saturation region and breakdown region.
4.14.3 Applications:
4.15 MOSFET
` The MOSFET is an abbreviation of metal oxide semiconductor field effect transistor. In MOSFET,
the gate is insulated from the channel by using SiO2 layer. The input impedance of MOSFET is high,
because the gate current is very small. It is also called insulated Gate FET( IGFET). There are two types
of MOSFETs. They are ,
i.) Enhancement MOSFET (E-MOSFET)
ii.) Depletion MOSFET (DE- MOSFET)
A proper biasing of N-channel E-MOSFET is given in fig., The gate is driven by only drain potential
(VGS) with respect to source. The drain is kept positive potential (V DS) with respect to source. When VGS is
equal to zero, the PN junction between drain and substrate is reverse biased. Hence only a small leakage
current (ID) flow through the device.
When the gate is driven by positive potential, the electrons (minority carriers) in the P-substrate
are moved towards the gate terminal. By the effect of layer SiO 2(insulator) , the electrons induce a N-
channel between drain and source, which improve the conductivity. The minimum gate voltage, which
produces N-channel layer between drain and source is called threshold voltage.
The drain and transfer characteristics of N-channel E-MOSFET are shown in the fig., From the
figures we understand that the increasing gate voltage(V GS) increase the drain current ID. The amount of
flow of drain current depends upon the width are density of the induced channel, which depends upon
applied gate voltage.
In the transfer characteristics, the drain current is plotted against gate voltage(V GS) at the constant
levels of VDS. At zero VGS level, the current ID is almost zero, because leakage current only flows. Then
the drain current is increased linearly with the increasing of gate voltage.
Operation: The depletion MOSFET can be operated two modes. They are,
i.) Depletion mode
ii.) Enhancement mode
In depletion the gate is maintained at negative potential and the drain is maintained at positive
potential with respect to source. The negative voltage on the gate attracts the holes in the P-type
substrate. Thus the holes are moved towards the gate terminal. Because of the SiO2(insulator) layer, the
holes are induced in the N-channel, which reduces the charge carriers(electrons) in the N-channel. So
the conductivity decreases, the value of drain current also decreases.
The transfer characteristic represents the flow of drain current with a variation of VGS, at the
constant of VDS potential. The drain current increases in enhancement mode and decreases in depletion
mode.
TWO MARKS
2. What is transistor?
Transistor consist of two junctions formed by sandwiching either P-type or N-type Semiconductor
between a pair of opposite types.