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2N7002K — N-Channel Enhancement Mode Field Effect Transistor

September 2014

2N7002K
N-Channel Enhancement Mode Field Effect Transistor
Features
• Low On-Resistance
• Low Gate Threshold Voltage
• Low Input Capacitance
• Fast Switching Speed
• Low Input / Output Leakage
• Ultra-Small Surface Mount Package
• Pb Free / RoHS Compliant
• ESD HBM = 2000 V (Typical: 3000 V) as per JESD22 A114
and ESD CDM = 2000 V as per JESD22 C101

D
D

G
SOT-23
Marking: 7K G S

Ordering Information
Part Number Top Mark Package Packing Method
2N7002K 7K SOT-23 3L Tape and Reel

Absolute Maximum Ratings


Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be opera-
ble above the recommended operating conditions and stressing the parts to these levels is not recommended. In addi-
tion, extended exposure to stresses above the recommended operating conditions may affect device reliability. The
absolute maximum ratings are stress ratings only. Values are at TA = 25°C unless otherwise noted.

Symbol Parameter Value Unit


VDSS Drain-Source Voltage 60 V
VDGR Drain-Gate Voltage (RGS ≤ 1.0 MΩ) 60 V
VGSS Gate-Source Voltage ±20 V
Continuous 300
ID Drain Current mA
Pulsed 800
TJ Operating Junction Temperature Range -55 to +150 °C
TSTG Storage Temperature Range -55 to +150 °C

© 2009 Fairchild Semiconductor Corporation www.fairchildsemi.com


2N7002K Rev. 1.1.0
2N7002K — N-Channel Enhancement Mode Field Effect Transistor
Thermal Characteristics
Values are at TA = 25°C unless otherwise noted.

Symbol Parameter Value Unit


Total Power Dissipation 350 mW
PD
Derate Above TA = 25°C 2.8 mW/°C
RθJA Thermal Resistance, Junction-to-Ambient(1) 350 °C/W

Note:
1. Device mounted on FR-4 PCB, 1 inch x 0.85 inch x 0.062 inch. Minimum land pad size.

Electrical Characteristics
Values are at TA = 25°C unless otherwise noted.

Symbol Parameter Conditions Min. Max. Unit


Off Characteristics(2)
BVDSS Drain-Source Breakdown Voltage VGS = 0 V, ID = 10 μA 60 V
VDS = 60 V, VGS = 0 V 1.0
IDSS Zero Gate Voltage Drain Current VDS = 60 V, VGS = 0 V, μA
500
TJ = 125°C
IGSS Gate-Body Leakage VGS = ±20 V, VDS = 0 V ±10 μA
On Characteristics(2)
VGS(th) Gate Threshold Voltage VDS = VGS, ID = 250 μA 1.0 2.5 V
VGS = 10 V, ID = 0.5 A 2
RDS(ON) Static Drain-Source On-Resistance Ω
VGS = 4.5 V, ID = 200 mA 4
ID(ON) On-State Drain Current VGS = 10 V, VDS = 7.5 V 1.5 A
gFS Forward Transconductance VDS = 10 V, ID = 0.2 A 200 mS
Dynamic Characteristics
Ciss Input Capacitance 50 pF
VDS = 25 V, VGS= 0 V,
Coss Output Capacitance 15 pF
f = 1.0 MHz
Crss Reverse Transfer Capacitance 6 pF
Switching Characteristics
tD(ON) Turn-On Delay Time VDD = 30 V, IDSS = 200 mA, 5 ns
tD(OFF) Turn-Off Delay Time RG = 10 Ω, VGS = 10 V 30 ns

Note:
2. Short duration test pulse used to minimize self-heating effect.

© 2009 Fairchild Semiconductor Corporation www.fairchildsemi.com


2N7002K Rev. 1.1.0 2
2N7002K — N-Channel Enhancement Mode Field Effect Transistor
Typical Performance Characteristics

2.0 3.0

VGS = 3V
ID. DRAIN-SOURCE CURRENT(A)

VGS = 10V

DRANI-SOURCE ON-RESISTANCE
4V
2.5
1.5
5V
4.5V

RDS(on), (Ω)
5V
2.0 6V
4V 7V
1.0

1.5

3V
0.5
1.0 10V
9V
2V 8V
0.0 0.5
0 2 4 6 8 10 0.0 0.2 0.4 0.6 0.8 1.0
VDS. DRAIN-SOURCE VOLTAGE (V) ID. DRAIN-SOURCE CURRENT(A)

Figure 1. On-Region Characteristics Figure 2. On-Resistance Variation with Gate Voltage


and Drain Current

3.0
VDS = 10V
ID = 500 mA
DRANI-SOURCE ON-RESISTANCE

2.5
RDS(on) (Ω)

2.0

1.5

1.0

0.5
-50 0 50 100 150
o
TJ. JUNCTION TEMPERATURE( C)

Figure 3. On-Resistance Variation with Temperature Figure 4. On-Resistance Variation


with Gate-Source Voltage

1.0 2.0
Vth, Gate-Source Threshold Voltage (V)

VDS = 10V
ID. DRAIN-SOURCE CURRENT(A)

25( C)
o
VDS = VGS

0.8 1.8
o
TJ = -25( C)
ID = 1 mA
o
150( C)
0.6 1.6
ID = 0.25 mA
o
125( C)
0.4 1.4
o
75( C)

0.2 1.2

0.0 1.0
2 3 4 5 6 -50 0 50 100 150
o
VGS. GATE-SOURCE VOLTAGE (V) TJ. JUNCTION TEMPERATURE( C)

Figure 5. Transfer Characteristics Figure 6. Gate Threshold Variation with Temperature

© 2009 Fairchild Semiconductor Corporation www.fairchildsemi.com


2N7002K Rev. 1.1.0 3
2N7002K — N-Channel Enhancement Mode Field Effect Transistor
Typical Performance Characteristics (Continued)

VGS = 0 V

VGS, GATE-SOURCE VOLTAGE (V)


IS Reverse Drain Current, [mA]

100

o
TA=150 C

o
10 25 C 500mA

280mA

115mA
o
-55 C

1
0.0 0.2 0.4 0.6 0.8 1.0

VSD, Body Diode Forward Voltage [V] Qg - Gate Charge

Figure 7. Reverse Drain Current Variation with Diode Figure 8. Gate Charge Characteristics
Forward Voltage and Temperature

0.5 100 μs
ID, DRAIN CURRENT (A)

RDS(ON) LIMIT
1ms

0.05
SINGLE PULSE
RθJA = 350oC/W 10ms
TA = 25oC
100ms
1s
10s
DC
0.005
0.01 0.1 1 10 100 200
VDS, DRAIN-SOURCE VOLTAGE (V)

Figure 9. Maximum Safe Operating Area

© 2009 Fairchild Semiconductor Corporation www.fairchildsemi.com


2N7002K Rev. 1.1.0 4
2N7002K — N-Channel Enhancement Mode Field Effect Transistor
Physical Dimensions

2.92±0.20 0.95

3
1.40

1.30+0.20
-0.15 2.20

1 2
(0.29) 0.60
0.95 0.37
0.20 A B 1.00
1.90 1.90
LAND PATTERN
RECOMMENDATION

1.20 MAX SEE DETAIL A

(0.93) 0.10
0.00
0.10 C
C 2.40±0.30

NOTES: UNLESS OTHERWISE SPECIFIED


GAGE PLANE
A) REFERENCE JEDEC REGISTRATION
TO-236, VARIATION AB, ISSUE H.
0.23 B) ALL DIMENSIONS ARE IN MILLIMETERS.
0.08 C) DIMENSIONS ARE INCLUSIVE OF BURRS,
0.25 MOLD FLASH AND TIE BAR EXTRUSIONS.
D) DIMENSIONING AND TOLERANCING PER
ASME Y14.5M - 1994.
0.20 MIN SEATING E) DRAWING FILE NAME: MA03DREV10
(0.55) PLANE

SCALE: 2X

Figure 10. 3-LEAD, SOT23, JEDEC TO-236, LOW PROFILE

© 2009 Fairchild Semiconductor Corporation www.fairchildsemi.com


2N7002K Rev. 1.1.0 5
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Datasheet contains the design specifications for product development. Specifications may change
Advance Information Formative / In Design
in any manner without notice.
Datasheet contains preliminary data; supplementary data will be published at a later date. Fairchild
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Obsolete Not In Production
The datasheet is for reference information only.
Rev. I71
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