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Mosfet FD
DH5500
O
Ovaj tranzistor je izz Fairchild porodic
ce N-kanalnih Ultrra Mos-fe tranzisttora, te se zbog visoke strujne provodljivosti, a i druggih pratećih karaktteristika
preporučuje za apllikacije kao sto su u; kontrola motora, kontrola solenoida, ''switch'' regulatorima, automobbilskoj industriji itd
d.
U
Ukupna snaga dissipacije 25 °C (W) 37
75
K
Kućište TO-247
T
75344G
FDH5500_F085 N-Channel UltraFET Power MOSFET
October 2008
FDH5500_F085
N-Channel UltraFET Power MOSFET
55V, 75A, 7mΩ
Features Applications
Typ rDS(on) = 5.2mΩ at VGS = 10V, ID = 75A DC Linear Mode Control
Typ Qg(10) = 118nC at VGS = 10V Solenoid and Motor Control
Simulation Models
Switching Regulators
-Temperature Compensated PSPICE and SABERTM
Models Automotive Systems
Peak Current vs Pulse Width Curve
UIS Rating Curve
Related Literature
-TB334, “Guidelines for Soldering Surface Mount
Componets to PC Boards“
Qualified to AEC Q101
RoHS Compliant
Thermal Characteristics
RθJC Thermal Resistance Junction to Case 0.4 oC/W
RθJA Thermal Resistance Junction to Ambient TO-247, 1in2 copper pad area 30 o
C/W
Off Characteristics
BVDSS Drain to Source Breakdown Voltage ID = 250μA, VGS = 0V 55 - - V
VDS = 50V, VGS = 0V - - 1
IDSS Zero Gate Voltage Drain Current μA
VDS = 45V TC = 150oC - - 250
IGSS Gate to Source Leakage Current VGS = ±20V - - ±100 nA
On Characteristics
VGS(th) Gate to Source Threshold Voltage VGS = VDS, ID = 250μA 2 2.9 4 V
rDS(on) Drain to Source On Resistance ID = 75A, VGS= 10V - 5.2 7 mΩ
Dynamic Characteristics
Ciss Input Capacitance - 3565 - pF
VDS = 25V, VGS = 0V,
Coss Output Capacitance - 1310 - pF
f = 1MHz
Crss Reverse Transfer Capacitance - 395 - pF
Qg(TOT) Total Gate Charge at 20V VGS = 0 to 20V - 206 268 nC
Qg(10) Total Gate Charge at 10V VGS = 0 to 10V VDD = 30V - 118 153 nC
ID = 75A
Qg(TH) Threshold Gate Charge VGS = 0 to 2V - 6.2 8.1 nC
RL = 0.4Ω
Qgs Gate to Source Gate Charge Ig = 1.0mA - 17.8 - nC
Qgd Gate to Drain “Miller“ Charge - 51 - nC
Switching Characteristics
ton Turn-On Time - - 185 ns
td(on) Turn-On Delay Time - 13.7 - ns
VDD = 30V, ID = 75A,
tr Rise Time - 102 - ns
RL = 0.4Ω, VGS = 10V,
td(off) Turn-Off Delay Time RGS = 2.5Ω - 34 - ns
tf Fall Time - 22 - ns
toff Turn-Off Time - - 91 ns
This product has been designed to meet the extreme test conditions and environment demanded by the automotive industry. For
a copy of the requirements, see AEC Q101 at: http://www.aecouncil.com/
All Fairchild Semiconductor products are manufactured, assembled and tested under ISO9000 and QS9000 quality systems
certification.
1.2 180
POWER DISSIPATION MULTIPLIER
CURRENT LIMITED
1.0 150 BY PACKAGE
0.6 90
0.4 60
0.2 30
0.0 0
0 25 50 75 100 125 150 175 25 50 75 100 125 150 175
TC, CASE TEMPERATURE(oC) TC, CASE TEMPERATURE(oC)
Figure 1. Normalized Power Dissipation vs Case Figure 2. Maximum Continuous Drain Current vs
Temperature Case Temperature
2
D = 0.50 PDM
0.20
0.10
0.05
0.1 t1
0.02
0.01 t2
NOTES:
DUTY FACTOR: D = t1/t2
PEAK TJ = PDM x ZθJA x RθJA + TC
SINGLE PULSE
0.01
-5 -4 -3 -2 -1
10 10 10 10 10 1 10
t, RECTANGULAR PULSE DURATION(s)
Figure 3. Normalized Maximum Transient Thermal Impedance
10000
TC = 25oC
VGS = 10V
FOR TEMPERATURES
ABOVE 25oC DERATE PEAK
IDM, PEAK CURRENT (A)
CURRENT AS FOLLOWS:
1000 175 - TC
I = I2
150
100
SINGLE PULSE
10
-5 -4 -3 -2 -1 0 1
10 10 10 10 10 10 10
t, RECTANGULAR PULSE DURATION(s)
1000 1000
If R = 0
If R ≠ 0
100us tAV = (L/R)ln[(IAS*R)/(1.3*RATED BVDSS - VDD) +1]
100
100
1ms
10 STARTING TJ = 25oC
10ms
10
DC
1 STARTING TJ = 150oC
OPERATION IN THIS SINGLE PULSE
AREA MAY BE TJ = MAX RATED
LIMITED BY rDS(on) TC = 25oC
0.1 1
0.01 0.1 1 10 100 1000 5000
1 10 100 200 tAV, TIME IN AVALANCHE (ms)
VDS, DRAIN TO SOURCE VOLTAGE (V)
NOTE: Refer to Fairchild Application Notes AN7514 and AN7515
Figure 5. Forward Bias Safe Operating Area Figure 6. Unclamped Inductive Switching
Capability
160
160 VGS = 10V
PULSE DURATION = 80μs
DUTY CYCLE = 0.5% MAX PULSE DURATION = 80μs
ID, DRAIN CURRENT (A)
120
VGS = 6V VGS = 5.5V
80
80
TJ = 175oC VGS = 5V
40
40 TJ = -55oC
VGS = 4.5V
TJ = 25oC
0
0 0 1 2 3 4 5
0 1 2 3 4 5 6 7
VDS, DRAIN TO SOURCE VOLTAGE (V)
VGS, GATE TO SOURCE VOLTAGE (V)
40 2.2
DRAIN TO SOURCE ON-RESISTANCE
30 1.8
NORMALIZED
1.6
20 1.4
TJ = 175oC
1.2
10 1.0
o 0.8 ID = 75A
TJ = 25 C
VGS = 10V
0 0.6
4 6 8 10 -80 -40 0 40 80 120 160 200
VGS, GATE TO SOURCE VOLTAGE (V) TJ, JUNCTION TEMPERATURE(oC)
1.2 1.20
VGS = VDS ID = 1mA
BREAKDOWN VOLTAGE
1.0
NORMALIZED GATE
1.10
1.05
0.8
1.00
0.95
0.6
0.90
0.4 0.85
-80 -40 0 40 80 120 160 200 -80 -40 0 40 80 120 160 200
TJ, JUNCTION TEMPERATURE(oC) TJ, JUNCTION TEMPERATURE (oC)
Figure 11. Normalized Gate Threshold Voltage vs Figure 12. Normalized Drain to Source
Junction Temperature Breakdown Voltage vs Junction Temperature
10000 10
VGS, GATE TO SOURCE VOLTAGE(V) ID = 75A
CAPACITANCE (pF)
8
VDD = 20V VDD = 30V
Ciss
6 VDD = 40V
1000
4
Coss
2
f = 1MHz
VGS = 0V Crss
100 0
0.1 1 10 80 0 20 40 60 80 100 120 140
VDS, DRAIN TO SOURCE VOLTAGE (V) Qg, GATE CHARGE(nC)
Figure 13. Capacitance vs Drain to Source Figure 14. Gate Charge vs Gate to Source Voltage
Voltage
PDP SPM™ ®
FPS™
Power-SPM™
* EZSWITCH™ and FlashWriter® are trademarks of System General Corporation, used under license by Fairchild Semiconductor.
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Datasheet contains preliminary data; supplementary data will be published at a later date.
Preliminary First Production Fairchild Semiconductor reserves the right to make changes at any time without notice to
improve design.