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MEM1763/1742 SYSTEM IDENTIFICATION AND ESTIMATION ASSIGNMENT 2 DESIGN PSEUDO RANDOM BINARY SEQUENCE (PRBS) OF 15 STAGES

MEM1763/1742

SYSTEM IDENTIFICATION AND ESTIMATION

ASSIGNMENT 2

DESIGN PSEUDO RANDOM BINARY SEQUENCE (PRBS) OF 15 STAGES SHIFT REGISTER USING SIMULINK AND HARDWARE

Prepared for:

Lecturer: Assoc. Prof. Dr. Mohd Fua’ad Rahmat

Prepared by:

Name

:

Nurul Syahirah Binti Khalid

Matrix

:

ME101156

Name

:

Masmaria Binti Abd Majid

Matrix

:

ME081600

The objective of this report is:

  • 1. To design of pseudo random binary sequence (PRBS) of 15 stages shift register using Simulink and hardware construction.

  • 2. To verify the PRBS output, using hardware construction.

Pseudo Random Binary Sequence (PRBS) generator with a given MLS Using Math Lab

MLS, N=2 n -1 = 32767

where n= 15. The orientation of bit on shift register are tabulate in

Appendix 1 for only until 40 clock. SR1 SR2 SR3 SR4 SR5 SR6 SR7 SR8 SR9
Appendix 1 for only until 40 clock.
SR1
SR2
SR3
SR4
SR5
SR6
SR7
SR8
SR9
SR10
SR11
SR12
SR13
SR14
SR15
Xo
r
Outpu
t

Figure 1 : PRBS

PART A: PRBS using SIMULINK

PRBS signal also simulate in Simulink. In Simulink it constructed based on PRBS equation, N=2 n -1. In our case , n is equal to 15.Therefore,we need to used 15 flip flop in order to make a shift register. To built shift register we used D flip flop but in Simulink, the limitation of using D flip flop is it cannot set the initial condition of the flip flop. Therefore JK flip flop are used to function as a D flip flop to make it as a shift register. Means the JK flip flop are designed to be a subsystem of D flip flop. In order to make JK flip flop to function as D flip flop, the input of K are complement of input J. The subsystems of the D flip flop as shown in Figure 3. The construction of PRBS using subsystem of JK flip flop are shown in Figure 2 .We use output of Q15 as our PRBS output and the input of our shift register is a feedback from the output Q1 XOR with the ouput of Q15.The results after simulation are shown in Figure 4

.

PART A: PRBS using SIMULINK PRBS signal also simulate in Simulink. In Simulink it constructed based

Figure 2: PRBS using SIMULINK

Figure 3 : Subsytem of D flip flop Figure 4: Output of Q15 and Q1 XOR

Figure 3 : Subsytem of D flip flop

Figure 3 : Subsytem of D flip flop Figure 4: Output of Q15 and Q1 XOR

Figure 4: Output of Q15 and Q1 XOR Q15

PART B: Circuit construction using TINA software.

Circuit for PRBS are design using TINA software. The hardware description consists of voltage regulator, timer, operational amplifier and 8 bit shift register . Voltage regulator (LM7805C) used to regulate voltage from 9V to 5V to source the circuits and timer NE555 function as a CLK to shift register. In our case, we use 8-bit serial in shift register (SN74164) . It will shift the output to the next flip flop to the right. Our input is a feedback from the output of Q1 XOR with output of Q15. The operational amplifier (LM741) are used to amplifier the signal from the output of the shift register. PRBS of the signal are measure using oscilloscope, in our case we choose output of Q15 as our PRBS signal. After simulation the result of PRBS as shown in Figure 6, while circuit construction are shown in Figure 5.

8 QB 1M P1 R1 13 QH QH 12 QG QG 11 QF QF + 1
8 QB
1M
P1
R1
13 QH
QH
12 QG
QG
11 QF
QF
+
1 QC
9 QA
2 QD
6 B
5 A
4 CLK
3 CLR
10 QE
LED1
C1
10n
GND
TRIG
THRES
CONT
VCC
RESET
U5
B
R5 15K
R2
R4 36k
-
Ch2
+
-
Ch1
13
U1
V1
P2
V2
OUT
OUT
DISC
IN
3
U6
6
10
12
11
5
4
+
+
U3
A
QE
CLK
CLR
8 QB
1 QC
9 QA
2 QD
-
U2
100n
GND
10u
C3
U4
C1
OSC2

Figure 5 : TINA Simulation for PRBS

Figure 6 : Output of PRBS after simulation of TINA From the results that obtain by

Figure 6 : Output of PRBS after simulation of TINA

From the results that obtain by using the TINA software, we can say that the waveform is the same with the waveform by using SIMULINK and same with the theoretical. After that, the hardware for the circuit is constructing so that the real circuit can be test by using oscilloscope. Figure 7 show the circuit that constructed. After that, we test the output (PRBS) by using ociloscopes. Figure 8 show the several output that we get from the circuit( purple line for clock and green line for PRBS output)

Figure 7: Circuit for PRBS.
Figure 7: Circuit for PRBS.

Figure 7: Circuit for PRBS.

Figure 8: Several Waveform for clock and PRBS taken for different value.
Figure 8: Several Waveform for clock and PRBS taken for different value.

Figure 8: Several Waveform for clock and PRBS taken for different value.

Conclusion :

The output of PRBS between Simulink ,TINA software and hardware are the same.We also construct the PRBS results also in truth table as shown in Appendix 1. In our case, because of big value of PRBS we just construct the truth table until 40 clock only in order to verify our simulation result.

CLK

SR1

SR2

SR3

SR4

SR14

SR15

1xor5

1

 
  • 1 1

 
  • 1 1

                 

1

1

0

2

  • 0 1

   
  • 1 1

 
  • 1 1

  • 1 1

 

1

 
  • 1 1

1

1

 

1

1

1

3

 
  • 1 0

 
  • 1 1

 
  • 1 1

  • 1 1

 

1

 
  • 1 1

1

1

 

1

1

0

4

  • 0 1

   
  • 0 1

 
  • 1 1

  • 1 1

 

1

 
  • 1 1

1

1

 

1

1

1

5

 
  • 1 0

 
  • 1 0

 
  • 1 1

  • 1 1

 

1

 
  • 1 1

1

1

 

1

1

0

6

  • 0 1

   
  • 0 1

 
  • 0 1

  • 1 1

 

1

 
  • 1 1

1

1

 

1

1

1

7

 
  • 1 0

 
  • 1 0

 
  • 1 1

    • 0 1

   

1

 
  • 1 1

1

1

 

1

1

0

8

  • 0 1

   
  • 0 1

 
  • 0 1

  • 1 0

 

1

 
  • 1 1

1

1

 

1

1

1

9

 
  • 1 0

 
  • 1 0

 
  • 1 0

    • 0 1

   

1

 
  • 1 1

1

1

 

1

1

0

10

  • 0 1

   
  • 0 1

 
  • 0 1

  • 1 0

 

0

 
  • 1 1

1

1

 

1

1

1

11

 
  • 1 0

 
  • 1 0

 
  • 1 0

    • 0 1

   

1

 
  • 0 1

1

1

 

1

1

0

12

  • 0 1

   
  • 0 1

 
  • 0 1

  • 1 0

 

0

 
  • 1 1

0

1

 

1

1

1

13

 
  • 1 0

 
  • 1 0

 
  • 1 0

    • 0 1

   

1

 
  • 0 1

1

0

 

1

1

0

14

  • 0 1

   
  • 0 1

 
  • 0 1

  • 1 0

 

0

 
  • 1 0

0

1

 

1

1

1

15

 
  • 1 0

 
  • 1 0

 
  • 1 0

    • 0 1

   

1

 
  • 0 1

1

0

 

0

1

0

16

  • 0 1

   
  • 0 1

 
  • 0 1

  • 1 0

 

0

 
  • 1 0

0

1

 

1

0

0

17

 
  • 0 0

 
  • 1 0

 
  • 1 0

    • 0 1

   

1

 
  • 0 1

1

0

 

0

1

1

18

 
  • 1 0

 
  • 0 1

 
  • 0 1

  • 1 0

 

0

 
  • 1 0

0

1

 

1

0

1

19

 
  • 1 1

 
  • 0 0

 
  • 1 0

    • 0 1

   

1

 
  • 0 1

1

0

 

0

1

0

20

  • 0 1

   
  • 1 0

 
  • 0 1

  • 1 0

 

0

 
  • 1 0

0

1

 

1

0

0

21

 
  • 0 0

 
  • 1 1

 
  • 0 0

    • 0 1

   

1

 
  • 0 1

1

0

 

0

1

1

22

 
  • 1 0

 
  • 0 1

 
  • 1 1

  • 0 0

 

0

 
  • 1 0

0

1

 

1

0

1

23

 
  • 1 1

 
  • 0 0

 
  • 1 0

  • 1 0

 

1

 
  • 0 1

1

0

 

0

1

0

24

  • 0 1

   
  • 1 0

 
  • 0 0

  • 1 1

 

0

 
  • 1 0

0

1

 

1

0

0

25

 
  • 0 0

 
  • 1 1

 
  • 0 1

    • 0 1

   

0

 
  • 0 1

1

0

 

0

1

1

26

 
  • 1 0

 
  • 0 1

 
  • 1 1

  • 0 0

 

1

 
  • 0 0

0

1

 

1

0

1

27

 
  • 1 1

 
  • 0 0

 
  • 1 0

  • 1 0

 

1

 
  • 1 1

0

0

 

0

1

0

28

  • 0 1

   
  • 1 0

 
  • 0 0

  • 1 1

 

0

 
  • 1 0

1

0

 

1

0

0

29

 
  • 0 0

 
  • 1 1

 
  • 0 1

    • 0 1

   

0

 
  • 0 0

1

1

 

0

1

1

30

 
  • 1 0

 
  • 0 1

 
  • 1 1

  • 0 0

 

1

 
  • 0 1

0

1

 

0

0

1

31

 
  • 1 1

 
  • 0 0

 
  • 1 0

  • 1 0

 

1

 
  • 1 1

0

0

 

1

0

1

32

 
  • 1 1

 
  • 1 0

 
  • 0 0

  • 1 1

 

0

 
  • 1 0

1

0

 

1

1

0

33

  • 0 1

   
  • 1 1

 
  • 0 1

    • 0 1

   

0

 
  • 0 0

1

1

 

0

1

1

34

 
  • 1 0

 
  • 1 1

 
  • 1 1

  • 0 0

 

1

 
  • 0 1

0

1

 

0

0

1

35

 
  • 1 1

 
  • 0 1

 
  • 1 0

  • 1 0

 

1

 
  • 1 1

0

0

 

1

0

1

36

 
  • 1 1

 
  • 1 0

 
  • 1 0

  • 1 1

 

0

 
  • 1 0

1

0

 

1

1

0

37

  • 0 1

   
  • 1 1

 
  • 0 1

  • 1 1

 

0

 
  • 0 0

1

1

 

0

1

1

38

 
  • 1 0

 
  • 1 1

 
  • 1 1

    • 0 1

   

1

 
  • 0 1

0

1

 

0

0

1

39

  • 1 1

  • 0 1

  • 1 1

    • 1 0

1

  • 1 1

0

0

1

0

1