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CMOS Inverter Amplifier

(3) VDD

(25.8U/5.4U)
M2/MP
IP
(1) (2)
Vi Vo

IN

M1/MN
(9.6U/5.4U)

(4) VSS

1. Low Frequency Small Signal Equivalent Circuit

Figure 2( a) shows its low frequency equivalent circuit. That is, all the stray capacitances are
ignored. In this circuit, PMOS transistor MP acts as the load of the driver NMOS transistor MN , and vice
versa. That is, each transistor acts as the load of the other. Hence, an unloaded two-port parameters are to
be determined. Comparing Figure 2(a) and Figure 2( b), one obtains:
YL = 0 (or Z L = ∞); YS = ∞ (or ZS = 0)

V1 = Vi = Vgs1
and
V2 = Vo
From Fig 2, the current equations are derived to obtain the Y parameters:

I1 = 0
I 2 = (g m1 + g m2 )V1 + (g ds1 + g ds2 )V2

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Vi I1 G1 =G2 D 1 D2 I2
+ + +

g m2v gs1
gm1v gs1
V1 V2
vgs1 g ds1 VO g ds2
- - -
S1 S2

(a)

I1 I2
+ +

V1 Y V2

Zi Zo
(b)

That is, the Y-parameter matrix is given by:

 0 0 
Y= ; detY = 0
g m1 + g m2 g ds1 + g ds2 
The input impedance of common source circuit,
y 22 + YL g + g ds2 + 0
Zi = = ds1 =∞
detY + y11 YL 0 + (0)(0)
The output impedance of the common source circuit,

y11 + YS 1 1
Zo = = =
detY + y 22 YS y 22 g ds1 + g ds2

The dc voltage gain is,

y 21 g + g m2
A V0 = − = − m1 or
y 22 + YL g ds1 + g ds2
1
A V0 = −2g m1 Z o = −g m1R out ; R out = Z o = ; g m1 = g m2
g ds1 + g ds2
2
The current gain is,

y 21 YL (g + g m2 )(0)
AI = − = − m1 = undefined
detY + y11 YL 0 + 0( 0)

The small signal dc gain can also be derived mathematically. This elegant method is applicable to this
circuit configuration only.

IN = IP
I DSN (Vi , Vo ) = −I DSP (Vi , Vo )
dI DSN (Vi , Vo ) = −dI DSP (Vi , Vo )

(∂IDSN / ∂Vi) d Vi + (∂IDSN / ∂Vo) d Vo = -(∂IDSP / ∂Vi) d Vi - (∂IDSP / ∂Vo) d Vo

Solve for Av = d Vi / d Vo

Av = d Vi / d Vo = [- (∂IDSN / ∂Vi )-(∂IDSP / ∂Vi)]/[ (∂IDSN / ∂Vo)+ (∂IDSP / ∂Vo)]

For the MN transistor:
VGSN = Vi - VSS , VDSN = Vo - VSS . Therefore ∂Vi = ∂ VGSN,, and ∂Vo = ∂ VDSN
For the MP transistor:
VGSP = Vi - VDD, VDSP = Vo- VDD. Therefore ∂Vi = ∂ VGSP,, and ∂Vo = ∂ VDSP
That is, the gain equation is rewritten as follows:

2. CMOS Inverter Static Characteristic

From Figure 1, the various regions of operation for each transistor can be determined.
MN Transistor Operating Regions:
• Cutoff
VGSN < VTN
Vi – VSS < VTN
Vi < VTN + VSS = 1+(-2.5)=-1.5
Vi < -1.5
• Saturation
VGSN - VTN < VDSN
Vi – VSS - VTN < VO - VSS
Vi – 1 < VO
• Ohmic
Vi – 1 >= VO
MP Transistor Operating Regions:
• Cutoff
|VGSP| < |VTP|

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|Vi – VDD|< |VTP|
VDD – Vi < - VTP ; since VTP <0
or VTP + VDD =(-1)+2.5=1.5V
Vi > 1.5V
• Saturation
|VGSP| - |VTP| < |VDSP|
|Vi – VDD| - |VTP| < |VO – VDD|
or VDD - Vi + VTP < VDD-VO
Vi – VTP > VO
Vi + 1 > VO
• Ohmic
Vi + 1 <= VO

These are summarized as follows:

Operating Region MN MP
Cutoff Vi < -1.5V Vi > 1.5V
Saturation Vi – 1 < VO Vi + 1 > VO
Ohmic Vi – 1 >= VO Vi + 1 <= VO

The various regions of operating of inverting cmos amplifier are summarized as follows:

Operating Region MN MP
Region I Cutoff Ohmic
Region II Saturation Ohmic
Region III Saturation Saturation
Region IV Ohmic Saturation
Region V Ohmic Cutoff

These regions are shown in the Pspice transfer characteristic graph, see Figure 3.

With zero output current (assuming driving a cmos type load) the load current is equal to the
driver current, i.e.
iP = iN

For the PMOS transistor MP, the current equation for saturated case is given by:
i DS = − i P = − ( β P / 2 )[ VGS − VTP ] when VGS − VTP ≤ VDS
2

i P = ( β P / 2 )[ Vi − VDD − VTP ] when Vi − VDD − VTP ≤ Vo − VDD

2

The absolute value symbol can be eliminated by accounting for the sign of each term within the symbol.
For PMOS transistor the following hold: Vi<VDD, VTP<0, Vo-VDD<0. The above current equation reduces
to:
i P = ( β P / 2 )[( VDD − Vi ) + VTP ] when ( VDD − Vi ) + VTP ≤ VDD − Vo or Vi − VTP > Vo
2

Similarly, the PMOS current equation for the non-saturated case is given by:
i P = β P [( VDD − Vi + VTP )( VDD − Vo ) − ( VDD − Vo ) / 2] when Vi − VTP ≤ Vo
2

For the NMOS driver transistor MN current equations are given by:

2

2

Inverter Static Characteristic

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The static characteristic is determined by equating the corresponding current equations at each voltage
range:

1. Vi - VSS < VTN , and Vi-VTP<Vo. The driver transistor MN is off, and MP is ohmic, hence Vo = Vdd.

2. Vi - VSS > VTN , Vi -VTN <Vo , and Vi-VTP<Vo. The transistor MN is saturated, and the transistor MP is
ohmic.
(β N / 2)(Vi − VSS − VTN ) 2 = β P [(VDD − Vi + VTP )(VDD − VO ) − (VDD − VO ) 2 / 2]

Solving for Vo,

VO = (Vi − VTP ) + (VDD − Vi + VTP ) 2 − β R (Vi − VSS − VTN ) 2 where β R = β N / β P

3. Vi - VSS > VTN , Vi -VTN <Vo, and Vi-VTP>Vo. The transistor MN is saturated, and the transistor MP is
also saturated.
(β N / 2)(Vi − VSS − VTN ) 2 = (β P / 2)(VDD − Vi + VTP ) 2

This equation is independent of Vo, it is used to determine the operating point Vbias of the inverter. This
corresponds to the input voltage Vi when the output voltage Vo=(VDD+ VSS) /2=(2.5-2.5)/2 = 0..

VDD + VTP + β R (VSS + VTN )

Vi = Vbias =
1 + βR

4. Vi - VSS > VTN, Vi - VTN > Vo , and Vi-VTP>Vo. The transistor MN is ohmic, and the transistor MP is
saturated.
β N = [(Vi − VSS − VTN )(VO − VSS ) − (VO − VSS ) 2 / 2] = (β P / 2)(VDD − Vi + VTP ) 2
Solving for Vo,

VO = (Vi − VTN ) − (Vi − VSS − VTN ) 2 − (VDD − Vi + VTP ) 2 / β R

5. Vi - VTN > Vo , and Vi-VDD>VTP. The transistor MN is ohmic, and MP is off. Hence Vo=VSS.

*Pspice file for CMOS Inverter

*Filename=”cmos.cir”
VIN 1 0 DC 0V AC 1VOLT
VDD 3 0 DC 2.5VOLT
VSS 4 0 DC -2.5VOLT
M1 2 1 4 4 NMOS1 W=9.6U L=5.4U
M2 2 1 3 3 PMOS1 W=25.8U L=5.4U
.MODEL NMOS1 NMOS VTO=1.0 KP=40U
+ GAMMA=1.0 LAMBDA=0.02 PHI=0.6
+ TOX=0.05U LD=0.5U CJ=5E-4 CJSW=10E-10
+ U0=550 MJ=0.5 MJSW=0.5 CGSO=0.4E-9 CGDO=0.4E-9
.MODEL PMOS1 PMOS VTO=-1.0 KP=15U
+ GAMMA=0.6 LAMBDA=0.02 PHI=0.6
+ TOX=0.05U LD=0.5U CJ=5E-4 CJSW=10E-10
+ U0=200 MJ=0.5 MJSW=0.5 CGSO=0.4E-9 CGDO=0.4E-9
.DC VIN -2.5 2.5 0.05

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.TF V(2) VIN
.AC DEC 100 1HZ 100GHZ
.PROBE
.END

Figure 3. CMOS inverter transfer function and its various regions of operation

Figure 4. Cmos inverter complimentary currents

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The operating point Vbias is computed for the given example. The W/L ratio must use the Leff = L - 2 *
LD=5.4u - 2*(0.5u) = 4.4 u , for both MN and MP transistors.
K N (W / L) N (40 E - 6)(9.6u / 4.4u)
βR = βN / βP = = =1
K P (W / L) P (15E - 6)(25.8u / 4.4u)
Vbias = VSS + (VDD + VTP + β R VTN ) / (1 + β R ) = −2.5 + (2.5 − 1 + 1(1)) / (1 + 1) = 0

Av = - [gmN + gmP][RON // ROP]

where:

R ON = 1/ (λ N I DSQ )
R OP = 1/ (λ P I DSQ )
I DSQ = I N = I P = (β N / 2)(Vbias − VSS − VTN )2
g mN = 2β N I DSQ
g mP = 2β P I DSQ
For the given example:

I DSQ = (β N / 2)(Vbias − VSS − VTN )2 = (87.3E − 6 / 2)(0 − (−2.5) − 1)2 = 98.3uA

R ON = 1 / (λ N I DSQ ) = 1 / [(0.02)(98.2uA)] =.509M
R OP = 1 / (λ P I DSQ ) = 1 / [(0.02)(98.2uA)] =.509M
β N = K N (W / L)N = (40 E - 6)(9.6u / 4.4u) = 87.3 uA / V 2
β P = K P (W / L) P = (15E - 6)(25.8u / 4.4u) = 87.95 uA / V 2
g mN = 2β N I DSQ = 2(87.3E - 6)(98.2E - 6) = 130.95 umho
g mP = 2β P I DSQ = 2(87.95E - 6)(98.2E - 6) = 131.43 umho
A V = − (g mN + gmP )(R ON / / R OP ) = − (130.95 + 131.43)E - 6(.509M / /.509M) = 66.77

The low frequency input resistance Rin = ∞ , since the input is capacitive. The output resistance
Rout=(RON//ROP)=.2545M, see Figure 1(b). These calculations agree well with Pspice simulation results of:

**** SMALL-SIGNAL CHARACTERISTICS

V(2)/VIN = -7.000E+01

OUTPUT RESISTANCE AT V(2) = 2.536E+05

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3. High Frequency Small Signal Equivalent Circuit

VDD

C gs2
M2

Cdb2
Cgd2

Vi Vo
Cgd1 Cdb1
CL

M1

C gs1

VSS

Figure 5. Cmos inverter parasitic capacitances

Figure 5 shows all the parasitic capacitances in the common source amplifier. Figure 3 shows the
high frequency small signal equivalent circuit of the common source amplifier circuit. Comparing Figure
3(b) and 3(c) one obtains:

V1 = VS = Vi = Vgs1 ; V2 = Vo

The current equation is:

I1 = s (C gs1 + C gs2 )V1 + s (C gd1 + C gd2 )(V1 − V2 ) = s (C gs1 + C gs2 + C gd1 + C gd2 )V1 − s (C gd1 + C gd2 )V2
I 2 = (g m1 + g m2 )V1 + s (C gd1 + C gd2 )(V2 − V1 ) + (g ds1 + g ds2 + sC o )V2
= [g m1 + g m2 − s (C gd1 + C gd2 )]V1 + [g ds1 + g ds2 + s (C gd1 + C gd2 + C o )]V2

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Cgd1+C gd2
G1 D1 D2

+

Cgs1 +C gs2

gds1 +g ds2
+ +
VS Vo
Vi
Cdb1 Cdb2 CL
-
S1 S2
(a)

Cgd1+ Cgd2
G1 D1 D2

(g m1+g m2)v gs1

+
Cgs1 +C gs2

g ds1 +g ds2
+ +
VS Vi Vo
Cout
-
S1 S2
Cout=Cdb1 +Cdb2 +CL

(b)

I2
+
+
VS V1 Y V2

(c)

 s (C gs1 + C gs2 + C gd1 + C gd2 ) − s (C gd1 + C gd2 ) 

Y = 
 g m1 + g m2 − s (C gd1 + C gd2 ) g ds1 + g ds2 + s (C gd1 + C gd2 + C o )

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detY = s (C gs1 + C gs2 + C gd1 + C gd2 )[g ds1 + g ds2 + s (C gd1 + C gd2 + C o )] +
s (C gd1 + C gd2 )[g m1 + g m2 − s (C gd1 + C gd2 )]
= s[(g ds1 + g ds2 )(C gs1 + C gs2 ) + (g ds1 + g ds2 )(C gd1 + C gd2 ) + (g m1 + g m2 )(C gd1 + C gd2 )] +
s 2 [(C gs1 + C gs2 )(C gd1 + C gd2 ) + (C gs1 + C gs2 )C o + (C gd1 + C gd2 )C o ]

The overall voltage gain is:

V2 y 21 g m1 + g m2 − s (C gd1 + C gd2 )
AV = =− =−
V1 y 22 + YL g ds1 + g ds2 + s (C gd1 + C gd2 + C o )
 C + C gd2   s 
 1 − s gd1  1− 
g m1 + g m2  g m1 + g m2   z1 
=-   = − A V0 
g ds1 + g ds2 C + C gd2 + C o s 
 1 + s gd1  1− 
 g ds1 + g ds2   p1 
where :
1
A V0 = −(g m1 + g m2 )R out ; R out =
g ds1 + g ds2
g m1 + g m2
z1 =
C gd1 + C gd2
1
p1 = w BW = - ; C out = C gd1 + C gd2 + C o = C gd1 + C gd2 + C db1 +C db2 +C L
R out C out
 1  g m1 + g m2
w GBW = A V0 w BW = (- (g m1 + g m2 )R out ) −  =
 R out C out  C out

That is, the wGBW is directly proportional to the transconductance of the driver transistor and inversely
proportional to the total output capacitance. The Bode Plot is shown below:

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The phase margin PM is the distance of the phase angle at the unity gain frequency with respect to –180 (in
the non-inverting amplifier case) or with respect to 0 (in the inverting amplifier case). In our case this is
with respect to 0. That is, the phase angle of the transfer function A(s) at the unity gain frequency or the
gain bandwidth frequency is also the phase margin, PM. This is obtained as follows:

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s
A 0 (1 − )
A(s) = z
s
(1 + )
p1
jw GBW jw GBW
A 0 (1 − ) A 0 (1 − )
A(jw GBW ) = z = z
jw GBW jw GBW
(1 + ) (1 + )
p1 p1
jw GBW
A 0 (1 − )
≈ z ; since w GBW >> p1
jw GBW
( )
p1
jw GBW jw
∠A(jw GBW ) = ∠A 0 + ∠(1 − ) − ∠( GBW )
z p1
 - w GBW 
= 180 + tan -1   − 90 = PM
 z 
w 
= 180 − tan -1  GBW  − 90 = PM
 z 
w 
PM = 90 − tan -1  GBW 
 z 

In the above analysis, the phase angle contribution of the zero, z, is negative because it is a RHP zero.
This is known as a non-minimum phase transfer function. This negative contribution causes the amplifier
to be potentially unstable. The phase angle dynamic range of the amplifier with first order pole and a zero
at the RHP is 180° rather than 0° if the zero is at LHP.

Without specifying the area and perimeter of the source and drain, only Cgs and Cgd are
calculated by Pspice. From the common source experiment the parasitic capacitances had been determined.
These are used to calculate the terminal capacitances for cmos inverter.

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C O = C gd1 + C gd2 = 3.84 + 10.32 = 14.16fF
Pspice extracted parameters :
A V = A V0 − 3 f BW = 44.212M
AV = 0 f GBW = ∞ = graph asymptotic to 0db
PM = 0
Comparing with theoretical calculation :

1 1
w BW = = = .2775E9
R O C O (.2545E6)(14.16E − 15)
w BW .2775E9
f BW = = = 44.186M
2π 2π
g + g m2 (130.95 + 131.43)E − 6
w GBW = m1 = = 18.53E9 = A VO w BW
CO 14.16E - 15
w GBW 18.53E9
f GBW = = = 2.95G
2π 2π
g + g m2 (130.95 + 131.43)E − 6
z 1 = m1 = = 18.53E9 = w GBW
C gd1 + C gd2 CO
z1
f Z1 = = 2.95G = f GBW

w 
PM = 90 − tan -1  GBW  = 90 − tan -1 (1) = 45
 z 

The discrepancy of the PM calculation is the result of zero occurring at wGBW . This causes the
slope of bode plot to decrease to zero db/dec prior to intersecting the zero db line. As a result, the actual
wGBW occurs at ∞ rather than at AVO*wBW and PM=0.

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