Documentos de Académico
Documentos de Profesional
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College of Engineering
Electrical department
Prepared by
Ahmed Sami Anter
Supervised by
principle of Operation
The principle of single-phase inverters [1] can be explained with Figure
6.2a. The inverter circuit consists of two choppers. When only transistor
Q1 is turned on for a time T0/2, the instantaneous voltage across the load
v0 is Vs/2. If only transistor Q2 is turned on for a time T0/2, -Vs/2
appears across the load. The logic circuit should be
the waveforms for the output voltage and transistor currents with a
resistive load. It should be noted that the phase shift is _1 = 0 for a
resistive load. This inverter requires a three-wire dc source, and when a
transistor is off, its reverse voltage is Vs instead of Vs/2. This inverter is
known as a half-bridge inverter. The root-mean-square (rms) output
voltage can be found from designed such that Q1 and Q2 are not turned
on at the same time. Figure 6.2b shows
180-Degree Conduction
Each transistor conducts for 180°. Three transistors remain on at any
instant of time .When transistor Q1 is switched on, terminal a is
connected to the positive terminal of the dc input voltage. When transistor
Q4 is switched on, terminal a is brought to the negative terminal of the dc
source. There are six modes of operation in a cycle and the duration of
each mode is 60°. The transistors are numbered in the sequence of gating
the transistors (e.g., 123, 234, 345, 456, 561, and 612). The gating signals
shown in Figure 6.6b are shifted from each other by 60° to obtain three-
phase balanced (fundamental) voltages .The load may be connected in Y
or delta as shown in Figure 6.7. The switches of any leg of the inverter
(S1 and S4, S3 and S6, or S5 and S2) cannot be switched on
simultaneously; this would result in a short circuit across the dc-link
voltage supply .Similarly, to avoid undefined states and thus undefined ac
output line voltages, thes witches of any leg of the inverter cannot be
switched off simultaneously; this can result in voltages that depend on the
respective line current polarity .Table 6.2 shows eight valid switch states.
Transistors Q1, Q6 in Figure 6.5a act as the switching device srespective
lIf two switches: one upper and one lower conduct at the same time such
that the output voltage is {Vs, the switch state is 1,whereas if these
switches are off at the same time, the switch state is 0. States 1 to
6produce nonzero output voltages. States 7 and 8 produce zero line
voltages and the line currents freewheel through either the upper or the
lower freewheeling diodes .To generate a given voltage waveform, the
inverter moves from one state to another .Thus, the resulting ac output
line voltages are built up of discrete values of voltages of Vs, 0, and -Vs.
To generate the given waveform, the selection of the states is usually
done by a modulating technique that should assure the use of only the
valid states.
120-Degree Conduction
In this type of control, each transistor conducts for 120°. Only two
transistors remain on at any instant of time. The gating signals are shown
in Figure 6.10. The conduction sequence of transistors is 61, 12, 23, 34,
45, 56, 61. There are three modes of operation in
sinusoidal Pulse-Width Modulation
Since the desired output voltage is a sine wave, a reference sinusoidal
signal is used as the reference signal. Instead of maintaining the width
of all pulses the same as in the case of multiple-pulse modulation, the
width of each pulse is varied in proportion to the amplitude of a sine
wave evaluated at the center of the same pulse [2]. The DF and LOH
are reduced significantly. The gating signals as shown in Figure6.14a
are generated by comparing a sinusoidal reference signal with a
triangular carrier wave of frequency fc. This sinusoidal pulse-width
modulation (SPWM) is commonly used in industrial applications. The
frequency of reference signal fr determines the inverter output
frequency fo; and its peak amplitude Ar controls the modulation index
M, and then in turn the rms output voltage Vo. Comparing the
bidirectional carrier signal v cr with two sinusoidal reference signals
vr and r shown in Figure 6.14a produces gating signals g1 and g4,
respectively, as shown in Figure 6.14b. The output voltage is v=0
Vs1g1 - g42. However, g1 and g4 cannot be released at the same time.
The number of pulses per half-cycle depends on the carrier frequency.
Within the constraint that two transistors of the same arm (Q1 and Q4)
cannot conduct at the same time, the instantaneous output voltage is
shown in Figure 6.14c. The same gating signals can be generated by
using unidirectional triangular carrier wave as shown in Figure 6.14d.
Itis easier to implement this method and is preferable. The gating
signal g1, which is the
Sinusoidal PWM
The generations of gating signals with sinusoidal PWM are shown in
Figure 6.20a.There are three sinusoidal reference waves (vra, v
rb, and vrc ) each shifted by 120°. A carrier wave is compared with the
reference signal corresponding to a phase to generate
the gating signals for that phase [10]. Comparing the carrier signal vcr
with the reference phases vra, vrb, and vrc produces g1, g3, and g5,
respectively, as shown in Figure 6.20b.The operation of switches Q1 to
Q6 in Figure 6.6a is determined by comparing the
modulating (or reference) sine waves with the triangular carrier wave.
When vra, 7 vcr,the upper switch Q1 in inverter leg ‘a’ is turned on. The
lower switch Q4 operates in a complementary manner and thus it is
switched off. Thus, the gate signals g2, g4, and g6 are complements of
g1, g3, and g5, respectively, as shown in Figure 6.20b. The phase
voltages as shown in Figure 6.20c for lines a and b are van = VS g1 and
vbn = VS g3. The instantaneous line-to-line output voltage is vab =Vs1g1
- g32. The output voltage, as shown in Figure 6.20c, is generated by
eliminating the condition that two switching devices
in the same arm cannot conduct at the same time. The fundamental
component of the line–line voltage vab as shown in Figure 6.20d is
denoted as vab1.