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LED TV
SERVICE MANUAL
CHASSIS : LD59R / LD5ZR

MODEL : 43/49UF640* 43/49UF640*-ZA

CAUTION
BEFORE SERVICING THE CHASSIS,
READ THE SAFETY PRECAUTIONS IN THIS MANUAL.

P/NO : MFL69305903 (1506-REV00) Printed in Korea


CONTENTS

CONTENTS ............................................................................................... 2

SAFETY PRECAUTIONS ......................................................................... 3

SERVICING PRECAUTIONS..................................................................... 4

SPECIFICATION........................................................................................ 6

ADJUSTMENT INSTRUCTION............................................................... 15

BLOCK DIAGRAM................................................................................... 21

EXPLODED VIEW ................................................................................... 30

SCHEMATIC CIRCUIT DIAGRAM ............................................ APPENDIX

TROUBLE SHOOTING GUIDE ................................................. APPENDIX

Copyright © LG Electronics. Inc. All rights reserved. -2- LGE Internal Use Only
Only for training and service purposes
SAFETY PRECAUTIONS

IMPORTANT SAFETY NOTICE


Many electrical and mechanical parts in this chassis have special safety-related characteristics. These parts are identified by in the
Schematic Diagram and Exploded View.
It is essential that these special safety parts should be replaced with the same components as recommended in this manual to prevent
Shock, Fire, or other Hazards.
Do not modify the original design without permission of manufacturer.

General Guidance Leakage Current Hot Check (See below Figure)


Plug the AC cord directly into the AC outlet.
An isolation Transformer should always be used during the
servicing of a receiver whose chassis is not isolated from the AC Do not use a line Isolation Transformer during this check.
power line. Use a transformer of adequate power rating as this Connect 1.5 K / 10 watt resistor in parallel with a 0.15 uF capacitor
protects the technician from accidents resulting in personal injury between a known good earth ground (Water Pipe, Conduit, etc.)
from electrical shocks. and the exposed metallic parts.
Measure the AC voltage across the resistor using AC voltmeter
It will also protect the receiver and it's components from being with 1000 ohms/volt or more sensitivity.
damaged by accidental shorts of the circuitry that may be Reverse plug the AC cord into the AC outlet and repeat AC voltage
inadvertently introduced during the service operation. measurements for each exposed metallic part. Any voltage
measured must not exceed 0.75 volt RMS which is corresponds to
If any fuse (or Fusible Resistor) in this TV receiver is blown, 0.5 mA.
replace it with the specified. In case any measurement is out of the limits specified, there is
possibility of shock hazard and the set must be checked and
When replacing a high wattage resistor (Oxide Metal Film Resistor, repaired before it is returned to the customer.
over 1 W), keep the resistor 10 mm away from PCB.
Leakage Current Hot Check circuit
Keep wires away from high voltage or high temperature parts.

Before returning the receiver to the customer,

always perform an AC leakage current check on the exposed


metallic parts of the cabinet, such as antennas, terminals, etc., to
be sure the set is safe to operate without damage of electrical
shock.

Leakage Current Cold Check(Antenna Cold Check)


With the instrument AC plug removed from AC source, connect an
electrical jumper across the two AC plug prongs. Place the AC
switch in the on position, connect one lead of ohm-meter to the AC
plug prongs tied together and touch other ohm-meter lead in turn to
each exposed metallic parts such as antenna terminals, phone
jacks, etc.
If the exposed metallic part has a return path to the chassis, the
measured resistance should be between 1 MΩ and 5.2 MΩ.
When the exposed metal has no return path to the chassis the
reading must be infinite.
An other abnormality exists that must be corrected before the
receiver is returned to the customer.

Copyright © LG Electronics. Inc. All rights reserved. -3- LGE Internal Use Only
Only for training and service purposes
SERVICING PRECAUTIONS
CAUTION: Before servicing receivers covered by this service 2. After removing an electrical assembly equipped with ES
manual and its supplements and addenda, read and follow the devices, place the assembly on a conductive surface such as
SAFETY PRECAUTIONS on page 3 of this publication. aluminum foil, to prevent electrostatic charge buildup or expo-
NOTE: If unforeseen circumstances create conflict between the sure of the assembly.
following servicing precautions and any of the safety precautions 3. Use only a grounded-tip soldering iron to solder or unsolder
on page 3 of this publication, always follow the safety precau- ES devices.
tions. Remember: Safety First. 4. Use only an anti-static type solder removal device. Some sol-
der removal devices not classified as “anti-static” can generate
General Servicing Precautions electrical charges sufficient to damage ES devices.
1. Always unplug the receiver AC power cord from the AC power 5. Do not use freon-propelled chemicals. These can generate
source before; electrical charges sufficient to damage ES devices.
a. Removing or reinstalling any component, circuit board 6. Do not remove a replacement ES device from its protective
module or any other receiver assembly. package until immediately before you are ready to install it.
b. Disconnecting or reconnecting any receiver electrical plug (Most replacement ES devices are packaged with leads elec-
or other electrical connection. trically shorted together by conductive foam, aluminum foil or
c. Connecting a test substitute in parallel with an electrolytic comparable conductive material).
capacitor in the receiver. 7. Immediately before removing the protective material from the
CAUTION: A wrong part substitution or incorrect polarity leads of a replacement ES device, touch the protective mate-
installation of electrolytic capacitors may result in an explo- rial to the chassis or circuit assembly into which the device will
sion hazard. be installed.
2. Test high voltage only by measuring it with an appropriate CAUTION: Be sure no power is applied to the chassis or cir-
high voltage meter or other voltage measuring device (DVM, cuit, and observe all other safety precautions.
FETVOM, etc) equipped with a suitable high voltage probe. 8. Minimize bodily motions when handling unpackaged replace-
Do not test high voltage by "drawing an arc". ment ES devices. (Otherwise harmless motion such as the
3. Do not spray chemicals on or near this receiver or any of its brushing together of your clothes fabric or the lifting of your
assemblies. foot from a carpeted floor can generate static electricity suf-
4. Unless specified otherwise in this service manual, clean ficient to damage an ES device.)
electrical contacts only by applying the following mixture to the
contacts with a pipe cleaner, cotton-tipped stick or comparable General Soldering Guidelines
non-abrasive applicator; 10 % (by volume) Acetone and 90 % 1. Use a grounded-tip, low-wattage soldering iron and appropri-
(by volume) isopropyl alcohol (90 % - 99 % strength) ate tip size and shape that will maintain tip temperature within
CAUTION: This is a flammable mixture. the range or 500 °F to 600 °F.
Unless specified otherwise in this service manual, lubrication 2. Use an appropriate gauge of RMA resin-core solder composed
of contacts in not required. of 60 parts tin/40 parts lead.
5. Do not defeat any plug/socket B+ voltage interlocks with which 3. Keep the soldering iron tip clean and well tinned.
receivers covered by this service manual might be equipped. 4. Thoroughly clean the surfaces to be soldered. Use a mall wire-
6. Do not apply AC power to this instrument and/or any of its bristle (0.5 inch, or 1.25 cm) brush with a metal handle.
electrical assemblies unless all solid-state device heat sinks Do not use freon-propelled spray-on cleaners.
are correctly installed. 5. Use the following unsoldering technique
7. Always connect the test receiver ground lead to the receiver a. Allow the soldering iron tip to reach normal temperature.
chassis ground before connecting the test receiver positive (500 °F to 600 °F)
lead. b. Heat the component lead until the solder melts.
Always remove the test receiver ground lead last. c. Quickly draw the melted solder with an anti-static, suction-
8. Use with this receiver only the test fixtures specified in this type solder removal device or with solder braid.
service manual. CAUTION: Work quickly to avoid overheating the circuit
CAUTION: Do not connect the test fixture ground strap to any board printed foil.
heat sink in this receiver. 6. Use the following soldering technique.
a. Allow the soldering iron tip to reach a normal temperature
Electrostatically Sensitive (ES) Devices (500 °F to 600 °F)
Some semiconductor (solid-state) devices can be damaged eas- b. First, hold the soldering iron tip and solder the strand
ily by static electricity. Such components commonly are called against the component lead until the solder melts.
Electrostatically Sensitive (ES) Devices. Examples of typical ES c. Quickly move the soldering iron tip to the junction of the
devices are integrated circuits and some field-effect transistors component lead and the printed circuit foil, and hold it there
and semiconductor “chip” components. The following techniques only until the solder flows onto and around both the compo-
should be used to help reduce the incidence of component dam- nent lead and the foil.
age caused by static by static electricity. CAUTION: Work quickly to avoid overheating the circuit
1. Immediately before handling any semiconductor component or board printed foil.
semiconductor-equipped assembly, drain off any electrostatic d. Closely inspect the solder area and remove any excess or
charge on your body by touching a known earth ground. Alter- splashed solder with a small wire-bristle brush.
natively, obtain and wear a commercially available discharg-
ing wrist strap device, which should be removed to prevent
potential shock reasons prior to applying power to the unit
under test.

Copyright © LG Electronics. Inc. All rights reserved. -4- LGE Internal Use Only
Only for training and service purposes
IC Remove/Replacement 3. Solder the connections.
Some chassis circuit boards have slotted holes (oblong) through CAUTION: Maintain original spacing between the replaced
which the IC leads are inserted and then bent flat against the cir- component and adjacent components and the circuit board to
cuit foil. When holes are the slotted type, the following technique prevent excessive component temperatures.
should be used to remove and replace the IC. When working with
boards using the familiar round hole, use the standard technique Circuit Board Foil Repair
as outlined in paragraphs 5 and 6 above. Excessive heat applied to the copper foil of any printed circuit
board will weaken the adhesive that bonds the foil to the circuit
Removal board causing the foil to separate from or "lift-off" the board. The
1. Desolder and straighten each IC lead in one operation by following guidelines and procedures should be followed when-
gently prying up on the lead with the soldering iron tip as the ever this condition is encountered.
solder melts.
2. Draw away the melted solder with an anti-static suction-type At IC Connections
solder removal device (or with solder braid) before removing To repair a defective copper pattern at IC connections use the
the IC. following procedure to install a jumper wire on the copper pattern
Replacement side of the circuit board. (Use this technique only on IC connec-
1. Carefully insert the replacement IC in the circuit board. tions).
2. Carefully bend each IC lead against the circuit foil pad and
solder it. 1. Carefully remove the damaged copper pattern with a sharp
3. Clean the soldered areas with a small wire-bristle brush. knife. (Remove only as much copper as absolutely necessary).
(It is not necessary to reapply acrylic coating to the areas). 2. carefully scratch away the solder resist and acrylic coating (if
used) from the end of the remaining copper pattern.
"Small-Signal" Discrete Transistor 3. Bend a small "U" in one end of a small gauge jumper wire and
Removal/Replacement carefully crimp it around the IC pin. Solder the IC connection.
1. Remove the defective transistor by clipping its leads as close 4. Route the jumper wire along the path of the out-away copper
as possible to the component body. pattern and let it overlap the previously scraped end of the
2. Bend into a "U" shape the end of each of three leads remain- good copper pattern. Solder the overlapped area and clip off
ing on the circuit board. any excess jumper wire.
3. Bend into a "U" shape the replacement transistor leads.
4. Connect the replacement transistor leads to the corresponding At Other Connections
leads extending from the circuit board and crimp the "U" with Use the following technique to repair the defective copper pattern
long nose pliers to insure metal to metal contact then solder at connections other than IC Pins. This technique involves the
each connection. installation of a jumper wire on the component side of the circuit
board.
Power Output, Transistor Device
Removal/Replacement 1. Remove the defective copper pattern with a sharp knife.
1. Heat and remove all solder from around the transistor leads. Remove at least 1/4 inch of copper, to ensure that a hazardous
2. Remove the heat sink mounting screw (if so equipped). condition will not exist if the jumper wire opens.
3. Carefully remove the transistor from the heat sink of the circuit 2. Trace along the copper pattern from both sides of the pattern
board. break and locate the nearest component that is directly con-
4. Insert new transistor in the circuit board. nected to the affected copper pattern.
5. Solder each transistor lead, and clip off excess lead. 3. Connect insulated 20-gauge jumper wire from the lead of the
6. Replace heat sink. nearest component on one side of the pattern break to the
lead of the nearest component on the other side.
Diode Removal/Replacement Carefully crimp and solder the connections.
1. Remove defective diode by clipping its leads as close as pos- CAUTION: Be sure the insulated jumper wire is dressed so the
sible to diode body. it does not touch components or sharp edges.
2. Bend the two remaining leads perpendicular y to the circuit
board.
3. Observing diode polarity, wrap each lead of the new diode
around the corresponding lead on the circuit board.
4. Securely crimp each connection and solder it.
5. Inspect (on the circuit board copper side) the solder joints of
the two "original" leads. If they are not shiny, reheat them and
if necessary, apply additional solder.

Fuse and Conventional Resistor


Removal/Replacement
1. Clip each fuse or resistor lead at top of the circuit board hollow
stake.
2. Securely crimp the leads of replacement component around
notch at stake top.

Copyright © LG Electronics. Inc. All rights reserved. -5- LGE Internal Use Only
Only for training and service purposes
SPECIFICATION
NOTE : Specifications and others are subject to change without notice for improvement.

1. Application range 3. Test method


This specification is applied to the LED TV used LD59R / 1) Performance: LGE TV test method followed
LD5ZR chassis. 2) Demanded other specification
- Safety : CE, IEC specification
- EMC : CE, IEC specification
2. Requirement for Test
Each part is tested as below without special appointment.

1) Temperature: 25 °C ± 5 °C(77 °F ± 9 °F), CST: 40 °C ± 5 °C


2) Relative Humidity: 65 % ± 10 %
3) Power Voltage
: Standard input voltage (AC 100-240 V~, 50/60 Hz)
* Standard Voltage of each products is marked by models.
4) Specification and performance of each parts are followed
each drawing and specification by part number in
accordance with BOM.
5) The receiver must be operated for about 20 minutes prior to
the adjustment.

4. Model General Specification


No. Item Specification Remarks
DTV & Analog (Total 37 countries)

DTV (MPEG2/4, DVB-T) : 26 countrie


Germany, Netherland, Switzerland, Hungary, Austria, Slovenia, Bulgaria,
France, Spain, Belgium, Luxemburg, Greece, Czech, Turkey, Morocco,
Ireland, Latvia, Estonia, Lithuania, Poland, Portugal, Romania, Albania,
Bosnia, Slovakia, Belarus

DTV (MPEG2/4, DVB-T2) :11 countries


UK(Ireland), Sweden, Denmark, Finland, Norway, Ukraine, Kazakhstan,
Russia, Italy, Croatia, Serbia

DTV (MPEG2/4, DVB-C) : 37 countries


Germany, Netherland, Switzerland, Hungary, Austria, Slovenia, Bulgaria,
France, Spain, Italy, Belgium, Russia, Luxemburg, Greece, Czech, Cro-
atia, Turkey, Morocco, Ireland, Latvia, Estonia, Lithuania, Poland, Portu-
gal, Romania, Albania, Bosnia, Serbia, Slovakia, Belarus, UK, Sweden,
Denmark, Finland, Norway, Ukraine, Kazakhstan
1 Market EU/CIS(PAL Market-37Countries)
DTV (MPEG2/4,DVB-S) : 37 countries
Germany, Netherland, Switzerland, Hungary, Austria, Slovenia, Bulgaria,
France, Spain,Belgium, Luxemburg, Greece, Czech, Turkey, Morocco,
Ireland, Latvia, Estonia, Lithuania, Poland, Portugal, Romania, Albania,
Bosnia, Slovakia, Belarus, UK(Ireland), Sweden, Denmark, Finland,
Norway, Ukraine, Kazakhstan,Russia, Italy, Croatia, Serbia

Supported satellite : 35 satellites


ABS1 75.0E, AMOS 4.0W, ASIASAT3S 105.5E, ASTRA 19.2E, ASTRA
23.5E, ASTRA 28.2E, ASTRA 4.8E, ATLANTIC BIRD2 8.0W, ATLANTIC
BIRD3 5.0W, BADR 26.0E, DIRECTV-1R 56.0E, EUROBIRD 9A 9.0E,
EUROBIRD3 33.0E, EUTELSAT 36 A/B 36.0E,EUTELSAT W2A 10.0E,
EUTELSAT W3A 7.0E, EUTELSAT7WA 7.3WEUTELSAT 16.0E, EX-
PRESS AM1 40.0E, EXPRESS AM3 140.0E, EXPRESS AM33 96.5E,
HELLASSAT 39.0E, HISPASAT 1CDE 30.0WHOTBIRD 13.0E, INTEL-
SAT10&7 68.5E, INTELSAT15 85.2E, INTELSAT1R 50.0W, INTEL-
SAT903 33.5W, INTELSAT904 60.0E, NILESAT 7.0W, NSS12 57.0E,
THOR 0.8W, TURKSAT 42.0E,YAMAL201 90.0E, OTHER

Copyright © LG Electronics. Inc. All rights reserved. -6- LGE Internal Use Only
Only for training and service purposes
No. Item Specification Remarks
(1) PAL/SECAM B/G/I/D/K, SECAM L/L’
2 Broadcasting system
(2) DVB-T/T2, C, S/S2
(1) Digital TV
- VHF, UHF
- C-Band, Ku-Band
(2) Analogue TV
3 Program coverage
-VHF : E2 to E12
-UHF : E21 to E69
-CATV : S1 to S20
-HYPER : S21 to S47
► DVB-T
- Guard Interval(Bitrate_Mbit/s)
1/4, 1/8, 1/16, 1/32
- Modulation : Code Rate
QPSK : 1/2, 2/3, 3/4, 5/6, 7/8
16-QAM : 1/2, 2/3, 3/4, 5/6, 7/8
64-QAM : 1/2, 2/3, 3/4, 5/6, 7/8

► DVB-T2
- Guard Interval(Bitrate_Mbit/s)
1/4, 1/8, 1/16, 1/32, 1/128, 19/128, 19/256,
- Modulation : Code Rate
QPSK : 1/2, 2/5, 2/3, 3/4, 5/6
Analog : Upper Heterodyne
16-QAM : 1/2, 2/5, 2/3, 3/4, 5/6
4 Receiving system Digital : COFDM, QAM
64-QAM : 1/2, 2/5, 2/3, 3/4, 5/6
256-QAM : 1/2, 2/5, 2/3, 3/4, 5/6

► DVB-C
- Symbolrate : 4.0 Msymbols/s to 7.2 Msymbols/s
- Modulation : 16QAM, 64-QAM, 128-QAM and 256-QAM

► DVB-S/S2
- symbolrate :
DVB-S2 (8PSK / QPSK) : 2 ~ 45 Msymbol/s
DVB-S (QPSK) : 2 ~ 45 Msymbol/s
- viterbi
DVB-S mode : 1/2, 2/3, 3/4, 5/6, 7/8
DVB-S2 mode : 1/2, 2/3, 3/4, 3/5, 4/5, 5/6, 8/9, 9/10
5 Input Voltage AC 100 ~ 240V 50/60Hz

Copyright © LG Electronics. Inc. All rights reserved. -7- LGE Internal Use Only
Only for training and service purposes
5. External Input Format
5.1. Standard Level For Input Signal (Video, Audio, Y/C, Component)
No. Item Min Typ Max Unit
1. Video Input Level 0.9 1 1.1 Vpp
2. S Video Input Level(Y) 0.85 1 1.15 Vpp
3. S Video Input Level(C-Burst) 0.143 0.286 Vpp
4. Audio Input Level 0.4 0.5 0.6 Vrms PAL,SECAM, AV1(SCART), AV2, Component
Component Video Input Level
5. 0.6 0.7 0.8 Vpp
(Y, CB/PB, CR/PR)

5.2. 2D Mode
(1) Component (Y, CB/PB, CR/PR)
No. Resolution H-freq(kHz) V-freq(Hz) Pixel clock(MHz) Proposed
1 720*480 15.73 60 13.5135 SDTV ,DVD 480I
2 720*480 15.73 59.94 13.5 SDTV ,DVD 480I
3 720*480 31.50 60 27.027 SDTV 480P
4 720*480 31.47 59.94 27.0 SDTV 480P
5 1280*720 45.00 60.00 74.25 HDTV 720P
6 1280*720 44.96 59.94 74.176 HDTV 720P
7 1920*1080 33.75 60.00 74.25 HDTV 1080I
8 1920*1080 33.72 59.94 74.176 HDTV 1080I
9 1920*1080 67.500 60 148.50 HDTV 1080P
10 1920*1080 67.432 59.94 148.352 HDTV 1080P
11 1920*1080 27.000 24.000 74.25 HDTV 1080P
12 1920*1080 26.97 23.976 74.176 HDTV 1080P
13 1920*1080 33.75 30.000 74.25 HDTV 1080P
14 1920*1080 33.71 29.97 74.176 HDTV 1080P

Copyright © LG Electronics. Inc. All rights reserved. -8- LGE Internal Use Only
Only for training and service purposes
(2) HDMI Input(DTV)

No. Resolution H-freq(kHz) V-freq.(kHz) Pixel clock(MHz) Proposed Remarks


1 640*480 31.46 59.94 25.13 SDTV 480P
2 640*480 31.50 60.00 25.13 SDTV 480P
3 720*480 15.73 59.94 13.50 SDTV, DVD 480I(525I)
4 720*480 15.75 60.00 13.51 SDTV, DVD 480I(525I) Spec. out but display
5 720*576 15.62 50.00 13.50 SDTV, DVD 576I(625I) 50Hz
6 720*480 31.47 59.94 27.00 SDTV 480P
7 720*480 31.50 60.00 27.03 SDTV 480P
8 720*576 31.25 50.00 27.00 SDTV 576P
9 1280*720 44.96 59.94 74.18 HDTV 720P
10 1280*720 45.00 60.00 74.25 HDTV 720P
11 1280*720 37.50 50.00 74.25 HDTV 720P
12 1920*1080 28.12 50.00 74.25 HDTV 1080I
13 1920*1080 33.72 59.94 74.18 HDTV 1080I
14 1920*1080 33.75 60.00 74.25 HDTV 1080I
15 1920*1080 26.97 23.97 63.30 HDTV 1080P
16 1920*1080 27.00 24.00 63.36 HDTV 1080P
17 1920*1080 33.71 29.97 79.12 HDTV 1080P
18 1920*1080 33.75 30.00 79.20 HDTV 1080P
19 1920*1080 56.25 50.00 148.50 HDTV 1080P
20 1920*1080 67.43 59.94 148.35 HDTV 1080P
21 1920*1080 67.50 60.00 148.50 HDTV 1080P
22 3840*2160 53.95 23.98 297.00 UDTV 2160P UHD only
23 3840*2160 54.00 24.00 297.00 UDTV 2160P UHD only
24 3840*2160 56.25 25.00 297.00 UDTV 2160P UHD only
25 3840*2160 61.43 29.97 297.00 UDTV 2160P UHD only
26 3840*2160 67.50 30.00 297.00 UDTV 2160P UHD only
27 3840*2160 112.50 50.00 594.00 UDTV 2160P(DVB) UHD only(Port1)
28 3840*2160 135.00 59.94 593.41 UDTV 2160P UHD only(Port1)
29 3840*2160 135.00 60.00 594.00 UDTV 2160P UHD only(Port1)
30 4096*2160 53.95 23.98 297.00 UDTV 2160P UHD only
31 4096*2160 54.00 24.00 297.00 UDTV 2160P UHD only
32 4096*2160 56.25 25.00 297.00 UDTV 2160P UHD only
33 4096*2160 61.43 29.97 297.00 UDTV 2160P UHD only
34 4096*2160 67.50 30.00 297.00 UDTV 2160P UHD only
35 4096*2160 112.50 50.00 594.00 UDTV 2160P(DVB) UHD only(Port1)
36 4096*2160 135.00 59.94 593.41 UDTV 2160P UHD only(Port1)
37 4096*2160 135.00 60.00 594.00 UDTV 2160P UHD only(Port1)

Copyright © LG Electronics. Inc. All rights reserved. -9- LGE Internal Use Only
Only for training and service purposes
(3) HDMI Input (PC)
No. Resolution H-freq(kHz) V-freq.(kHz) Pixel clock(MHz) Proposed Remarks
1 640*350 31.46 70.09 25.17 EGA
2 720*400 31.46 70.08 28.32 DOS
3 640*480 31.46 59.94 25.17 VESA(VGA)
4 800*600 37.87 60.32 40.00 VESA(SVGA)
5 1024*768 48.36 60.00 65.00 VESA(XGA)
6 1152*864 54.34 60.05 80.00 VESA
7 1280*1024 63.98 60.02 109.00 VESA(SXGA) FHD only
8 1360*768 47.71 60.01 85.00 VESA(WXGA)
9 1920*1080 67.50 60.00 158.40 WUXGA(CEA 861D) FHD only
10 3840*2160 67.50 30.00 297.00 UDTV 2160P UHD only
11 3840*2160 56.25 25.00 297.00 UDTV 2160P UHD only
12 3840*2160 54.00 24.00 297.00 UDTV 2160P UHD only
13 4096*2160 53.95 23.97 296.703 UDTV 2160P UHD only
14 4096*2160 54.00 24.00 297.00 UDTV 2160P UHD only

Copyright © LG Electronics. Inc. All rights reserved. - 10 - LGE Internal Use Only
Only for training and service purposes
ADJUSTMENT INSTRUCTION
1. Application Range 3.2. LAN Inspection
This specification sheet is applied to all of the LED TV with 3.2.1. Equipment & Condition
LD59R / LD5ZR chassis. ▪ Each other connection to LAN Port of IP Hub and Jig

2. Designation
(1) Because this is not a hot chassis, it is not necessary to
use an isolation transformer. However, the use of isolation
transformer will help protect test instrument.
(2) Adjustment must be done in the correct order.
(3) The adjustment must be performed in the circumstance of
25 °C ± 5 °C of temperature and 65 % ± 10 % of relative
3.2.2. LAN inspection solution
▪ LAN Port connection with PCB
humidity if there is no specific designation.
▪ Network setting at MENU Mode of TV
(4) The input voltage of the receiver must keep AC 100-240
▪ setting automatic IP
V~, 50/60 Hz.
▪ Setting state confirmation
(5) The receiver must be operated for about 5 minutes prior to
- If automatic setting is finished, you confirm IP and MAC
the adjustment when module is in the circumstance of over
Address.
15 °C.

In case of keeping module is in the circumstance of 0 °C, it


should be placed in the circumstance of above 15 °C for 2
hours.

In case of keeping module is in the circumstance of below


-20 °C, it should be placed in the circumstance of above 15
°C for 3 hours.

[Caution]
When still image is displayed for a period of 20 minutes or
longer (Especially where W/B scale is strong. Digital pattern
13ch and/or Cross hatch pattern 09ch), there can some 3.2.3. WIDEVINE key Inspection
afterimage in the black level area. - Confirm key input data at the "IN START" MENU Mode.

3. Automatic Adjustment
3.1. MAC address D/L, CI+ key D/L, Widevine
key D/L, ESN D/L, HDCP2.0 D/L
Connect: USB port
Communication Prot connection
▪ Com 1,2,3,4 and 115200(Baudrate)
Mode check: Online Only
▪ C heck the test process: DETECT → MAC → ESN →
Widevine → CI → HDCP20
▪ Play: Press Enter key
▪ Result: Ready, Test, OK or NG
▪ Printer Out (MAC Address Label)

Copyright © LG Electronics. Inc. All rights reserved. - 11 - LGE Internal Use Only
Only for training and service purposes
3.3. LAN PORT INSPECTION(PING TEST) 3.5. CI+ Key checking method
Connect SET → LAN port == PC → LAN Port (Check the Section 3.1)
Check whether the key was downloaded or not at ‘In Start’
SET PC menu. (Refer to below).

3.3.1. Equipment setting


(1) Play the LAN Port Test PROGRAM.
(2) Input IP set up for an inspection to Test Program. => Check the Download to CI+ Key value in LGset.
*IP Number : 12.12.2.2 3.5.1. Check the method of CI+ Key value
(1) Check the method on Instart menu
3.3.2. LAN PORT inspection(PING TEST) (2) Check the method of RS232C Command
(1) Play the LAN Port Test Program. 1) Into the main ass’y mode(RS232: aa 00 00)
(2) Connect each other LAN Port Jack. CMD 1 CMD 2 Data 0
(3) Play Test (F9) button and confirm OK Message. A A 0 0
(4) Remove LAN cable.
2) Check the key download for transmitted command
(RS232: ci 00 10)
CMD 1 CMD 2 Data 0
C I 1 0
3) Result value
- Normally status for download : OKx
- Abnormally status for download : NGx

3.5.2. Check the method of CI+ key value(RS232)


1) Into the main ass’y mode(RS232: aa 00 00)
CMD 1 CMD 2 Data 0
3.4. Model name & Serial number Download A A 0 0
3.4.1. Model name & Serial number D/L 2) Check the mothed of CI+ key by command
▪ Press "P-ONLY" key of service remote control. (RS232: ci 00 20)
(Baud rate : 115200 bps)
▪ Connect RS-232C Signal to USB Cable to USB.
CMD 1 CMD 2 Data 0
▪ Write Serial number by use USB port. C I 2 0
▪ Must check the serial number at Instart menu.
3) Result value
i 01 OK 1d1852d21c1ed5dcx
3.4.2. Method & notice
CI+ Key Value
(1) Serial number D/L is using of scan equipment.
(2) Setting of scan equipment operated by Manufacturing
Technology Group.
(3) Serial number D/L must be conformed when it is produced 3.6. WIFI MAC ADDRESS CHECK
in production line, because serial number D/L is mandatory (1) Using RS232 Command
by D-book 4.0. H-freq(kHz) V-freq.(Hz)
Transmission [A][I][][Set ID][][20][Cr] [O][K][X] or [NG]
* Manual Download (Model Name and Serial Number)
If the TV set is downloaded by OTA or service man, sometimes
model name or serial number is initialized.(Not always) (2) Check the menu on in-start
It is impossible to download by bar code scan, so It need
Manual download.
1) Press the "Instart" key of Adjustment remote control.
2) Go to the menu "7.Model Number D/L" like below photo.
3) Input the Factory model name(ex 47LB650V-ZA) or Serial
number like photo.

4) Check the model name Instart menu. → Factory name


displayed. (ex 47LB650V-ZA)
5) C heck the Diagnostics.(DTV country only) → Buyer
model displayed. (ex 47LB650V-ZA)

Copyright © LG Electronics. Inc. All rights reserved. - 12 - LGE Internal Use Only
Only for training and service purposes
4. Manual Adjustment (1) EDID for 2D Model(UF68)
1) DTS
* ADC adjustment is not needed because of OTP(Auto ADC
adjustment) # HDMI 1(C/S : A0 C7) - HDMI UHD Deep On Case
EDID Block 0, Bytes 0-127 [00H-7FH]
0 1 2 3 4 5 6 7 8 9 A B C D E F
4.1. EDID(The
 Extended Display Identification 0 00 FF FF FF FF FF FF 00 1E 6D 01 00 01 01 01 01
Data)/DDC(Display Data Channel) download 10 01 19 01 03 80 A0 5A 78 0A EE 91 A3 54 4C 99 26
20 0F 50 54 A1 08 00 31 40 45 40 61 40 71 40 81 80
4.1.1. Overview 30 01 01 01 01 01 01 08 E8 00 30 F2 70 5A 80 B0 58
It is a VESA regulation. A PC or a MNT will display an optimal 40 8A 00 40 84 63 00 00 1E 02 3A 80 18 71 38 2D 40
resolution through information sharing without any necessity 50 58 2C 45 00 40 84 63 00 00 1E 00 00 00 FD 00 3A
of user input. It is a realization of "Plug and Play". 60 3E 1E 88 3C 00 0A 20 20 20 20 20 20 00 00 00 FC
70 00 4C 47 20 54 56 0A 20 20 20 20 20 20 20 01 A0
4.1.2. Equipment EDID Block 1, Bytes 128-255 [80H-FFH]
- Since embedded EDID data is used, EDID download JIG,
0 1 2 3 4 5 6 7 8 9 A B C D E F
HDMI cable and D-sub cable are not need. 80 02 03 47 F1 58 10 9F 04 13 05 14 03 02 12 20 21
- Adjustment remote control 90 22 15 01 60 61 5D 5E 5F 65 66 62 63 64 29 3D 06
A0 C0 15 07 50 09 57 07 6E 03 0C 00 10 00 B8 3C 20
4.1.3. Download method B0 00 80 01 02 03 04 67 D8 5D C4 01 78 80 03 E3 05
(1) Press "ADJ" key on the Adjustment remote control, then C0 C0 00 E4 0F 00 C0 18 66 21 50 B0 51 00 1B 30 40
select "12.EDID D/L", By pressing "Enter" key, enter EDID D0 70 36 00 40 84 63 00 00 1E 01 1D 00 72 51 D0 1E
E0 20 6E 28 55 00 40 84 63 00 00 1E 00 00 00 00 00
D/L menu.
F0 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 C7
For HDMI EDID
DVI-D to HDMI or HDMI to HDMI # HDMI 1(C/S : E6 1D) - HDMI UHD Deep Off Case
EDID Block 0, Bytes 0-127 [00H-7FH]
0 1 2 3 4 5 6 7 8 9 A B C D E F
0 00 FF FF FF FF FF FF 00 1E 6D 01 00 01 01 01 01
10 01 19 01 03 80 A0 5A 78 0A EE 91 A3 54 4C 99 26
20 0F 50 54 A1 08 00 31 40 45 40 61 40 71 40 81 80
30 01 01 01 01 01 01 02 3A 80 18 71 38 2D 40 58 2C
(2) S elect "Start" button by pressing "Enter" key, HDMI1/ 40 45 00 40 84 63 00 00 1E 66 21 50 B0 51 00 1B 30
HDMI2/ HDMI3/ HDMI4 are writing and display OK or NG. 50 40 70 36 00 40 84 63 00 00 1E 00 00 00 FD 00 3A
60 3E 1E 53 10 00 0A 20 20 20 20 20 20 00 00 00 FC
70 00 4C 47 20 54 56 0A 20 20 20 20 20 20 20 01 E6
4.1.4. EDID DATA
▪ Reference EDID Block 1, Bytes 128-255 [80H-FFH]
- HDMI1 ~ HDMI3 0 1 2 3 4 5 6 7 8 9 A B C D E F
- In the data of EDID, bellows may be different by Input mode. 80 02 03 38 F1 54 10 9F 04 13 05 14 03 02 12 20 21
0 1 2 3 4 5 6 7 8 9 A B C D E F 90 22 15 01 5D 5E 5F 62 63 64 29 3D 06 C0 15 07 50
0x00 00 FF FF FF FF FF FF 00 1E 6D ⓐ ⓑ A0 09 57 07 6E 03 0C 00 10 00 B8 3C 20 00 80 01 02
0x01 ⓒ 01 03 80 A0 5A 78 0A EE 91 A3 54 4C 99 26 B0 03 04 E5 0E 60 61 65 66 01 1D 80 18 71 1C 16 20
0x02 0F 50 54 A1 8 00 31 40 45 40 61 40 71 40 81 80 C0 58 2C 25 00 40 84 63 00 00 9E 01 1D 00 72 51 D0
0x03 01 01 01 01 01 01 02 3A 80 18 71 38 2D 40 58 2C D0 1E 20 6E 28 55 00 40 84 63 00 00 1E 00 00 00 00
0x04 45 00 40 84 63 00 00 1E 66 21 50 B0 51 00 1B 30
E0 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
0x05 40 70 36 00 40 84 63 00 00 1E 00 00 00 FD 00 3A
F0 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 1D
0x06 3E 1E 53 10 00 0A 20 20 20 20 20 20 ⓓ
0x07 ⓓ 01 ⓔ1
# HDMI 2(C/S : A0 B7) - HDMI UHD Deep On Case
0x00 02 03 3A F1 4E 10 9F 04 13 05 14 03 02 12 20 21
0x01 22 15 01 29 3D 06 C0 15 07 50 ⓕ EDID Block 0, Bytes 0-127 [00H-7FH]
0x02 ⓕ 0 1 2 3 4 5 6 7 8 9 A B C D E F
0x03 ⓕ 10 28 10 E3 05 03 01 02 3A 80 18 71 38 0 00 FF FF FF FF FF FF 00 1E 6D 01 00 01 01 01 01
0x04 2D 40 58 2C 45 00 40 84 63 00 00 1E 01 1D 80 18 10 01 19 01 03 80 A0 5A 78 0A EE 91 A3 54 4C 99 26
0x05 71 1C 16 20 58 2C 25 00 40 84 63 00 00 9E 01 1D 20 0F 50 54 A1 08 00 31 40 45 40 61 40 71 40 81 80
0x06 00 72 51 D0 1E 20 6E 28 55 00 40 84 63 00 00 1E
30 01 01 01 01 01 01 08 E8 00 30 F2 70 5A 80 B0 58
0x07 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ⓔ2
40 8A 00 40 84 63 00 00 1E 02 3A 80 18 71 38 2D 40
50 58 2C 45 00 40 84 63 00 00 1E 00 00 00 FD 00 3A
ⓐ Product ID
60 3E 1E 88 3C 00 0A 20 20 20 20 20 20 00 00 00 FC
ⓑ Serial No: Controlled on production line.
70 00 4C 47 20 54 56 0A 20 20 20 20 20 20 20 01 A0
ⓒ Month, Year: Controlled on production line:
ex) Monthly : ‘01’ → ‘01’, Year : ‘2015’ → ‘19’ EDID Block 1, Bytes 128-255 [80H-FFH]
ⓓ Model Name(Hex): LGTV 0 1 2 3 4 5 6 7 8 9 A B C D E F
ⓔ Checksum(LG TV): Changeable by total EDID data. 80 02 03 47 F1 58 10 9F 04 13 05 14 03 02 12 20 21
ⓕ Vendor Specific(HDMI) 90 22 15 01 60 61 5D 5E 5F 65 66 62 63 64 29 3D 06
A0 C0 15 07 50 09 57 07 6E 03 0C 00 20 00 B8 3C 20
B0 00 80 01 02 03 04 67 D8 5D C4 01 78 80 03 E3 05
C0 C0 00 E4 0F 00 C0 18 66 21 50 B0 51 00 1B 30 40
D0 70 36 00 40 84 63 00 00 1E 01 1D 00 72 51 D0 1E
E0 20 6E 28 55 00 40 84 63 00 00 1E 00 00 00 00 00
70 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 B7

Copyright © LG Electronics. Inc. All rights reserved. - 13 - LGE Internal Use Only
Only for training and service purposes
# HDMI 2(C/S : E6 0D) - HDMI UHD Deep Off Case EDID Block 1, Bytes 128-255 [80H-FFH]
EDID Block 0, Bytes 0-127 [00H-7FH] 0 1 2 3 4 5 6 7 8 9 A B C D E F
0 1 2 3 4 5 6 7 8 9 A B C D E F 80 02 03 35 F1 54 10 9F 04 13 05 14 03 02 12 20 21
0 00 FF FF FF FF FF FF 00 1E 6D 01 00 01 01 01 01 90 22 15 01 5D 5E 5F 62 63 64 26 15 07 50 09 57 07
10 01 19 01 03 80 A0 5A 78 0A EE 91 A3 54 4C 99 26 A0 6E 03 0C 00 10 00 B8 3C 20 00 80 01 02 03 04 E5
20 0F 50 54 A1 08 00 31 40 45 40 61 40 71 40 81 80 B0 0E 60 61 65 66 01 1D 80 18 71 1C 16 20 58 2C 25
30 01 01 01 01 01 01 02 3A 80 18 71 38 2D 40 58 2C C0 00 40 84 63 00 00 9E 01 1D 00 72 51 D0 1E 20 6E
40 45 00 40 84 63 00 00 1E 66 21 50 B0 51 00 1B 30 D0 28 55 00 40 84 63 00 00 1E 00 00 00 00 00 00 00
50 40 70 36 00 40 84 63 00 00 1E 00 00 00 FD 00 3A E0 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
60 3E 1E 53 10 00 0A 20 20 20 20 20 20 00 00 00 FC F0 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 26
70 00 4C 47 20 54 56 0A 20 20 20 20 20 20 20 01 E6
# HDMI 2(C/S : A0 C0) - HDMI UHD Deep On Case
EDID Block 1, Bytes 128-255 [80H-FFH] EDID Block 0, Bytes 0-127 [00H-7FH]
0 1 2 3 4 5 6 7 8 9 A B C D E F 0 1 2 3 4 5 6 7 8 9 A B C D E F
80 02 03 38 F1 54 10 9F 04 13 05 14 03 02 12 20 21 0 00 FF FF FF FF FF FF 00 1E 6D 01 00 01 01 01 01
90 22 15 01 5D 5E 5F 62 63 64 29 3D 06 C0 15 07 50 10 01 19 01 03 80 A0 5A 78 0A EE 91 A3 54 4C 99 26
A0 09 57 07 6E 03 0C 00 20 00 B8 3C 20 00 80 01 02 20 0F 50 54 A1 08 00 31 40 45 40 61 40 71 40 81 80
B0 03 04 E5 0E 60 61 65 66 01 1D 80 18 71 1C 16 20 30 01 01 01 01 01 01 08 E8 00 30 F2 70 5A 80 B0 58
C0 58 2C 25 00 40 84 63 00 00 9E 01 1D 00 72 51 D0 40 8A 00 40 84 63 00 00 1E 02 3A 80 18 71 38 2D 40
D0 1E 20 6E 28 55 00 40 84 63 00 00 1E 00 00 00 00 50 58 2C 45 00 40 84 63 00 00 1E 00 00 00 FD 00 3A
E0 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 60 3E 1E 88 3C 00 0A 20 20 20 20 20 20 00 00 00 FC
F0 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 0D 70 00 4C 47 20 54 56 0A 20 20 20 20 20 20 20 01 A0

* Checksum(HDMI 1/2) EDID Block 1, Bytes 128-255 [80H-FFH]


HDMI Deep Color On HDMI Deep Color Off 0 1 2 3 4 5 6 7 8 9 A B C D E F
Input
FFh (Checksum) FFh (Checksum) 80 02 03 44 F1 58 10 9F 04 13 05 14 03 02 12 20 21
HDMI1 A0 C7 E6 1D 90 22 15 01 60 61 5D 5E 5F 65 66 62 63 64 26 15 07
HDMI2 A0 B7 E6 0D A0 50 09 57 07 6E 03 0C 00 20 00 B8 3C 20 00 80 01
B0 02 03 04 67 D8 5D C4 01 78 80 03 E3 05 C0 00 E4
C0 0F 00 C0 18 66 21 50 B0 51 00 1B 30 40 70 36 00
2) AC3
D0 40 84 63 00 00 1E 01 1D 00 72 51 D0 1E 20 6E 28
# HDMI 1(C/S : A0 D0) - HDMI UHD Deep On Case E0 55 00 40 84 63 00 00 1E 00 00 00 00 00 00 00 00
EDID Block 0, Bytes 0-127 [00H-7FH] F0 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 C0
0 1 2 3 4 5 6 7 8 9 A B C D E F
0 00 FF FF FF FF FF FF 00 1E 6D 01 00 01 01 01 01 # HDMI 2(C/S : E6 16) - HDMI UHD Deep off Case
10 01 19 01 03 80 A0 5A 78 0A EE 91 A3 54 4C 99 26 EDID Block 0, Bytes 0-127 [00H-7FH]
20 0F 50 54 A1 08 00 31 40 45 40 61 40 71 40 81 80 0 1 2 3 4 5 6 7 8 9 A B C D E F
30 01 01 01 01 01 01 08 E8 00 30 F2 70 5A 80 B0 58 0 00 FF FF FF FF FF FF 00 1E 6D 01 00 01 01 01 01
40 8A 00 40 84 63 00 00 1E 02 3A 80 18 71 38 2D 40 10 01 19 01 03 80 A0 5A 78 0A EE 91 A3 54 4C 99 26
50 58 2C 45 00 40 84 63 00 00 1E 00 00 00 FD 00 3A 20 0F 50 54 A1 08 00 31 40 45 40 61 40 71 40 81 80
60 3E 1E 88 3C 00 0A 20 20 20 20 20 20 00 00 00 FC 30 01 01 01 01 01 01 02 3A 80 18 71 38 2D 40 58 2C
70 00 4C 47 20 54 56 0A 20 20 20 20 20 20 20 01 A0 40 45 00 40 84 63 00 00 1E 66 21 50 B0 51 00 1B 30
50 40 70 36 00 40 84 63 00 00 1E 00 00 00 FD 00 3A
EDID Block 1, Bytes 128-255 [80H-FFH] 60 3E 1E 53 10 00 0A 20 20 20 20 20 20 00 00 00 FC
0 1 2 3 4 5 6 7 8 9 A B C D E F 70 00 4C 47 20 54 56 0A 20 20 20 20 20 20 20 01 E6
80 02 03 44 F1 58 10 9F 04 13 05 14 03 02 12 20 21
90 22 15 01 60 61 5D 5E 5F 65 66 62 63 64 26 15 07 EDID Block 1, Bytes 128-255 [80H-FFH]
A0 50 09 57 07 6E 03 0C 00 10 00 B8 3C 20 00 80 01 0 1 2 3 4 5 6 7 8 9 A B C D E F
B0 02 03 04 67 D8 5D C4 01 78 80 03 E3 05 C0 00 E4 80 02 03 35 F1 54 10 9F 04 13 05 14 03 02 12 20 21
C0 0F 00 C0 18 66 21 50 B0 51 00 1B 30 40 70 36 00 90 22 15 01 5D 5E 5F 62 63 64 26 15 07 50 09 57 07
D0 40 84 63 00 00 1E 01 1D 00 72 51 D0 1E 20 6E 28 A0 6E 03 0C 00 20 00 B8 3C 20 00 80 01 02 03 04 E5
E0 55 00 40 84 63 00 00 1E 00 00 00 00 00 00 00 00 B0 0E 60 61 65 66 01 1D 80 18 71 1C 16 20 58 2C 25
F0 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 D0 C0 00 40 84 63 00 00 9E 01 1D 00 72 51 D0 1E 20 6E
D0 28 55 00 40 84 63 00 00 1E 00 00 00 00 00 00 00
# HDMI 1(C/S : E6 26) - HDMI UHD Deep Off Case E0 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
EDID Block 0, Bytes 0-127 [00H-7FH] F0 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 16
0 1 2 3 4 5 6 7 8 9 A B C D E F
0 00 FF FF FF FF FF FF 00 1E 6D 01 00 01 01 01 01 * Checksum(HDMI 1/2)
10 01 19 01 03 80 A0 5A 78 0A EE 91 A3 54 4C 99 26 HDMI Deep Color On HDMI Deep Color Off
Input
20 0F 50 54 A1 08 00 31 40 45 40 61 40 71 40 81 80 FFh (Checksum) FFh (Checksum)
30 01 01 01 01 01 01 02 3A 80 18 71 38 2D 40 58 2C HDMI1 A0 D0 E6 26
40 45 00 40 84 63 00 00 1E 66 21 50 B0 51 00 1B 30 HDMI2 A0 C0 E6 16
50 40 70 36 00 40 84 63 00 00 1E 00 00 00 FD 00 3A
60 3E 1E 53 10 00 0A 20 20 20 20 20 20 00 00 00 FC
70 00 4C 47 20 54 56 0A 20 20 20 20 20 20 20 01 E6

Copyright © LG Electronics. Inc. All rights reserved. - 14 - LGE Internal Use Only
Only for training and service purposes
3) PCM # HDMI 2(C/S : E6 88) - HDMI UHD Deep off case
# HDMI 1(C/S : A0 42) - HDMI UHD Deep On Case EDID Block 0, Bytes 0-127 [00H-7FH]
EDID Block 0, Bytes 0-127 [00H-7FH] 0 1 2 3 4 5 6 7 8 9 A B C D E F
0 1 2 3 4 5 6 7 8 9 A B C D E F 00 00 FF FF FF FF FF FF 00 1E 6D 01 00 01 01 01 01
0 00 FF FF FF FF FF FF 00 1E 6D 01 00 01 01 01 01 01 01 19 01 03 80 A0 5A 78 0A EE 91 A3 54 4C 99 26
10 01 19 01 03 80 A0 5A 78 0A EE 91 A3 54 4C 99 26 0F 0F 50 54 A1 08 00 31 40 45 40 61 40 71 40 81 80
20 0F 50 54 A1 08 00 31 40 45 40 61 40 71 40 81 80 01 01 01 01 01 01 01 02 3A 80 18 71 38 2D 40 58 2C
30 01 01 01 01 01 01 08 E8 00 30 F2 70 5A 80 B0 58 45 45 00 40 84 63 00 00 1E 66 21 50 B0 51 00 1B 30
40 8A 00 40 84 63 00 00 1E 02 3A 80 18 71 38 2D 40 40 40 70 36 00 40 84 63 00 00 1E 00 00 00 FD 00 3A
50 58 2C 45 00 40 84 63 00 00 1E 00 00 00 FD 00 3A 3E 3E 1E 53 10 00 0A 20 20 20 20 20 20 00 00 00 FC
60 3E 1E 88 3C 00 0A 20 20 20 20 20 20 00 00 00 FC 00 00 4C 47 20 54 56 0A 20 20 20 20 20 20 20 01 E6
70 00 4C 47 20 54 56 0A 20 20 20 20 20 20 20 01 A0
EDID Block 1, Bytes 128-255 [80H-FFH]
EDID Block 1, Bytes 128-255 [80H-FFH] 0 1 2 3 4 5 6 7 8 9 A B C D E F
0 1 2 3 4 5 6 7 8 9 A B C D E F 80 02 03 32 F1 54 10 9F 04 13 05 14 03 02 12 20 21
80 02 03 41 F1 58 10 9F 04 13 05 14 03 02 12 20 21 90 22 15 01 5D 5E 5F 62 63 64 23 09 57 07 6E 03 0C
90 22 15 01 60 61 5D 5E 5F 65 66 62 63 64 23 09 57 A0 00 20 00 B8 3C 20 00 80 01 02 03 04 E5 0E 60 61
A0 07 6E 03 0C 00 10 00 B8 3C 20 00 80 01 02 03 04 B0 65 66 01 1D 80 18 71 1C 16 20 58 2C 25 00 40 84
B0 67 D8 5D C4 01 78 80 03 E3 05 C0 00 E4 0F 00 C0 C0 63 00 00 9E 01 1D 00 72 51 D0 1E 20 6E 28 55 00
C0 18 66 21 50 B0 51 00 1B 30 40 70 36 00 40 84 63 D0 40 84 63 00 00 1E 00 00 00 00 00 00 00 00 00 00
D0 00 00 1E 01 1D 00 72 51 D0 1E 20 6E 28 55 00 40 E0 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
E0 84 63 00 00 1E 00 00 00 00 00 00 00 00 00 00 00 F0 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 88
F0 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 42
* Checksum(HDMI 1/2)
# HDMI 1(C/S : E6 98) - HDMI UHD Deep off case Input
HDMI Deep Color On HDMI Deep Color Off
EDID Block 0, Bytes 0-127 [00H-7FH] FFh (Checksum) FFh (Checksum)
HDMI1 A0 42 E6 98
0 1 2 3 4 5 6 7 8 9 A B C D E F
HDMI2 A0 32 E6 88
0 00 FF FF FF FF FF FF 00 1E 6D 01 00 01 01 01 01
10 01 19 01 03 80 A0 5A 78 0A EE 91 A3 54 4C 99 26
20 0F 50 54 A1 08 00 31 40 45 40 61 40 71 40 81 80
4.1.5. Green Eye inspection guide(Depending on model)
30 01 01 01 01 01 01 02 3A 80 18 71 38 2D 40 58 2C
Step 1) Turn on the TV set.
40 45 00 40 84 63 00 00 1E 66 21 50 B0 51 00 1B 30
50 40 70 36 00 40 84 63 00 00 1E 00 00 00 FD 00 3A
Step 2). Press “EYE” button on the Adjustment remote control.
60 3E 1E 53 10 00 0A 20 20 20 20 20 20 00 00 00 FC
70 00 4C 47 20 54 56 0A 20 20 20 20 20 20 20 01 E6

EDID Block 1, Bytes 128-255 [80H-FFH]


0 1 2 3 4 5 6 7 8 9 A B C D E F 

80 02 03 32 F1 54 10 9F 04 13 05 14 03 02 12 20 21
90 22 15 01 5D 5E 5F 62 63 64 23 09 57 07 6E 03 0C
A0 00 10 00 B8 3C 20 00 80 01 02 03 04 E5 0E 60 61
B0 65 66 01 1D 80 18 71 1C 16 20 58 2C 25 00 40 84
C0 63 00 00 9E 01 1D 00 72 51 D0 1E 20 6E 28 55 00
D0 40 84 63 00 00 1E 00 00 00 00 00 00 00 00 00 00
E0 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 Step 3) Block the Intelligent Sensor module on the front C/A
F0 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 98 about 6 seconds. When the “Sensor Data” is lower
than 20, you can see the “OK” message
# HDMI 2(C/S : A0 32) - HDMI UHD Deep On Case → If it doesn’t show “OK” message, the Sensor
EDID Block 0, Bytes 0-127 [00H-7FH] Module is defected one.
0 1 2 3 4 5 6 7 8 9 A B C D E F You have to replace that with a good one.
0 00 FF FF FF FF FF FF 00 1E 6D 01 00 01 01 01 01
10 01 19 01 03 80 A0 5A 78 0A EE 91 A3 54 4C 99 26
20 0F 50 54 A1 08 00 31 40 45 40 61 40 71 40 81 80
30 01 01 01 01 01 01 08 E8 00 30 F2 70 5A 80 B0 58
40 8A 00 40 84 63 00 00 1E 02 3A 80 18 71 38 2D 40
50 58 2C 45 00 40 84 63 00 00 1E 00 00 00 FD 00 3A
60 3E 1E 88 3C 00 0A 20 20 20 20 20 20 00 00 00 FC
70 00 4C 47 20 54 56 0A 20 20 20 20 20 20 20 01 A0

EDID Block 1, Bytes 128-255 [80H-FFH]


0 1 2 3 4 5 6 7 8 9 A B C D E F
80 02 03 41 F1 58 10 9F 04 13 05 14 03 02 12 20 21 Step 4) After check the “OK” message come out, take out
90 22 15 01 60 61 5D 5E 5F 65 66 62 63 64 23 09 57
your hand from the Sensor module.
A0 07 6E 03 0C 00 20 00 B8 3C 20 00 80 01 02 03 04
B0 67 D8 5D C4 01 78 80 03 E3 05 C0 00 E4 0F 00 C0
→ Check “Backlight” value change from “0” to “100” or
C0 18 66 21 50 B0 51 00 1B 30 40 70 36 00 40 84 63
not. If it doesn’t change the value, the sensor is also
D0 00 00 1E 01 1D 00 72 51 D0 1E 20 6E 28 55 00 40 defected one.
E0 84 63 00 00 1E 00 00 00 00 00 00 00 00 00 00 00 You have to replace it.
F0 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 32

Copyright © LG Electronics. Inc. All rights reserved. - 15 - LGE Internal Use Only
Only for training and service purposes
4.2. V-COM Adjust (ONLY FOR EPI model) ▪ V-com Adj. must begin as start command “va 00 00” , and
finish as end command “wb 00 ff”
4.2.1 Overview
▪ V-com adjust data
▪ V-COM adj. Objective & How-it-works
V-com Data
- O bjective: To reduce each Panel’s V-COM voltage 43 inch
deviation hex dec
- How-it-works: When V-COM gain in the adjust-OSD of Max B4 180
each SET is at default value, each SET can have flicker by Default 96 150
each Panel’s V-COM voltage deviation. In order to prevent Min 78 120
flicker of each SET, find the desired each Panel’s V-COM
V-com Data
voltage value. 49 inch
hex dec
- Adj. condition: normal temperature
1) Surrounding Temperature: 25 °C ± 5 °C Max 8B 139
2) Warm-up time: About 5 Min Default 6D 109
3) Surrounding Humidity: 20% ~ 80% Min 4F 79

V-com Data
4.2.2 Equipment 55 inch
hex dec
(1) Color Analyzer: CA-310(LED Module : CH 14) or CM-H505
Max 85 133
(2) A dj. Computer(During auto adj., RS-232C protocol is
Default 68 104
needed)
(3) Adjust Remote control Min 49 73
(4) Signal : internal flicker Pattern in SET V-com Data
▪ Color Analyzer Matrix should be calibrated using CS-100 65 inch
hex dec
Max AB 171
4.2.3 Equipment connection MAP Default 8D 141
Flicker Analyzer Min 6F 111
Probe RS-232C

Computer
USB to RS-232C
4.3. White Balance Adjustment
* If you want to use Signal Source,
you use TV internal Flicker pattern
4.3.1. Overview
▪ W/B adj. Objective & How-it-works
(1) Objective: To reduce each Panel's W/B deviation
4.2.4 Adj. Command (Protocol) (2) How-it-works : When R/G/B gain in the OSD is at 192, it
<Command Format> means the panel is at its Full Dynamic Range. In order to
CMD ID DATA CR RF prevent saturation of Full Dynamic range and data, one
of R/G/B is fixed at 192, and the other two is lowered to
-. CMD: Command find the desired value.
-. ID : Command (3) Adjustment condition : normal temperature
-. Data : Command 1) Surrounding Temperature : 25 °C ± 5 °C
Ex) [Send: va 00 00\r\n] 2) Warm-up time: About 5 Min
3) Surrounding Humidity : 20 % ~ 80 %
▪ RS-232C Command used during auto-adj.
RS-232C COMMAND 4.3.2. Equipment
Explanation (1) Color Analyzer: CA-210 (LED Module : CH 14)
[CMD ID DATA]
va 00 00 V-com pattern (2) Adjustment Computer(During auto adj., RS-232C protocol
vb 00 00 ~ FE V-com adj.(internal Flicker pattern) is needed)
wb 00 FF V-com adj. completed
(3) Adjustment Remote control
(4) Video Signal Generator MSPG-925F 720p/216-Gray
(Model: 204, Pattern: 49)
4.2.5 Adj. method → Only when internal pattern is not available
• Color Analyzer Matrix should be calibrated using CS-100.
(1) Auto adj. method
1) Set TV in POWER-ONLY mode using POWER ONLY key.
2) Zero calibrate probe then place it on the center of the
Display.
3) Connect Cable(RS-232C to USB).
4) Select Model in “V-com adj. Program” and begin “V-com
adj.”.
5) When V-com adj. is complete(OK).
6) Remove probe and RS-232C to USB cable to complete
adjustment.

Copyright © LG Electronics. Inc. All rights reserved. - 16 - LGE Internal Use Only
Only for training and service purposes
4.3.3. Equipment connection MAP 4.3.5. Adj. method
(1) Auto adj. method
Co lo r Analyzer

Probe RS -232C
1) Set TV in adj. mode using POWER ON key.
Co m p ut er 2) Zero calibrate probe then place it on the center of the
RS -232C
RS -232C Display.
Pat t ern Generat o r 3) Connect Cable.(RS-232C to USB)
Signal Source
4) Select mode in adj. Program and begin adj.
5) When adj. is complete (OK Sign), check adj. status pre
* If TV internal pattern is used, not needed

mode. (Warm, Medium, Cool)


4.3.4. Adj. Command (Protocol) 6) Remove probe and RS-232C cable to complete adj.
<Command Format>
START 6E A 50 A LEN A 03 A CMD A 00 A VAL A CS STOP ▪ W/B Adj. must begin as start command “wb 00 00”, and
- LEN: Number of Data Byte to be sent finish as end command “wb 00 ff”, and Adj. offset if need.
- CMD: Command
- VAL: FOS Data value (2) Manual adjustment. method
- CS: Checksum of sent data 1) Set TV in Adj. mode using POWER ON.
- A: Acknowledge 2) Zero Calibrate the probe of Color Analyzer, then place it
Ex) [Send: JA_00_DD] / [Ack: A_00_okDDX] on the center of LCD module within 10 cm of the surface.
3) Press ADJ key → EZ adjust using adj. R/C → 7. White-
▪ RS-232C Command used during auto-adjustment. Balance then press the cursor to the right(key ►).
RS-232C COMMAND (When right key(►) is pressed 216 Gray internal pattern
Explanation will be displayed)
[CMD ID DATA]
wb 00 00 Begin White Balance adjustment 4) One of R Gain / G Gain / B Gain should be fixed at 192,
wb 00 10 Gain adjustment(internal white pattern) and the rest will be lowered to meet the desired value.
wb 00 1f Gain adjustment completed
5) Adjustment is performed in COOL, MEDIUM, WARM 3
modes of color temperature.
wb 00 20 Offset adjustment(internal white pattern)
wb 00 2f Offset adjustment completed
** G-fix adjustment
End White Balance adjustment Adjust modes (Cool), Fix the G gain to 172 (default data)
wb 00 ff
(internal pattern disappears )
and change the others (G/B Gain).
Ex) wb 00 00 → Begin white balance auto-adj. Adjust two modes(Medium / Warm), Fix the one of R/G/B
wb 00 10 → Gain adj. gain to 192 (default data) and decrease the others.
ja 00 ff → Adj. data If internal pattern is not available, use RF input. In EZ Adj.
jb 00 c0 menu 7.White Balance, you can select one of 2 Test-
... pattern: ON, OFF. Default is inner(ON). By selecting OFF,
... you can adjust using RF signal in 216 Gray pattern.
wb 00 1f → Gain adj. completed
*(wb 00 20(Start), wb 00 2f(end)) → Off-set adj. ▪ Adjustment condition and cautionary items
wb 00 ff → End white balance auto-adj. 1) Lighting condition in surrounding area
Surrounding lighting should be lower 10 lux. Try to
▪ Adj. Map isolate adj. area into dark surrounding.
Command Data Range 2) Probe location
(lower case ASCII) (Hex.) Default : Color Analyzer(CA-210) probe should be within 10 cm
Adj. item
(Decimal)
CMD1 CMD2 MIN MAX and perpendicular of the module surface (80° ~ 100°)
R Gain j g 00 C0 3) Aging time
G Gain j h 00 C0 - After Aging Start, Keep the Power ON status during 5
B Gain j i 00 C0 Minutes.
Cool - In case of LCD, Back-light on should be checked using
R Cut
G Cut
no signal or Full-white pattern.
B Cut
R Gain j a 00 C0
G Gain j b 00 C0
B Gain j c 00 C0
Medium
R Cut
G Cut
B Cut
R Gain j d 00 C0
G Gain j e 00 C0
Warm B Gain j f 00 C0
R Cut
G Cut

Copyright © LG Electronics. Inc. All rights reserved. - 17 - LGE Internal Use Only
Only for training and service purposes
4.3.6. 
R eference (White balance adjusmtment 4.5. Magic Motion Remote control test
coordinate and color temperature) - E quipment : RF Remote control for test, IR-KEY-Code
▪ Luminance : 206 Gray Remote control for test
▪ Standard color coordinate and temperature using CS-1000 - You must confirm the battery power of RF-Remote control
(over 26 inch) before test(recommend that change the battery per every lot)
Coordinate - Sequence (test)
Mode Temp ∆uv 1) If you select the ‘start key(OK)’ on the Adjustment remote
x y
control, you can pairing with the TV SET.
Cool 0.271 0.270 13000 K 0.0000 2) You can check the cursor on the TV Screen, when select
Medium 0.286 0.289 9300 K 0.0000 the "OK" key on the Adjustment remote control.
Warm 0.313 0.329 6500 K 0.0000 3) You must remove the pairing with the TV Set by select
‘Mute + OK Key’ on the Adjustment remote control.
▪ Standard color coordinate and temperature using CA-210(CH 14)

Mode
Coordinate
Temp ∆uv
4.6. 3D function test
x y (Pattern Generator MSHG-600, MSPG-6100[Support HDMI1.4])
Cool 0.271 ± 0.002 0.270 ± 0.002 13000 K 0.0000 * HDMI mode NO. 872 , pattern No.83
(1) Please input 3D test pattern like below.
Medium 0.286 ± 0.003 0.289 ± 0.003 9300 K 0.0000
Warm 0.313 ± 0.002 0.329 ± 0.002 6500 K 0.0000

4.3.7. EDGE & IOL LED White balance table


▪ Edge & ALEF LED module change color coordinate because
of aging time.
▪ Apply under the color coordinate table, for compensated
aging time. (2) When 3D OSD appear automatically, then select green key.
▪ (Normal line) Edge & ALEF LED White balance table
- gumi(Mar.~Dec.) & Global
Model : (normal line)LGD, CMI
Aging Cool Medium Warm
time x y x y x y
(Min) 271 270 286 289 313 329
1 0-2 282 289 297 308 324 348
2 3-5 281 287 296 306 323 346
3 6-9 279 284 294 303 321 343
4 10-19 277 280 292 299 319 339
5 20-35 275 277 290 296 317 336
6 36-49 274 274 289 293 316 333 (3) Don't wear a 3D Glasses, Check the picture like below.
7 50-79 273 272 288 291 315 331
8 80-119 272 271 287 290 314 330
9 Over 120 271 270 286 289 313 329

4.4. Local Dimming Function Check


(1) Turn on TV.
(2) A t the Local Dimming mode, module Edge Backlight
moving right to left Back light of IOP module moving.
(3) Confirm the Local Dimming mode.
(4) Press “exit” Key.

Copyright © LG Electronics. Inc. All rights reserved. - 18 - LGE Internal Use Only
Only for training and service purposes
4.7. Option selection per country 5. GND and Internal Pressure check
4.7.1. Overview 5.1. Method
- Option selection is only done for models in AJ/JA/IL (1) GND & Internal Pressure auto-check preparation
- Check that Power Cord is fully inserted to the SET. (If
4.7.2.Method loose, re-insert)
(1) Press "ADJ" key on the Adjustment remote control, then (2) Perform GND & Internal Pressure auto-check
select Country Group Menu. - Unit fully inserted Power cord, Antenna cable and A/V
(2) Depending on destination, select Country Group Code or arrive to the auto-check process.
Country Group then on the lower Country option, select - Connect D-terminal to AV JACK TESTER
US, CA, MX. Selection is done using +, - or ►◄ KEY. - Auto CONTROLLER(GWS103-4) ON
- Perform GND TEST
4.8. HDMI ARC Function Inspection - If NG, Buzzer will sound to inform the operator.
(1) Test equipment - If OK, changeover to I/P check automatically.
- Optic Receiver Speaker (Remove CORD, A/V form AV JACK BOX.)
- MSHG-600 (SW: 1220 ↑) - Perform I/P test
- HDMI Cable (for 1.4 version) - If NG, Buzzer will sound to inform the operator.
- If OK, Good lamp will lit up and the stopper will allow the
(2) Test method pallet to move on to next process.
1) Insert the HDMI Cable to the HDMI ARC port from the
master equipment. (HDMI2) 5.2. Checkpoint
▪ TEST voltage
- GND: 1.5 KV / min at 100 mA
- SIGNAL: 3 KV / min at 100 mA
▪ TEST time: 1 second
▪ TEST POINT
- GND TEST = POWER CORD GND & SIGNAL CABLE
METAL GND
- Internal Pressure TEST = POWER CORD GND & LIVE &
NEUTRAL
▪ LEAKAGE CURRENT: At 0.5 mArms

2) Check the sound from the TV Set. 6. Audio


No. Item Min Typ Max Unit
Audio practical max 10 12 W EQ Off
1 Output, L/R(Distortion AVL Off
= 10 % max Output) 8.10 10.8 Vrms Clear Voice Off
EQ On
Speaker
2 10 12 W AVL On
(8 Ω Impedance)
Clear Voice On

3) Check the Sound from the Speaker or using AV & Optic Measurement condition:
TEST program (It’s connected to MSHG-600) (1) RF input: Mono, 1 KHz sine wave signal, 100 % Modulation
(2) CVBS, Component: 1 KHz sine wave signal 0.5 Vrms
4.9. Tool Option selection
- Method : Press "ADJ" key on the Adjustment remote control,
then select Tool option.

4.10. Ship-out mode check (In-stop)


- After final inspection, press In-Stop key of the Adjustment
remote control and check that the unit goes to Stand-by
mode.

Copyright © LG Electronics. Inc. All rights reserved. - 19 - LGE Internal Use Only
Only for training and service purposes
7. USB S/W Download(Service only)
(1) Put the USB Stick to the USB socket.
(2) Go to General menu then enter to About This TV.
- If your downloaded program version in USB Stick is
Lower, it didn’t work.
B ut your downloaded version is Newer, USB data is
automatically detecting. (Download Version High & Power
only mode, Set is automatically Download)
(3) Show the message “Copying files from memory”.

(4) Updating is starting.


(5) Updating completed, the TV will restart automatically

(6) If your TV is turned on, check your updated version and
Tool option. (explain the Tool option, next stage)
* If downloading version is more new than your TV have,
TV can lost all channel data. In this case, you have to
channel recover. if all channel data is cleared, you didn’t
have a DTV/ATV test on production line.

* After downloading, have to adjust Tool Option again.


(1) Push "IN-START" key in service remote control.
(2) Select "Tool Option 1" and push "OK" key.
(3) Punch in the number. (Each model has their number)

Copyright © LG Electronics. Inc. All rights reserved. - 20 - LGE Internal Use Only
Only for training and service purposes
Copyright ©
X_TAL
24MHz
CI Slot DDR3 1866 X 32
T2/C/S2 W/O AD (512MB X 2EA)
P_TS
P_TS
1. LM14A(+URSA11)

Air/ A B

Only for training and service purposes


Cable TUNER DDR3 1866 X 32
R IF (+/-) (256MB X 2EA)
E (T2/C/A)
A P_TS
R DVB-S EEPROM(NVRAM)
TUNER DEMOD I2C 1
(S2) CVBS (256Kb)
(S2)

LG Electronics. Inc. All rights reserved.


LNB eMMC
(4GB)

Vx1
Mstar URSA11
51P

- 21 -
OCP LM14A
USB1 (2.0) USB
With URSA model
HDMI1 (4K@60Hz/DVI)
HDMI
HDMI2(ARC)
I2S Out MAIN Audio AMP
BLOCK DIAGRAM

I2C 4 (NTP7515)

USB_WIFI WIFI
SUB
AV/COMP CVBS/YPbPr ASSY
SCART
CVBS/RGB IR / KEY
(IN/OUT)

OPTIC SPDIF OUT


I2C 3 Sub Micom X_TAL
LAN ETHERNET (HW Port) (RENESAS 32.768KHz
R5F100GEAFB)

LGE Internal Use Only


2. Internal

Copyright © LG Electronics. Inc. All rights reserved. - 22 - LGE Internal Use Only
Only for training and service purposes
3. I2C

Copyright ©
+3.3V_NORMAL
MSTAR
LM14A
1.8KΩ
+3.3V_TU
I2C SCL/SDA4(SW)
GPIO19 / [LED0] / GPIO74

Only for training and service purposes


IC5800 100Ω
NTP7515(Main AMP) GPIO20 / [LED1] / GPIO75
1.8KΩ
I2C_SCL/SDA2(HW)
33pF +3.3V_NORMAL
GPIO30 / SCK4
33Ω TU6702
GPIO31 / SDA4 TUNER

LG Electronics. Inc. All rights reserved.


1.8KΩ +3.3V_NORMAL
I2C SCL/SDA3(HW)
IC3000 GPIO28 / SCK0 / GPIO83
RENESAS 33Ω
GPIO29 / SDA0 /GPIO84 1.8KΩ
MICOM

- 23 -
I2C SCL/SDA1(HW)
DDCR_CK/ SCK3 / GPIO54
+3.3V_NORMAL 33Ω IC101
DDCR_DA / SDA3 / GPIO53 NVRAM
+3.3V_LNA_TU
1.8KΩ
I2C_SCL/SDA6(SW)
DIM2 / TX4 / GPIO112
IC7700
33Ω 1.8KΩ
SW5094A (PMIC) DIM3 / RX4 / GPIO113
I2C SCL/SDA5(HW)
GPIO32 / SCK5 / GPIO87 TU6702
33Ω
GPIO33 / SDA5 / GPIO88 TUNER

LGE Internal Use Only


Copyright ©
4. URSA11

Only for training and service purposes


Power +13.5V

I2C_SDA6
I2C_SCL6
I2C_SCL7 V x1
URSA11 PQ

HTPDn_IN
LOCKn_IN
PANEL_VCC
(+12V)

URSA I2C_SDA7 8 lane


DC- DC Converter +1.5V_U_DDR UART2_RX DEBUG
Data_Format_0
Data_Format_1

UART I2CS_SCL
(BD9D320EFJ _3A) Switch
(URSA DDR) UART2_TX
I2CS_SDA 51P

URSA11 SYS
DC- DC Converter +1.15V
IRE SCL2_+3.3V_DB
(MP8762HGLE-Z_10A) I2C_S Port
UART

LG Electronics. Inc. All rights reserved.


(URSA) 4 Pin
UART1_TX SDA2_+3.3V_DB

Jig Download

X-Tal
(24Mhz)

- 24 -
XO_URSA

XIN_URSA

LOCKn

HTPDn
Data_Format_1
Vx1 VIDEO 8Lane
Data_Format_2
3D_EN
Vx1 OSD 4Lane L_DIM_EN
SPI_DI SPI FLASH
LM14A LOCKAn_OSD / LOCKAN_Video URSA11 SPI_DO/CK/CS (4MB)
IRE

UART1_TX
UART2_RX

UART2_TX
URSA9_CONNECT I2CS_SCL

I2CS_SDA

LGE Internal Use Only


Copyright ©
5. Tuner/CI

TDJM-G301D +3.3V_NORMAL

+2.5V_NORMAL
[+3.3V_LNA_TU] 1
[+3.3V_TUNER] 11
[3.3V_Demod_TU] 26
[+2.5V_DEMOD] 38 +3.3V_NORMAL

+1.1V_Demod_Core
[1,1V_D_Demod_Core] 28 1.8KΩ CI Slot

Only for training and service purposes


LNB_TX 10 [TONECTRL]
[LNB_TX] 29 LNB PCM_5V_CTL CI 5V +5V_CI_ON
LNB_OUT 2 [LNB] VCC
[LNB_OUT] 31 IC6900 Power detect
I2C_SCL2 7 [SCL]
[I2C_SCL2_TU] 27 A8303SESTR-TB
33Ω 8 [SDA]
[I2C_SDA2_TU] 30 I2C_SDA2
+5V_CI_ON

F5[SCK2]
LM14A
33 Ω
F6 [SDA2] AE3[GPIO_PM4] CAM_CD1_N 10K Ω
/CI_CD1 CI_CD1

LG Electronics. Inc. All rights reserved.


[I2C_SCL5_TU] 4 I2C_SCL5 OR
33 Ω F10[SCK5] AR17[PCMCD] /CI_CD2
[I2C_SDA5_TU] 5 I2C_SDA5 G10[SDA5] GATE CI_CD2
AP13[TS2CLK] CI_MISTRT
FE_DEMOD1_TS_ERROR AP12[TS2VALID] CI_MIVA_ERR
[FE_DEMOD1_TS_ERROR_TU] 12
AM13[TS2SYNC] /PCM_CE1 CI_MCLKI
FE_DEMOD1_TS_CLK AM13[PCMCEN]
[FE_DEMOD1_1_TS_CLK] 14 PCM_CE1
FE_DEMOD1_TS_SYNC AN11[TS0CLK]
[FE_DEMOD1_TS_SYNC] 15 AP9(TS0SYNC]
FE_DEMOD1_TS_VAL EB_BE_NO
[FE_DEMOD1_TS_VAL] 16 AN9[TS0VALID] AT15[PCMIOWR] CI_IOWR
EB_BE_N1
AR15PCMIORD] CI_IORD

- 25 -
FE_DEMOD1_TS_DATA[0] 17
FE_DEMOD1_TS_DATA[1] 18
FE_DEMOD1_TS_DATA[2] 19 EB_ADDR[0-14] CI_ADDR[0-14]
FE_DEMOD1_TS_DATA[3] 20 AU10-AR19 CI_ADDR[0-14]
FE_DEMOD1_TS_DATA [0-7] AP10~AM9
FE_DEMOD1_TS_DATA[4] 21 [TS0DATA[0-7] EB_DATA[0-7] CI_DATA[0-7]
FE_DEMOD1_TS_DATA[5] 22 AT13-AT18 EB_DATA[0-7]
FE_DEMOD1_TS_DATA[6] 23
FE_DEMOD1_TS_DATA[7] 24 AU11[PCMRST]
PCM_RESET
PCM_RESET
AT10[PCMWAIT] CAM_WAIT_N CAM_WAIT_N
CAM_REG_N
REG
AR14[PCMREG]
CAM_IREQ_N CAM_IREQ_N
AU20[PCMIRQA]
/EB_OE_N
AT21[PCMOEN] CI_OE
RF_SWITCH_CTL /EB_WE_N
A15 [GPIO159] AR11[[PCMWEN] CI_WE
[RF_SWITCH_CTL] 2 /TU_RESET1
A12 [GPIO62] TPI_CLK CI_TS_CLK
[/TU_RESET1_TU] 25 AN17[TS1CLK] TS_OUT_CLK
TPI_VAL CI_TS_VAL
AM17[TS1VALID] TS_OUT_VAL
IF_P ADC_I_INP TPI_SOP CI_TS_SYNC
AP1 [VIFP] AN16[TS1SYNC] TS_OUT_SYNC
[IF_P] 6 IF_N FILTER ADC_I_INN
AP2 [VIFM] TPI_DATA[0-7]
[IF_N] 7 AN16~AP19 TPI_DATA[0-7]
TUNER_SIF 33Ω TS_OUT[0-7]
AN2[SIFP] [TPI_DATA[0-7]]
[TU_SIF_TU] 8
TU_CVBS FE_DEMOD1_TS_DATA [0-7] CI_MDI[0-7]
[TU_CVBS_TU] 9 AE5[CVBS0] AM14~AM15 TS_IN[0-7]
[TPO_DATA[0-7]]
33Ω
IF_AGC
[IF_AGC_TU] 3 AP3[IF_AGC]

LGE Internal Use Only


Copyright ©
Jack Side SoC
Side
JK3802
COMP1_Y COMP1_Y
[GIN1P]

COMP1_Pb COMP1_Pb
6. Video/Audio In

[BIN1P]

COMP1_Pr COMP1_Pr

Only for training and service purposes


[RIN1P]

AV1_CVBS_IN AV1_CVBS_IN
[CVBS1]

COMP1/AV1/DVI_L_IN COMP1/AV1/DVI_L_IN
[LINE_IN_0L]

COMP1/AV1/DVI_R_IN COMP1/AV1/DVI_R_IN
[LINE_IN_0R]

LG Electronics. Inc. All rights reserved.


SCART
SC_CVBS_IN SC_CVBS_IN LM14A
[CVBS2]

- 26 -
SC_FB/ID SC_FB/ID
[VSYNC0,HSYNC0]

SC_R/G/B SC_R/G/B
[RIN0P,GIN0P,BIN0P]

SC_L/R_IN SC_L/R_IN
[LINE_IN_1L,LINE_IN_1R]

DTV/MNT_V_OUT DTV/MNT_V_OUT
[CVBSOUT1]

DTV/MNT_L/R_OUT SCART_L/Rout
[LINEOUT_L2, LINEOUT_R2]

JK4600

Tuner TU_CVBS_TU TU_CVBS


[CVBS0]

TUNER_SIF, IF_P/N_TU TUNER_SIF, IF_P/N


[SIFP,VIFP/VIFM]

FE_DEMOD1/2_TS_ERROR,CLK,SYNC,VAL FE_DEMOD1/2_TS_ERROR,CLK,SYNC,VAL
[TS0CLK,TS0SYNC,TS0VALID]

LGE Internal Use Only


Copyright ©
7. Audio Out

SCART

SCART_L/ Rout IC6000 DTV/MNT_L/R_OUT


[ LINEOUT_L2]
COMP1/ AV1/ DVI_L_IN AZ4580MTR LPF
[ LINEOUT_R2]
COMP1/ AV1/ DVI_R_IN

Only for training and service purposes


[ LINEIN_L0] OP AMP
[ LINE_N_R0]
Mute CTRL
JK3802 (TR)
JK4600
DVB only
SCART

SCART_MUTE

LG Electronics. Inc. All rights reserved.


SC_L_IN / SC_R_IN [ LINEIN_L1] AUD_LRCK
[ I2S_OUT_WS/ GPIO98]
[ LINE_N_R1]
AUD_LRCH
[ I2S_OUT_SD/ GPIO101] 4P WAFER
AUD_SCK
[ I2S_OUT_BCK/ GPIO100]
IC5800 LPF SPEAKER_L
DVB only I2C_SDA4
Audio AMP
JK4600 [ GPIO20/ [ LED1] / GPIO75]
NTP7515 LPF SPEAKER_R
[ GPIO19/ [ LED0] / GPIO74]
I2C_SCL4

- 27 -
[ PWM3/ GPIO155] AMP_RESET_N

LM14A AMP_MUTE

Tuner
TUNER_SIF
TR BUF [ SIFP]
IC3000
MICOM

SPDIF_OUT
[ SPDIF_OUT]

JK3800

LGE Internal Use Only


Copyright ©
8. HDMI
[DDCDD_CK/GPIO44] DDC_SCL_3
DDC_SDA_3
[DDCDD_DA/GPIO45]
TMDS Link 8bits

HDMI2&External EDID
IC3301 HDMI1.4(ARC)

Only for training and service purposes


LM14A EDID External
EDID

LG Electronics. Inc. All rights reserved.


- 28 -
CEC_REMOTE

DDC_SCL_1
[DDCDA_CK/GPIO38]
DDC_SDA_1
[DDCDA_DA/GPIO39]
TMDS Link 8bits

MHL_DET_LM15
[GPIO_PM[14]/GPIO24]
HDMI1&MHL
HDMI2.0

X-Tal(X3000) RENESAS
32.768kHz MICOM(IC3000) Q3001
* TMDS Link 8bits = TMDS DATA 6bits(DATA0,1,2)+ TMDS CLK 2bits HDMI_CEC_MICOM

LGE Internal Use Only


Copyright ©
USB_DM3 USB1
[DM_P2] +5V_USB_3
[DP_P2] USB_DP3
[TGPIO0/GPIO157] /USB_OCD3
OCP USB2.0
[TGPIO1/GPIO158] IC2302
USB_CTL3

Only for training and service purposes


[DM_PSS1]
[DP_PSS1]
[SAR0/GPIO46]
[SAR1/GPIO47]

LG Electronics. Inc. All rights reserved.


[DM_PSS]
9. USB / WIFI / M-REMOTE / UART

[DP_PSS]
LM14A
[SSUSB_RXP/N]
[SSUSB_TXP/N]

- 29 -
[GPIO_PM[1]/PM_UART1/GPIO11]
[GPIO_PM[5]/PM_UART1/GPIO15]

WIFI_DM
[DM_P0]

[DP_P0] WIFI_DP
WIFI only
M_RFModule_RESET
[GPIO_PM[10]/[SPI-CZ2N]/GPIO20]

SOC_TX
[GPIO3/TX1/GPIO58]
SOC_RX
[GPIO4/RX1] RS232C_Debug(4P wafer)

RENESAS MICOM(IC3000)

LGE Internal Use Only


EXPLODED VIEW
IMPORTANT SAFETY NOTICE
Many electrical and mechanical parts in this chassis have special safety-related characteristics. These
parts are identified by in the Schematic Diagram and EXPLODED VIEW.
It is essential that these special safety parts should be replaced with the same components as
recommended in this manual to prevent Shock, Fire, or other Hazards.
Do not modify the original design without permission of manufacturer.

900
400

901
570
800

571
521

120
540

121
530
(Option)
LV2
LV1

820

500

Set + Stand
A10
A2
200

Copyright © LG Electronics. Inc. All rights reserved. - 30 - LGE Internal Use Only
Only for training and service purposes
LD59R
(LM14A)

Copyright © 2015 LG Electronics. Inc. All rights reserved. LGE Internal Use Only
Only for training and service purposes
SPI_CK_SOC COMPENSATION_DONE OLED
LM14A+URSA9
SPI_DI_SOC TXVBY1_0N
FAN_ON LM14A UF68/64
+3.3V_NORMAL SPI_DO_SOC FRC_FLASH_SEL_SOC TXVBY1_0P
CHIP CONFIG NVRAM +3.3V_NORMAL
/SPI_CS TXVBY1_1N /TU_RESET2
Rohm_NVRAM
IC101-*1
FRC_FLASH_WP GST_A LM14A UF74
BR24G256FJ-3
EAN62389502 TXVBY1_1P
ROHM Semiconductor KOREA CORPORATION
TXOSD_3P LOCKAn_OSD GCLK_A
4.7K

4.7K

4.7K

Atmel_NVRAM WOL_WAKE_UP_SOC
4.7K

A0 VCC

IC101 1 8

TXOSD_3N URSA9_CONNECT MCLK_A PMIC_RESET 5V_DET_HDMI_1


AT24C256C-SSHL-T C100 A1
2 7
WP

Data_Format_1
OPT

EO_A
OPT

EAN61133501
ATMEL CORPORATION
0.1uF A2
3 6
SCL
TXOSD_2P DATA_FORMAT_1_SOC LM14A_ONLY LOCKOUT12 /USB_OCD3
GND
4 5
SDA

TXOSD_2N Data_Format_0
R108

R110

R115

DATA_FORMAT_0_SOC USB_CTL3
R122

TXOSD_1P URSA_RESET_SoC
A0 VCC HTPDAn_OSD
1 8 L/D_VSYNC_SOC
TXOSD_1N
HTPDAn_Video IC100
Write Protection L/D_CLK_SOC
LED1 A1 WP
TXOSD_0P LGE5332(LM14A)
2 7
TXOSD_0N L/D_DI_SOC
SPI_DI_SOC - Low : Normal Operation IC100
- High : Write Protection EB_DATA[0-7]
LED0 A2
3 A0’h SCL LGE5332(LM14A)
6
EB_DATA[0]
PWM_PM I2C_SCL1
V-BY-ONE AH14
4.7K

4.7K

4.7K

FE_DEMOD1_TS_DATA[0-7]
4.7K

EB_DATA[1] PCM_D[0]/GPIO147 FE_DEMOD1_TS_DATA[0]


GND SDA I2C_SDA1 AG13 AH13
4 5 PCM_D[1]/GPIO148 TS1_D0/GPIO182
EB_DATA[2] FE_DEMOD1_TS_DATA[1]
OPT

OPT

33 D9 AF32 AG12 AG11


AR101 PWM_DIM TXVBY1_0N PCM_D[2]/GPIO149 TS1_D1/GPIO181
PWM0/GPIO152 LVSYNC/[VX1_0-] EB_DATA[3] AK22 AG10 FE_DEMOD1_TS_DATA[2]
F10 AF31
R109

TXVBY1_0P
R111

R116

PWM_DIM2
R123

PWM1/GPIO153 LHSYNC/[VX1_0+] EB_DATA[4] PCM_D[3]/GPIO119 TS1_D2/GPIO180 FE_DEMOD1_TS_DATA[3]


F8 AG32 AK21 AJ11
FAN_ON TXVBY1_1N PCM_D[4]/GPIO120 TS1_D3/GPIO179
PWM2/GPIO154 LDE/[VX1_1-] EB_DATA[5] AL21 AH10 FE_DEMOD1_TS_DATA[4]
E9 AG31 TXVBY1_1P
AMP_RESET_N PWM3/GPIO155 LCK/[VX1_1+] EB_DATA[6] PCM_D[5]/GPIO121 TS1_D4/GPIO178 FE_DEMOD1_TS_DATA[5]
AM23 AJ13
EB_DATA[7] PCM_D[6]/GPIO122 TS1_D5/GPIO177 FE_DEMOD1_TS_DATA[6]
N5 AH31 AH20 AG9
PWM_PM TXVBY1_2N EB_ADDR[0-14] PCM_D[7]/GPIO123 TS1_D6/GPIO176
PWM_PM/GPIO7 R_ODD[7]/LVB0N/[VX1_2-] AH9 FE_DEMOD1_TS_DATA[7]
AH30 TXVBY1_2P
R_ODD[6]/LVB0P/[VX1_2+] EB_ADDR[0] TS1_D7/GPIO175
F4 AJ31 AG14 AH11
TXVBY1_3N PCM_A[0]/GPIO146 TS1_CLK/GPIO172 FE_DEMOD1_TS_CLK
CHIP_CONFIG[3:0] /USB_OCD2 SAR0/GPIO46 R_ODD[5]/LVB1N/[VX1_3-] EB_ADDR[1] AL20 AJ10
G5 AJ32 TXVBY1_3P
{LED1, SPI_DI,LED0, PWM_PM} USB_CTL2 SAR1/GPIO47 R_ODD[4]/LVB1P/[VX1_3+] EB_ADDR[2] PCM_A[1]/GPIO145 TS1_VLD/GPIO174 FE_DEMOD1_TS_VAL
E5 AK32 AG15 AH12
FRC_FLASH_WP TXVBY1_4N PCM_A[2]/GPIO143 TS1_SYNC/GPIO173 FE_DEMOD1_TS_SYNC
Value Mode Description SAR2/GPIO48 R_ODD[3]/LVB2N/[VX1_4-] EB_ADDR[3] AH15
E4 AK31 TXVBY1_4P TPI_DATA[0-7]
4’b1000 SB51_ExtSPI 51 boot from SPI DDTS_TX SAR3/GPIO49 R_ODD[2]/LVB2P/[VX1_4+] EB_ADDR[4] PCM_A[3]/GPIO142 TPI_DATA[0]
4’b1001 HEMCU_ExtSPI ARM boot from SPI G4 AL32 AM19 AK17
TXVBY1_5N PCM_A[4]/GPIO141 TS0_D0/GPIO161
SAR5 R_ODD[1]/LVBCLKN/[VX1_5-] EB_ADDR[5] AJ17 AL18 TPI_DATA[1]
4’b1010 HEMCU_ROM_EMMC ARM boot from ROM; outer storage is eMMC AL31 TXVBY1_5P
4’b1011 HEMCU_ROM_NAND ARM boot from ROM; outer storage is NAND R_ODD[0]/LVBCLKP/[VX1_5+] EB_ADDR[6] PCM_A[5]/GPIO139 TS0_D1/GPIO162 TPI_DATA[2]
AK30 AJ16 AK18
4’b1100 DBUS for test only TXVBY1_6N PCM_A[6]/GPIO138 TS0_D2/GPIO163
G_ODD[7]/LVB3N/[VX1_6-] EB_ADDR[7] AH17 AL15 TPI_DATA[3]
4’b0000 SB51_ExtSPI + Authentication 51 boot from SPI with ARM authentication W5 AL30 TXVBY1_6P
SPI_CK_SOC PM_SPI_CK/GPIO1 G_ODD[6]/LVB3P/[VX1_6+] EB_ADDR[8] PCM_A[7]/GPIO137 TS0_D3 TPI_DATA[4]
4’b0001 SB51_ExtSPI + Authentication HEMCU_ExtSPI + Authentication V4 AK29 AM20 AL16
SPI_DI_SOC TXVBY1_7N PCM_A[8]/GPIO131 TS0_D4/GPIO165
4’b0011 HEMCU_ROM_NAND + Authentication ARM boot from ROM with authentication; PM_SPI_DI/GPIO2 G_ODD[5]/LVB4N/[VX1_7-] EB_ADDR[9] AH19 AK15 TPI_DATA[5]
V5 AL29 TXVBY1_7P
SPI_DO_SOC PM_SPI_DO/GPIO3 G_ODD[4]/LVB4P/[VX1_7+] EB_ADDR[10] PCM_A[9]/GPIO129 TS0_D5/GPIO166 TPI_DATA[6]
Y6 AJ20 AM16
/TU_RESET1 PM_SPI_CZ/GPIO0 EB_ADDR[11] PCM_A[10]/GPIO125 TS0_D6/GPIO167 TPI_DATA[7]
R167 0 Y4 AK28 TXOSD_0N
AK20 AK16
/SPI_CS GPIO_PM[6]/[SPI-CZ1N]/GPIO16 G_ODD[3]/LVA0N/[OSD_0-] EB_ADDR[12] PCM_A[11]/GPIO127 TS0_D7/GPIO168
OPT Y5 AM28 AG17 AL19
TXOSD_0P PCM_A[12]/GPIO136 TS0_CLK/GPIO171 TPI_CLK
GPIO_PM[10]/[SPI-CZ2N]/GPIO20 G_ODD[2]/LVA0P/[OSD_0+] EB_ADDR[13] AJ19 AM17
LM14 HW Option M_RFModule_RESET
G_ODD[0]/LVA1P/[OSD_1+]
AL28
AK27
TXOSD_1N
TXOSD_1P
EB_ADDR[14] AG18
PCM_A[13]/GPIO132 TS0_VLD/GPIO169
AL17
TPI_VAL
G_ODD[1]/LVA1N/[OSD_1-] PCM_A[14]/GPIO133 TS0_SYNC/GPIO170 TPI_SOP
AK26 TXOSD_2N
+3.3V_NORMAL B_ODD[7]/LVA2N/[OSD_2-] AH18 AH23
AL8 AL26 TXOSD_2P
DDCA_CK DDCA_CK/GPIO8 B_ODD[6]/LVA2P/[OSD_2+] SM_Vsel CAM_IREQ_N PCM_IRQA_N/GPIO135 TS3_D0/GPIO206 POL EPI
AK8 AM26 AM22 AH27
DDCA_DA TXOSD_3N SM_CLK EB_OE_N PCM_OE_N/GPIO126 TS3_D1/GPIO207 GST_A GST
DDCA_DA/GPIO9 B_ODD[5]/LVACLKN/[OSD_3-] AG20 AJ23
AK25 TXOSD_3P GCLK
B_ODD[4]/LVACLKP/[OSD_3+] SM_RST EB_BE_N1 PCM_IORD_N/GPIO128 TS3_D2/GPIO208 GCLK_A
AL25 AL22 AG27
B_ODD[3]/LVA3N/[LOCKN] LOCKAn_Video SM_IO /PCM_CE1 PCM_CE_N/GPIO124 TS3_D3/GPIO209 MCLK_A MCLK
AH28 AK24 AK19 AH24
10K
10K

10K

10K

10K

10K

10K

10K

EB_WE_N PCM_WE_N/GPIO134 OPT_P


10K

10K

TS3_D4/GPIO210
10K

10K

SOC_TX GPIO3/TX1/GPIO58 B_ODD[2]/LVA3P/[HTPDN] HTPDAn_Video SM_VCC


BIT2_1

BIT10_1

BIT11_1
BIT0_1

BIT1_1

BIT3_1

BIT4_1

BIT5_1

BIT6_1

BIT7_1

BIT8_1

AG21 AH26
BIT9_1

AH29 AL24
SOC_RX GPIO4/RX1 B_ODD[1]/LVA4N/[OSD_LOCKN] LOCKAn_OSD CAM_CD1_N PCM_CD_N/GPIO151 TS3_D5/GPIO211 SOE
AA4 AK23 AH16 AJ25
FRC_FLASH_SEL_SOC GPIO23/[TX3]/GPIO78 B_ODD[0]/LVA4P/[OSD_HTPDN] HTPDAn_OSD PCM_RESET PCM_RESET/GPIO150 TS3_D6/GPIO212 FB
W6 AJ14 AG26
R119
R112

R125

R128

R132

R135

R138

R140

R142

R146
R105

R148

/TU_RESET2 GPIO24/[RX3]/GPIO79 CAM_REG_N PCM_REG_N/GPIO144 TS3_D7/GPIO213 EO_A E/O


F14 AG19 AH25
I2C_SCL6 DIM2/TX4/GPIO112 SM_CD EB_BE_N0 PCM_IOWR_N/GPIO130 TS3_CLK/GPIO216 HCONV
F12 AG16 AJ26
BIT0 I2C_SDA6 DIM3/RX4/GPIO113 CAM_WAIT_N PCM_WAIT_N/GPIO140 TS3_VLD/GPIO214 DPM
AG24
BIT1 TS3_SYNC/GPIO215 LOCKOUT12 LOCK
AJ27
CPU_VID1 GPIO2/GPIO57
BIT2
C7
BIT3 BIT0 EMMC_IO15/[GPIO]/GPIO189
C6
BIT1 EMMC_IO17/[GPIO]/GPIO188
BIT4 AE2 C8 AJ28
GPIO_PM[0]/GPIO10 COMP1_DET EMMC_CMD EMMC_IO9/[EMMC_CMD]/GPIO183 GPIO8/[TS4_D[0]]/GPIO63 FE_DEMOD3_TS_DATA
B8 AG28
BIT2 EMMC_IO14/[GPIO]/GPIO185 GPIO5/[TS4_CLK]/GPIO60 FE_DEMOD3_TS_CLK

1K
R176
BIT5 U6 A9 AJ29
GPIO_PM[3]/GPIO13 DDTS_RX EMMC_CLK EMMC_IO10/[EMMC_CLK]/GPIO186 GPIO7/[TS4_VLD]/GPIO62 FE_DEMOD3_TS_VAL
P4 B7 AG29
BIT6 GPIO_PM[4]/GPIO14 PCM_5V_CTL R175 TCON_I2C_EN BIT3 EMMC_IO16/[GPIO]/GPIO187 GPIO6/[TS4_SYNC]/GPIO61 FE_DEMOD3_TS_SYNC
U5 22 B9
GPIO_PM[7]/GPIO17 EMMC_RST EMMC_IO11/[EMMC_RSTN]/GPIO190
AE5 A8
BIT7 PMIC_RESET BIT4 EMMC_IO12/[GPIO]/GPIO184
GPIO_PM[8]/GPIO18 C9
AJ7 AJ5
I2C_SCL3 GPIO28/SCK0/GPIO83 GPIO_PM[9]/GPIO19 COMPENSATION_DONE EMMC_STRB EMMC_IO8/[NAND-DQS]/GPIO191
BIT8 AH8 AG6 B6
I2C_SDA3 EMMC_DATA[0-7] BIT5 EMMC_IO13/[GPIO]/GPIO217
GPIO29/SDA0/GPIO84 GPIO_PM[13]/GPIO23 URSA9_CONNECT
E11
BIT9 I2C_SCL1 DDCR_CK/SCK3/GPIO54 EMMC_DATA[6] C10
E10
I2C_SDA1 DDCR_DA/SDA3/GPIO53 EMMC_DATA[7] EMMC_IO6/[EMMC_D6]/GPIO221
AJ6 B11
I2C_SCL2 GPIO30/SCK4/GPIO85 EMMC_DATA[2] EMMC_IO7/[EMMC_D7]/GPIO220
AG8 A11
I2C_SDA2 GPIO31/SDA4/GPIO86 EMMC_DATA[1] EMMC_IO2/[EMMC_D2]/GPIO219
BIT10 AH7 P5 C11
I2C_SCL5 GPIO32/SCK5/GPIO87 GPIO_PM[1]/PM_UART1/GPIO11 /USB_OCD1 EMMC_DATA[0] EMMC_IO1/[EMMC_D1]/GPIO218
AJ8 P6 A12 AL2
BIT11 I2C_SDA5 GPIO33/SDA5/GPIO88 GPIO_PM[5]/PM_UART1/GPIO15 USB_CTL1 EMMC_DATA[3] EMMC_IO0/[EMMC_D0]/GPIO194 VIFP
AJ4 B12 AM2
GPIO_PM[11]/PM_UART0/GPIO21 DATA_FORMAT_0_SOC EMMC_DATA[4] EMMC_IO3/[EMMC_D3]/GPIO193 VIFM
AH4 C12
GPIO_PM[12]/PM_UART0/GPIO22 DATA_FORMAT_1_SOC EMMC_DATA[5] EMMC_IO4/[EMMC_D4]/GPIO192
B13 AK1 Close to MSTAR DTV_IF
EMMC_IO5/[EMMC_D5]/GPIO222 SIFP
AK2
10K

10K
10K

10K

10K

10K

10K

10K

10K

SIFM
10K
10K

10K

L6 G7 R183 100 C103 0.1uF OPT IF_P


BIT10_0

BIT11_0
BIT2_0
BIT0_0

BIT1_0

BIT7_0

BIT8_0

BIT9_0
BIT4_0
BIT3_0

BIT5_0

BIT6_0

CPU_VID0 VID0/GPIO50 TESTPIN C107


M6 AK3 100pF
CORE_VID0 VID1/GPIO51 IFAGC
AD5
R126

LED0
R129
R106

R133

R136

R139

R141

LED0/GPIO29
R143

R147

R149
R113

R120

AD4
LED1 LED1/GPIO30 R184 100 C104 0.1uF OPT IF_N
AB5 AJ1 C109
WOL_WAKE_UP_SOC WOL_INT_OUT/[GPIO]/GPIO52 TGPIO0/GPIO157 /USB_OCD3 33pF OPT
E13 AJ2 C110
SPI1_DI/GPIO107 HP_DET TGPIO1/GPIO158 USB_CTL3 33pF
D12 R4
SPI1_CK/GPIO106 RF_SWITCH_CTL TGPIO2/SCK1/GPIO159 I2C_SCL7
F11 R5
SPI2_DI/GPIO109 L/D_DI_SOC TGPIO3/SDA1/GPIO160 I2C_SDA7
D11
SPI2_CK/GPIO108 L/D_CLK_SOC
E12
VSYNC_LIKE/GPIO105 L/D_VSYNC_SOC C101 0.1uF R185 47
D14 AM7 TU_SIF
DIM0/GPIO110 SC_DET NC_1 C102 0.1uF R186 47
E14 AL7 R188
DIM1/GPIO111 AV1_CVBS_DET NC_2 C105 300
AM8 1000pF
NC_3 ANALOG SIF OPT OPT
AK7
NC_4 Close to MSTAR
20150123 version AL5
NC_5
+3.3V_NORMAL
BIT(0/1) DVB ATSC JP AM5
GPIO34/GPIO89 CORE_VID1
M7 L100
00 TW/COL US NC_6 PZ1608U121-2R0TF
Low High
01 CN/HK KR JP
10 EU BR T-con I2C R182 C106
BIT8 16Kbit 32Kbit 0.1uF
BIT(2/3) EU/CIS AJJA TW/COL CN/HK KR North.AM BR JP Protocol 10K
11 AJJA CI BIT(6/7) B/E(FRC)
R187
00 T2/C/S2 PIP T2/C PIP T2/C PIP Default ATSC NIM+T2 Default ISDB PIP Default 0
00 LM14A only BIT9 Division NON_Division 4_Division IF_AGC
Low High
01 T2/C/S2 T2/C/S2 T2/C ATSC+T2 ISDB EXT
01 N/A C108
BIT4 Display LCD OLED 0.047uF
BIT10 Interface EPI Vx1
10 LM14A+URSA11 10 T/C T T/C ATSC 25V
ISDB INT
4K@60Hz
BIT5 Resolution FHD UHD 11 LM14A+URSA11 11 T2 BIT11 OS(DDR) WebOS Lite WebOS
ATSC PIP
4K@120Hz

+3.3V_TU
+3.3V_LNA_TU
+3.3V_NORMAL I2C PULL UP
GPIO PULL UP
Mstar Debug RS232C_Debug DDTS_Debug
+3.3V_NORMAL MSTAR_DEBUG_OLD
P101 +3.3V_NORMAL +3.3V_NORMAL
UART_4PIN_WAFER DDTS_Debug
R100
1.8K

R101
1.8K

R102
1.8K

R103
1.8K

R104
1.8K

R107
1.8K

R114
1.8K

R121
1.8K

R124
1.8K

R127
1.8K

R130
1.8K

R131
1.8K

R134
1.8K

R137
1.8K

MSTAR_DEBUG_NEW
12505WS-04A00
P100 P102 P103
12507WS-04L 12507WS-04L 12507WS-04L
10K

10K

10K
10K
10K

10K

10K

10K
10K

10K

I2C_SDA7
10K

10K
1
OPT

I2C for URSA9 (URSA9 Only)


OPT

I2C_SCL7
OPT

OPT
1 1
R152

1
R154

R164

I2C_SDA6
R156
R157

R161

R165

R170
R166

R168

I2C for LCD Module 2


R178

R180
I2C_SCL6
I2C_SDA1 2 SOC_RX 2
I2C for NAVRAM 2 DDTS_RX
I2C_SCL1
10K

10K
/TU_RESET1 DDCA_CK 3
I2C_SDA3
OPT

OPT
I2C for Micom RF_SWITCH_CTL 3 3
I2C_SCL3 3
AMP_RESET_N 4
R179

R181
I2C_SDA4 DDCA_DA
I2C for Main Amp / Woofer AMP TCON_I2C_EN
I2C_SCL4 4 4 SOC_TX 4
/USB_OCD3 5 DDTS_TX
I2C_SDA5
I2C for tuner USB_CTL3
I2C_SCL5 5 5 5
/USB_OCD2
I2C_SDA2 USB_CTL2
I2C for tuner&LNB M_RFModule_RESET
AR100 I2C_SCL2
33 PCM_5V_CTL
I2C_SDA_MICOM I2C_SDA3
I2C_SCL_MICOM I2C_SCL3

THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES BSD-15Y-LM14A-001_00-HD


SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FIRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS LM14A 2015-01-23
ESSENTIAL THAT ONLY MANUFACTURES SPECIFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC. MAIN1_SYSTEM 01

Copyright © 2015 LG Electronics. Inc. All rights reserved. LGE Internal Use Only
Only for training and service purposes
+1.1V_VDDC_CPU
+1.1V_Bypass Cap(CLOSE TO CHIP SIDE)
IC100
LGE5332(LM14A) 1st layer 4th layer

+1.1V_VDDC +1.1V_VDDC +1.1V_VDDC DVDD_DDR11


4th layer

0.1uF

0.1uF

0.1uF
J9 AC17 L226

10uF
VDDC_1 VDDC_24 PZ1608U121-2R0TF
J10 AC18 C263 C323
VDDC_2 VDDC_25
J11 AC19 10uF C208 0.1uF
VDDC_3 VDDC_26 10V 10uF 16V

C322
C276

C278

C299
J12 AC20
J13
VDDC_4 VDDC_27
AC21
10V 2A C257
VDDC_5 VDDC_28 C324
K9 AC22 0.47uF 0.47uF
VDDC_6 VDDC_29 6.3V 6.3V
K10 AD17
VDDC_7 VDDC_30
K11 AD18
VDDC_8 VDDC_31
K12 AD19 Close to chip side
VDDC_9 VDDC_32
K13 AD20
VDDC_10 VDDC_33
L9 AD21 Close to chip side
VDDC_11 VDDC_34
L10 AD22
VDDC_12 VDDC_35
L11 AE19
VDDC_13 VDDC_36 Close to chip side
L12 AE20
VDDC_14 VDDC_37
R11 AE21
VDDC_15 VDDC_38 +1.1V_VDDC
R12 AE22
VDDC_16 VDDC_39 AVDDL_MOD11
R13 1st layer 4th layer
VDDC_17 4th layer
T11 AE31
VDDC_18 VDD_SRAM_1 L202
T12 AC24 PZ1608U121-2R0TF
VDDC_19 VDD_SRAM_2
T13 AD23

0.1uF

0.1uF

0.1uF
VDDC_20 VDD_SRAM_3

10uF
U11
VDDC_21
U12
VDDC_22 CTRL_SRAMLDO
AE30
C205
10uF
C261
0.1uF 2A C320
U13 10V 16V C238

C250
C230

C234

C235
VDDC_23 0.47uF 0.47uF
6.3V 6.3V
AVDDL_MOD11 A6 AVDD_DMPLL
EMMC_CTRL
W21
AVDDL_PREDRV_1
Y21
AVDDL_PREDRV_2
AD29 V7
AVDDL_PREDRV_3 AVDD_NODIE Close to chip side
0.1uF

AD30
AVDDL_MOD_1 DVDD_DDR11
W20
AVDD15_MOD AVDDL_MOD_2 Close to chip side
Y20 L7
AVDDL_MOD_3 AVDDL_MHL3_1 AVDDP3P3_MHL Close to chip side
U19 N12
C227

AVDD15_MOD_1 AVDDL_MHL3_2
V19 R7
AVDD15_MOD_2 AVDD3P3_MHL3_1
DVDD_DDR11 AA13 T7
AVDDL_USB3_1 AVDD3P3_MHL3_2
AF11 AVDD33_ADC
AVDDL_USB3_2 AVDD_DMPLL

U21 Y7
VDDC_CPU_1 AVDD3P3_ETH
U22 AB7
+1.1V_VDDC_CPU VDDC_CPU_2 AVDD3P3_DADC_1
U23
U24
VDDC_CPU_3 AVDD3P3_DADC_2
AB8
AA7
+1.5V_Bypass Cap
VDDC_CPU_4 AVDD3P3_ADC_1 AVDD_DMPLL +1.5V_DDR AVDD_DDR
U25 AA8
VDDC_CPU_5 AVDD3P3_ADC_2
V23 G9
VDDC_CPU_6 AVDD3P3_USB_1
V24 G10 L227
VDDC_CPU_7 AVDD3P3_USB_2 PZ1608U121-2R0TF
V25 AB15
VDDC_CPU_8 AVDD3P3_USB3_1 1st layer 4th layer
W23 AF13 AVDD_AU33
VDDC_CPU_9 AVDD3P3_USB3_2 AVDDP3P3 L200 AVDD_DDR AVDD15_MOD
W24 AD7
VDDC_CPU_10 AVDD_AU33
W25 AE7
2A

0.47uF
VDDC_CPU_11 AVDD_EAR33 PZ1608U121-2R0TF

0.1uF

0.1uF

0.1uF

0.1uF

0.1uF

0.1uF

0.1uF
Y23 AF8
VDDC_CPU_12 AVDD3P3_DMPLL OPT
L224
Y24
Y25
VDDC_CPU_13 VDDP_1
AE15
AF15
4A C207
10uF
C201
10uF
C247
C316
10uF
C223
10uF
C248
0.47uF
C249
0.47uF
0.47uF PZ1608U121-2R0TF
VDDC_CPU_14 VDDP_2 10V 10V 6.3V

C314
10V 10V 6.3V

0.1uF
C209

C224

C225

C226

0.1uF
AA22 6.3V

C203

C204

C287
VDDC_CPU_15
AA23
VDDC_CPU_16
AA24 V17
VDDC_CPU_17 AVDD_MOD_1

C307
AA25 V18

C308
VDDC_CPU_18 AVDD_MOD_2
AB24 W19
VDDC_CPU_19 AVDD_LPLL_1
AB25 Y19
VDDC_CPU_20 AVDD_LPLL_2
Close to chip side Close to chip side
AE16
MCP_VDDC_1
AF16 N15
MCP_VDDC_2 AVDD_PLL_A
N16
AVDD_PLL_B
DVDD_NODIE VDDP_NAND_A VDDP_NAND_C
L13
DVDD_NODIE
DVDD_DDR11 H16
VDDP_3318_A/[3.3V/1.8V]
K21 K16
C200 DVDD_DDR_1 VDDP_3318_C/[3.3V/1.8V]
N21 AVDD_DDR
1uF DVDD_DDR_2
25V
M21 J21
DVDD_DDR_3 AVDD_DDR_A_1
L21 K17
DVDD_DDR_4 AVDD_DDR_A_2
K18
AVDD_DDR_A_3
K19
AVDD_DDR_A_4
AVDD_DDR_A_5
L17
GND JIG POINT +3.3V_Bypass Cap
L19
AVDD_DDR_A_6
L20
AVDD_DDR_A_7
J23
AVDD_DDR_B_1
K22
AVDD_DDR_B_2 4th layer
JP202

JP204

JP205
JP203

K23
AVDD_DDR_B_3 +3.3V_NORMAL AVDDP3P3
M22 +3.3V_NORMAL
AVDD_DDR_B_4
N22 AVDD_DMPLL
AVDD_DDR_B_5 1st layer 4th layer
N23
AVDD_DDR_B_6 L215
P23 L213 PZ1608U121-2R0TF

0.1uF
AVDD_DDR_B_7 PZ1608U121-2R0TF

0.1uF

0.47uF

0.1uF
C293
2A 0.47uF 2A C256 C217

C269
L18 6.3V C222 10uF
C268 10uF
AVDD_DDR_LDO_A 10uF

C274
10V 10V

C311

C253
L22 10uF 10V
AVDD_DDR_LDO_B 10V
AVDD5V_MHL
H7
AVDD_HDMI_5V_PA
R201 Close to chip side
0 AVDD_DDR
G8
GND_EFUSE
+3.3V_NORMAL VDDP_NAND_C 0
R207 Close to chip side Close to chip side
0.1uF

4th layer
C14 OPT
C229

AVDD_DDR_VBP_A_1 0.47uF C210


B14 L208
5V_HDMI_1 AVDD5V_MHL AVDD_DDR_VBP_A_2 AVDD33_ADC
J17 PZ1608U121-2R0TF
AVDD_DDR_VBP_A_3
J18 0.47uF C211
AVDD_DDR_VBP_A_4 L221
0.1uF

+5V_NORMAL 4th layer


R200
10 B15
2A C260
C266
0.1uF
PZ1608U121-2R0TF

AVDD_DDR_VBN_A_1 10uF R206


C15 0.47uF C212 C294 C295 C251 C252 AVDDP3P3_MHL
10V 10K
AVDD_DDR_VBN_A_2
2A
C219

J19 1uF 1uF 0.47uF 0.47uF

G
AVDD_DDR_VBN_A_3 10V 10V 6.3V 6.3V
J20 0.47uF C213 L201
AVDD_DDR_VBN_A_4 PZ1608U121-2R0TF

D
AC30
AVDD_DDR_VBP_B_1 0.47uF C214 RUE003N02 C240 C241
AC31
AVDD_DDR_VBP_B_2 0.1uF 0.47uF
K24 Q200
6.3V
AVDD_DDR_VBP_B_3 0.47uF C215
L24 Close to chip side
AVDD_DDR_VBP_B_4 VDDP_NAND_A
0.1uF

AD31 +1.8V
AVDD_DDR_VBN_B_1
AD32 C216
AVDD_DDR_VBN_B_2 0.47uF L209
C221

L23 PZ1608U121-2R0TF
AVDD_DDR_VBN_B_3 Close to chip side
M24
AVDD_DDR_VBN_B_4 0.47uF C220
4th layer
2A C236
C239
0.1uF
10uF AVDD_AU33
10V

L219
PZ1608U121-2R0TF

C292
2A 0.47uF
6.3V

Close to chip side

THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES


SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FIRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS LM14A 2014-11-06
ESSENTIAL THAT ONLY MANUFACTURES SPECIFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC. MAIN2_POWER 2

Copyright © 2015 LG Electronics. Inc. All rights reserved. LGE Internal Use Only
Only for training and service purposes
DDR_VTT DDR_VTT

AR400 AR407
M0_DDR_VREFDQ 56 56
Hynix_DDR3_4Gb_29n Hynix_DDR3_4Gb_29n M0_1_DDR_VREFDQ 1/16W 1/16W
IC400 IC401 C424 0.1uF C453 0.1uF
M0_DDR_A14 M1_DDR_A14
H5TQ4G63AFR-RDC H5TQ4G63AFR-RDC M0_DDR_A8 M1_DDR_A8
M0_DDR_A11 M1_DDR_A11
EAN63053201 EAN63053201 C425 0.1uF C454 0.1uF
M0_DDR_A6 M1_DDR_A6
M0_DDR_A0
N3
A0 DDR3 VREFCA
M8
M0_DDR_A0
N3
A0
DDR3 VREFCA
M8
AR401 AR408
P7 P7 4Gbit 56 56
M0_DDR_A1 A1 4Gbit M0_DDR_A1 A1 1/16W 1/16W
P3 P3
M0_DDR_A2 A2 (x16) M0_DDR_A2 A2 (x16) C426 0.1uF C455 0.1uF
N2 H1 N2 H1 M0_DDR_A1 M1_DDR_A1
M0_DDR_A3 A3 VREFDQ M0_DDR_A3 A3 VREFDQ
P8 P8 M0_DDR_A4 M1_DDR_A4
M0_DDR_A4 A4 M0_DDR_A4 A4
P2 P2 M0_DDR_A12 M1_DDR_A12
M0_DDR_A5 A5 M0_DDR_A5 A5 C427 0.1uF C456 0.1uF
R8 L8 R400 240 R8 L8 R403 240 M0_DDR_BA1 M1_DDR_BA1
M0_DDR_A6 A6 ZQ M0_DDR_A6 A6 ZQ
R2 AVDD_DDR R2 AR402 AR409
M0_DDR_A7 A7 M0_DDR_A7 A7 AVDD_DDR
T8 T8 56 56
M0_DDR_A8 A8 M0_DDR_A8 A8 1/16W 1/16W
R3 B2 R3 B2 C428 0.1uF C457 0.1uF
M0_DDR_A9 A9 VDD_1 M0_DDR_A9 A9 VDD_1
L7 D9 L7 D9
M0_DDR_A10 A10/AP VDD_2 M0_DDR_A10 A10/AP VDD_2 M0_DDR_A13 M1_DDR_A13
R7 G7 R7 G7

DDR3 1.5V bypass Cap - Place these caps near Memory

DDR3 1.5V bypass Cap - Place these caps near Memory


M0_DDR_A11 A11 VDD_3 M0_DDR_A11 A11 VDD_3
N7 K2 N7 K2 M0_DDR_A9 M1_DDR_A9
M0_DDR_A12 A12/BC VDD_4 M0_DDR_A12 C429 0.1uF C458 0.1uF
A12/BC VDD_4 M0_DDR_A7 M1_DDR_A7
T3 K8 T3 K8
M0_DDR_A13 A13 VDD_5 M0_DDR_A13 A13 VDD_5
T7 N1 T7 N1 AR403 AR410
M0_DDR_A14 A14 VDD_6 M0_DDR_A14 A14 VDD_6 56 56
M7 N9 M7 N9 1/16W 1/16W
M0_DDR_A15 NC_5 VDD_7 M0_DDR_A15 NC_5 VDD_7
R1 R1 C430 0.1uF C459 0.1uF
VDD_8 VDD_8 M0_DDR_A2 M1_DDR_A2
M2 R9 M2 R9
M0_DDR_BA0 BA0 VDD_9 M0_DDR_BA0 BA0 VDD_9 M0_DDR_A5 M1_DDR_A5
N8 N8
M0_DDR_BA1 BA1 M0_DDR_BA1 BA1 M0_DDR_A3 M1_DDR_A3
M3 M3 C431 0.1uF C460 0.1uF
M0_DDR_BA2 BA2 M0_DDR_BA2 BA2 M0_DDR_A0 M1_DDR_A0
A1 A1
VDDQ_1 VDDQ_1 AR404 AR411
J7 A8 J7 A8
M0_D_CLK CK VDDQ_2 M0_D_CLK CK VDDQ_2 56 56
K7 C1 K7 C1 1/16W 1/16W
M0_D_CLKN CK VDDQ_3 M0_D_CLKN CK VDDQ_3 C432 0.1uF C461 0.1uF
K9 C9 K9 C9 M0_DDR_BA0 M1_DDR_BA0
M0_DDR_CKE CKE VDDQ_4 M0_DDR_CKE CKE VDDQ_4
D2 D2 M0_DDR_BA2 M1_DDR_BA2
VDDQ_5 VDDQ_5
L2 E9 L2 E9 M0_DDR_A15 M1_DDR_A15
M0_DDR_CS1 CS VDDQ_6 M0_DDR_CS2 CS VDDQ_6 C433 0.1uF C462 0.1uF
K1 F1 K1 F1 M0_DDR_A10 M1_DDR_A10
M0_DDR_ODT ODT VDDQ_7 M0_DDR_ODT ODT VDDQ_7
J3 H2 C410 0.1uF J3 H2 C440 0.1uF
M0_DDR_RASN RAS VDDQ_8 M0_DDR_RASN RAS VDDQ_8 AR405 AR412
K3 H9 C411 0.1uF K3 H9 C441 0.1uF 56 56
M0_DDR_CASN CAS VDDQ_9 M0_DDR_CASN CAS VDDQ_9 1/16W 1/16W
L3 L3
M0_DDR_WEN WE M0_DDR_WEN WE C434 0.1uF C463 0.1uF
J1 J1 M0_DDR_WEN M1_DDR_WEN
NC_1 NC_1
T2 J9 T2 J9 M0_DDR_CASN M1_DDR_CASN
M0_DDR_RESET_N RESET NC_2 M0_DDR_RESET_N RESET NC_2
IC100 L1 L1 M0_DDR_ODT M1_DDR_ODT
NC_3 NC_3 C435 0.1uF C464 0.1uF
LGE5332(LM14A) L9 L9 M0_DDR_RASN M1_DDR_RASN
NC_4 NC_4
F3 F3 AR406 AR413
M0_DDR_DQS0 DQSL SS_DDR3_4Gb_25n Hynix_DDR3_4Gb_25n M0_DDR_DQS2 DQSL SS_DDR3_4Gb_25n
Hynix_DDR3_4Gb_25n
G3 IC400-*1 IC400-*2 G3
IC401-*1
K4B4G1646D-BCMA IC401-*2 SS_DDR3_2Gb
IC401-*3
Hynix_DDR3_2Gb
IC401-*4
56 56
K4B4G1646D-BCMA H5TQ4G63CFR_RDC H5TQ4G63CFR_RDC
M0_DDR_DQS_N0 DQSL M0_DDR_DQS_N2 DQSL EAN63391401 K4B2G1646Q-BCMA H5TQ2G63FFR-RDC 1/16W 1/16W
EAN63391401 EAN63053202 N3 M8 EAN63053202

F17 H28 N3
P7
A0 VREFCA
M8 N3
P7
A0 VREFCA
M8 P7
A0
A1
VREFCA N3
P7
A0 VREFCA
M8
N3
EAN63667401
M8 N3
EAN63648701
M8
C436 0.1uF C465 0.1uF
M0_DDR_A0 IO[3]/A-A0[AB-A0]/A-A6 IO[75]/B-A0[CD-A0]/B-A6 M1_DDR_A0 C7 A9 P3
A1
A2
P3
A1
A2
C7 A9
P3
N2
A2
H1 P3
A1
A2
P7
A0
A1
VREFCA
P7
A0
A1
VREFCA
M0_DDR_CKE M1_DDR_CKE
C17 K31 M0_DDR_DQS1 DQSU
N2
A3 VREFDQ
H1 N2
A3 VREFDQ
H1

M0_DDR_DQS3
P8
A3
A4
VREFDQ N2
A3 VREFDQ
H1 P3
A2
P3
A2

M0_DDR_A1 IO[2]/A-A1[AB-A1]/A-A5 IO[80]/B-A1[CD-A1]/B-A5 M1_DDR_A1 VSS_1 P8


P2
A4
P8
P2
A4 DQSU VSS_1 P2
R8
A5
L8
P8
P2
A4
N2
P8
A3 VREFDQ
H1 N2
P8
A3 VREFDQ
H1

E17 J29 B7 B3 R8
A5
A6 ZQ
L8 R8
A5
A6 ZQ
L8 B7 B3 R2
A6
A7
ZQ R8
A5
A6 ZQ
L8 P2
A4
A5
P2
A4
A5

M0_DDR_A2 IO[8]/A-A2[AB-A2]/A-A8 M1_DDR_A2 M0_DDR_DQS_N1 DQSU VSS_2


R2
A7
R2
A7
M0_DDR_DQS_N3 DQSU VSS_2 T8
A8
R2
A7
R8
R2
A6 ZQ
L8 R8
R2
A6 ZQ
L8

M0_D_CLKN M1_D_CLKN
IO[83]/B-A2[CD-A2]/B-A8 E1
T8
R3
A8
B2
T8
R3
A8
B2
E1
R3
L7
A9 VDD_1
B2
D9
T8
R3
A8
B2 T8
A7
T8
A7

F18 K27 L7
A9 VDD_1
D9 L7
A9 VDD_1
D9 R7
A10/AP VDD_2
G7 L7
A9 VDD_1
D9 R3
A8
B2 R3
A8
B2
C437 0.1uF C466 0.1uF
M0_DDR_A3 IO[12]/A-A3[AB-A3]/A-A4 IO[79]/B-A3[CD-A3]/B-A4 M1_DDR_A3 VSS_3 R7
A10/AP
A11
VDD_2
VDD_3
G7 R7
A10/AP
A11
VDD_2
VDD_3
G7
VSS_3 N7
A11
A12/BC
VDD_3
VDD_4
K2 R7
A10/AP
A11
VDD_2
VDD_3
G7 L7
A9
A10/AP
VDD_1
VDD_2
D9 L7
A9
A10/AP
VDD_1
VDD_2
D9
M0_D_CLK M1_D_CLK
B18 K30 E7 G8 N7
T3
A12/BC VDD_4
K2
K8
N7
T3
A12/BC VDD_4
K2
K8 E7 G8 T3
A13 VDD_5
K8
N1
N7
T3
A12/BC VDD_4
K2
K8
R7
N7
A11
A12/BC
VDD_3
VDD_4
G7
K2
R7
N7
A11
A12/BC
VDD_3
VDD_4
G7
K2

M0_DDR_A4 M1_DDR_A4 M0_DDR_DM0 DML VSS_4


A13 VDD_5
VDD_6
N1 T7
A13
A14
VDD_5
VDD_6
N1
M0_DDR_DM2 DML VSS_4 M7
VDD_6
N9 T7
A13
A14
VDD_5
VDD_6
N1 T3
A13 VDD_5
K8 T3
A13 VDD_5
K8

IO[11]/A-A4[AB-A4]/A-BA1 IO[87]/B-A4[CD-A4]/B-BA1 D3 J2
M7
NC_5 VDD_7
N9
R1
M7
NC_5 VDD_7
N9
R1 D3 J2
NC_5 VDD_7
VDD_8
R1 M7
NC_5 VDD_7
N9
R1 M7
VDD_6
N1
N9
T7
M7
A14 VDD_6
N1
N9
E18 J28 M0_DDR_DM1 DMU
M2
VDD_8
R9 M2
VDD_8
R9
M0_DDR_DM3
M2
BA0 VDD_9
R9
M2
VDD_8
R9
NC_5 VDD_7
R1
NC_5 VDD_7
R1

M0_DDR_A5 IO[14]/A-A5[AB-A5]/A-A0 IO[86]/B-A5[CD-A5]/B-A0 M1_DDR_A5 VSS_5 N8


BA0 VDD_9
N8
BA0 VDD_9
DMU VSS_5 N8
M3
BA1 N8
BA0 VDD_9
M2
BA0
VDD_8
VDD_9
R9 M2
BA0
VDD_8
VDD_9
R9

A17 K32 J8 M3
BA1
BA2
A1
M3
BA1
BA2
A1
J8 J7
BA2
VDDQ_1
A1
A8
M3
BA1
BA2
A1
N8
M3
BA1
N8
M3
BA1

M0_DDR_A6 IO[10]/A-A6[AB-A6]/A-A1 IO[90]/B-A6[CD-A6]/B-A1 M1_DDR_A6 VSS_6 J7


CK
VDDQ_1
VDDQ_2
A8 J7
CK
VDDQ_1
VDDQ_2
A8
VSS_6 K7
CK
CK
VDDQ_2
VDDQ_3
C1 J7
CK
VDDQ_1
VDDQ_2
A8
BA2
VDDQ_1
A1
BA2
VDDQ_1
A1

D17 H31 E3 M1 K7
K9
CK VDDQ_3
C1
C9
K7
K9
CK VDDQ_3
C1
C9 E3 M1 K9
CKE VDDQ_4
C9
D2
K7
K9
CK VDDQ_3
C1
C9
J7
K7
CK
CK
VDDQ_2
VDDQ_3
A8
C1
J7
K7
CK
CK
VDDQ_2
VDDQ_3
A8
C1

M0_DDR_A7 M1_DDR_A7 M0_DDR_DQ0 DQL0 VSS_7


CKE VDDQ_4
VDDQ_5
D2
CKE VDDQ_4
VDDQ_5
D2
M0_DDR_DQ16 DQL0 VSS_7 L2
VDDQ_5
E9
CKE VDDQ_4
VDDQ_5
D2 K9
CKE VDDQ_4
C9 K9
CKE VDDQ_4
C9

IO[13]/A-A7[AB-A7]/A-A2 IO[78]/B-A7[CD-A7]/B-A2 F7 M9
L2
K1
CS VDDQ_6
E9
F1
L2
K1
CS VDDQ_6
E9
F1 F7 M9
K1
CS
ODT
VDDQ_6
VDDQ_7
F1 L2
K1
CS VDDQ_6
E9
F1 L2
VDDQ_5
D2
E9 L2
VDDQ_5
D2
E9
C16 J32 M0_DDR_DQ1 DQL1
J3
ODT VDDQ_7
H2 J3
ODT VDDQ_7
H2
M0_DDR_DQ17
J3
RAS VDDQ_8
H2
J3
ODT VDDQ_7
H2 K1
CS VDDQ_6
F1 K1
CS VDDQ_6
F1

M0_DDR_A8 IO[0]/A-A8[AB-A8]/A-A9 IO[77]/B-A8[CD-A8]/B-A9 M1_DDR_A8 VSS_8 K3


RAS VDDQ_8
H9 K3
RAS VDDQ_8
H9 DQL1 VSS_8 K3
L3
CAS VDDQ_9
H9
K3
RAS VDDQ_8
H9 J3
ODT VDDQ_7
H2 J3
ODT VDDQ_7
H2
AVDD_DDR
E16 G30 F2 P1 L3
CAS
WE
VDDQ_9

J1
L3
CAS
WE
VDDQ_9

J1
F2 P1 T2
WE
NC_1
J1
J9