Mole! REG —_— TV CHASSIS SERVICE MANUAL CONTENT (3) IC Function Introduction — 3.1 N201 TMPA8823. 3.2. N702 AN7522 3.3 _N740 TA1343N 3.4 N401A LA78040/STV9302A. — (4) PC Bus Control - 4.1 Menu Entry - 4.2,8823 BUS DATA (5) IC Voltage — (6) Trouble shorting.(1) General ‘This chassis is consists of main IC TMPA$823, AT24CO8A, LA78040(STV9302A/LA78041/TDABI77), (CD4033.TMP.A8823 is an integrated citeuit for a PAL-BG/I TV. A MCU and a TV signal processor (SP) are integraed in a 64 pin shrink DIP package. The MCU contains 8-bit CPU, ROM, RAM, V/O pors,timer/eounters, AID converters, an on-scteen display controller,emoter control interfaces, IIC bus interfaces. The TV signal processor gontains PIF, SIF, Video, multi-standard chroma,Sync, RGB processors, (@) Frame Chart (see fig.1) il vou (Eh son | stv9302 1LA78040 | SAW C ter HOUT ref Herve 7 | ns ae t asczs0 T*] pays9 1 TMPA8821/8823 r +| | RGB amp oxom rower |—> 110V 7220V]}) Kasqoms =» 25 KASQIIGS » 15 AV SW Liev cp4os3_| L_.| Aucio ANTS22 + TAIN | t TTT +4 DvD aviav2 av (S-Video) (3) IC Function Introducti ‘TMPA8823 consists of two pieces of IC chip in one package using Multi-Chip-Package(MCU) technology.One is a micro controller (MCU) and the other one isa signal processor (SP) for a colour TV. 23.1 N201 TMPA8823_Funetion: MCU and SP NO. Jean. Description 1_| sc. JIC bus serial clock input/output 2_| spa JIC bus serial data input/output 3_| key Key on wake up input 4_| uppvss Power Supply GND_ s__| Reser’ Reset signal input 6_|xour. ‘8 MHz oscillator connecting pins 7 [x 8 MHz oscillator connecting pins 3_| test GND connection 9_| uppvppsv) Power supply SV 10_| up vvss\ GND connection u_| tvaGNp GND terminal for Analog block [22_[ pp iv Input terminal for FBP 13_| nour Output terminal for Horizontal driving pulse 14_| HAFCI HAC filter connection is_|vsaw. ‘Terminal to be connected capacitor to generate V saw signal is_| v.our (Output terminal for Vertical driving pulse 17_| Hveci9vy ‘Vee terminal for DEF circuit is_[ Nc 19 | coin Input terminal for Cb signal 20 [vin Input terminal for Y signal 21 | crim ‘Input terminal for Cr signal 22_| TVDGND GND terminal for Digital block 23 [Cin Input terminal for Chroma signal 24 [vain Input terminal for ext Video signal 25_ [Tv pvec ‘Vee terminal for Digital block 26_[ TV IN in) Input terminal for video signal 27_| ABCL in Input terminal for ABLIACL control 28_| avour Output terminal for Audio singal 29_ | wFvccoV) ‘Vee terminal for IF circuit 30_| Tv our Output terminal for detected PIF signal 31_| sour Output terminal for detected SIF signal 32_[exrauN Input terminal for external audio signal 33_| sir Input terminal for 2nd SIF 34_[DCNF ‘Terminal to be connected capacitor for DC Negative Feedback 35_| PIFPLL ‘Terminal to be connected with loop filter for PIF PLL 36_| IF VeCSV} Vee terminal for IF circuit 37_| REG FIL. ‘Terminal to be connected capacitor for stabilizing internal bias 38_| DEEMPHA ‘Terminal to be connected capacitor for SIF Det De-Emphasis 39_ [race ‘Terminal to be connected IF AGC filter |40_[ir xp GND terminal for IF circuit 41_[ie Input terminal for IF signals 2 [rN Input terminal for IF signals 43_| RFAGC. Output terminal for RF AGC control level output 44_| ycvecy) Vee terminal for TV YiC cizeuit| 45_| BUS VIDEO SW __| Output terminal for CVBS or Y signal slected by BUS (Video SW) -