CHAPTER- 1

INTRODUCTION
1.1 Overview

Multilevel inverters are considerably indifferent to an ordinary inverter in

which only 2 levels will be generated. For producing single level only one single high
voltage switch is used. For producing multilevel voltage number of semiconductor
devices are used. In that each group of devices produces a step within the output
waveform of voltage. For obtaining a sinusoidal waveform the steps are increased.
For every level increment the number of switches involved is increased. Fig 1 shows
the block diagram of the general multilevel inverter

Fig.1.1 Block Diagram of Multilevel Inverter

Generally, when a voltage source usually capacitors voltage source applied to a

multilevel inverter an output wave form will be obtained. In the past twenty years,
number of multilevel voltage source converters are introduced. Few topologies are
more popular when compared with other topologies.

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1.2 Harmonics

Voltages or currents which are sinusoidal in nature having frequencies that are
whole multiples of the frequency at which the supply system is designed to operate
(e.g. 50Hz or 60 Hz) are called Harmonics,

Additional Definition and Origin:

Suppose a 250 Hz sine-wave signal is imposed onto the fundamental of mains
frequency 50 Hz, will be taken as the 5th harmonic or as 5th order harmonic (5 x 50
Hz). If a signal component has a frequency which is not an integer multiple of the
fundamental frequency will be taken as an inter harmonic component or simply
known as inter harmonic.
Harmonics and inter harmonics are resulted from modern developments in electricity
usage and the utilization of electronic power conditioning modules. For controlling
loads and to reduce the consumption of the power usage of power switching supplies
has been increased. But this resulted in developing of unwanted frequencies on the
supply voltage. The voltage with different frequencies needs to be avoided.

Potential Sources of Harmonics

•Switched mode power supplies
•Dimmer‘s
•Current Regulators
•Frequency Converters
•Voltage source inverters with pulse width modulated
converters
•Low power consumption lamps •Electrical arc-furnaces
•Arc welding machines
•Induction to motors with irregular magnetizing current associated with saturation of
the iron

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 1.3 Filters:-

For the proper operation of many electronic devices and circuits, few types of
filters are needed. So whenever developing an electronic circuit one should familiar
with filter circuits, and should know the specifications and values. Unfortunately,
most of the people working with electronic circuits lacks the knowledge on filters
because of less familiar with it, or might find it difficult with the maths portion
involved in the design of filters.
The intention of this Application Note is to give the introduction on filters and some
of the terms and concepts involved with them. It may not give full knowledge on
filter designer, but it can give a basic idea on the design of filter design.

1.4Types of Filters:-
Low-Pass:-
One of the types of filters is low-pass filter. A filter which allows low
frequency signals only and does not allow signals whose frequencies are above the filter's cut-
off frequency. The rearrangement of components of the above example as in Figure 1.2, the
resultant transfer function is:

Figure 1.2 Example of a Simple Low-Pass Filter

The transfer function with low frequency has more gain than with the high
frequency. As 0 approaches 0, HLP approaches 1; as 0 approaches infinity, HLP
approaches 0. Amplitude and phase response curves are shown in Figure1.3
It is always has negative slope, and others having ripple in the pass band and/or stop
band.

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When in a signal the high frequency components are to be removed a Low-pass filters
needs to be used. Let us consider an example, using a photo diode in a light sensing
instrument. The Photo diode can give very low output, if the levels of the light are
low. Its spectrum can be extended to a very high frequency by partly allowing it to an
uncertain noise and its amplifier. The level of the noise can be reduced to a maximum
level if a required signal is passed by having a high cutoff frequency and also placing
a low-pass filter at the amplifier output.

Figure1.3 Amplitude (a) and Phase (b) Response Curves for Example Low-Pass Filter

High-Pass:-
A filter which allows a signal with high frequency and rejects the signals which has
frequency below its cutoff frequency. It is opposite to a low-pass filter. A
rearrangement of the components to create high pass filter has been given below,
as in Figure 1.4 . The transfer function for this filter is:

Figure1.4. Example of Simple High-Pass Filter

The amplitude and the phase curves are shown in Figure 1.5 .the output from
a low-pass filter can be a “mirror image” to the output of a high-pass filter. Few more
examples responses of high-pass filter are shown in Figure 1.6, with

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the ``ideal'' response in (a) and the number of approximations to the ideal shown in
(b) through (f). Few applications does not need low frequency signal i.e. the low-pass
filters, in those applications High-pass filters can be employed. An example for that is
loudspeaker systems with high-fidelity. For example Music system contains energy
with high frequency vary from 100 Hz to 2 kHz, if a low-frequency signals are placed
at the input terminals may lead to the breakage of the high-frequency drivers.in order
to prevent this breakage of high-frequency drives mostly tweeters, A high-pass filter
placed between the broadband audio signal and the tweeter. This prevents the tweeter
breakage. A combination of low-pass filter and the high-pass filter is a component
known as a ``crossover network''.

Figure1.5. Amplitude (a) and Phase (b) Response Curves for Example High-Pass
Filter

1.5 Passive Filters:-

The filters which are discussed so far uses are a combination of passive
components: resistors, capacitors, and inductors, hence they are called as passive filters.
In other words a passive filter which contains no active or amplifying elements. As
Passive filters does have any active elements the power supply required by these filters is
zero. This is the one of the advantages of the passive filters. They can work with high
frequencies as there is no restriction on the bandwidth. Even though they are passive in
nature by adding active devices these can be employed with high voltages or currents. The
noise produced by the Passive filters is comparably low when compared with high-pass
filters. The only noise they can produce is thermal noise.

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This noise can also be reduced using the resistive elements, and, with the careful
design. In few applications Passive filters will not use any active elements, hence
cannot produce any signal gain. This has become a disadvantage for passive filters.
For some applications Input impedances may be less than required, and output
impedances may be higher than the optimum, therefore buffer amplifiers also need for
this purpose. For synthesizing the characteristics of passive filters there is a need of
Inductors, but these inductors are very expensive with higher accuracy. The physical
size of these inductors or higher values are taken. The spacing of the normal values of
inductors are not near, and it may become difficult to know the spacing within ten
percentage (10%) of any value, that is why adjustable inductors are generally used.
While producing large quantities using these filters may become costly and also time
consuming. Designing an advance passive filters not only difficult but also takes a lot
of time.

1.6 Active Filters:-

Amplifying components like operational amplifier, resistor and capacitor are used
by Active filters, in synthesizing the required filter characteristics. Active filters will have
high input resistance, low output resistance, and nearly any discretionary gain. Designing
an active filter is more easy, when compared with the design of passive filter. Not using
an inductor might be the one of the reasons as the need for dealing the issues about
inductor will not rise. As the capacitor is being used chances of arising issues related to
accuracy and value spacing. The amplifying components (such as op-amp ,capacitor)
gain-bandwidth product limits the performance at high frequencies, however the
operating range of the amplifier at every interval changes. Accuracy can be obtained by
using an active filter based on op amp, until the usage of low-tolerance resistors and
capacitors continues. As the usage of amplifying circuit some noise will be produced, but
this can be reduced by using some low noise amplifiers and the proper design of circuit.
The configuration of few common active filters. The second-order Sallen-Key low pass
filter in (a) may be used as a building block for higher order filters. Higher order filters
can be built depending on the number of filters connected in cascade. The more number
of filters the higher the order. The two resistors and two capacitors connected to the op
amp's non-inverting input and to VIN conform the filter's cutoff frequency and have an
effect on the Q.

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The gain of the filter is determined from the two resistors connected to the inverting
which also has affect on Q. Changes cannot be done independently on the gain and
cutoff frequency.
When a comparison made between the center frequency which is very low and gain-
bandwidth product of op-amp, temperature drifts and tolerance of external
components effects the active RC filters. For getting a predetermined results in
difficult filter circuits, an expensive filter circuits which have high accuracy and low
sensitivity to different temperatures have to be used. When the center frequency
multiplied with the filter's Q is greater than a small quantity of the gain-band width of
op-amp product, the ideal transfer function is different from the output of filter. Filter
topology depends on the degree of deviation, to minimize the effect of limited op amp
band width some topologies are designed.

Figure1.6. Examples of Active Filter Circuits Based on Op Amps, Resistors, and

Capacitors

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1.7 Total Harmonic Distortion:-

A forced impact on Power regulation and power consumption by the

distribution system power quality. Johan Lundquist of the Chalmers University of
Technology in Goteborg, Sweden put it best, stating “The phrase ‘power quality’ has
been wide used throughout the last decade and includes all aspects of events with in
the system that deviates from normal operation.” This has been come true when some
distortion is caused in the waveform by the new types of electronic power sources.
Hormonics will be contained in the waveforms which is distorted where a power
source act as non linear load. These harmonics may cause problems of interference in
the transmission lines and the conductor degradation motor and transformer
insulation. Therefore it is important to determine the overall impact of these
harmonics. The summation of all harmonics in a system is known as total harmonic
distortion (THD).This paper will attempt to explain the concept of THD and its effects
on electrical equipment. It will also outline the low THD of the Associated Power
Technologies (APT)line of programmable sources and how these can be used to more
effectively test equipment.

What is Total Harmonic Distortion?

Total harmonic distortion is a complex and often confusing to understand
concept. However when broken down into the basic definitions of harmonics and
distortion, it becomes more easier to understand.
Imagine a power system with an AC source and an electrical load (Figure 1.7).

Figure 1.7 Power System with AC source and electrical load

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 Now imagine that this load is going to take on one of two basic types: linear or
nonlinear. The type of load goes to have an effect on the power quality of the system.
This is due to the current draw of each type of load. Linear loads draw current that is
sinusoidal in nature so they generally do not distort the waveform (Figure 2). Most
household appliances are categorized as linear loads. Non-linear loads, however, can
draw current that is not perfectly sinusoidal (Figure 3). Since the current waveform
deviates from a sine wave, voltage waveform distortions are created.

Figure 1.8 Ideal Sine wave

Figure 1.9 Distorted Waveform

As may be determined from the waveform in Figure 3, waveform distortions
will drastically alter the shape of the sinusoid. However, no matter the level of
complexity of the fundamental wave, it is actually just a composite of multiple
waveforms called harmonics.
Harmonics have frequencies that are integer multiples of the waveform’s fundamental
frequency. For example, given a 60Hz fundamental waveform, the 2nd, 3rd, 4th and
th
5 harmonic components will be at 120Hz, 180Hz, 240Hz and 300Hz respectively. Thus,
harmonic distortion is the degree to which a waveform deviates from its pure sinusoidal
values as a result of the summation of all these harmonic elements. The ideal sine wave
has zero harmonic components. In that case, there is nothing to distort this

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perfect wave. Total harmonic distortion, or THD, is the summation of all harmonic
components of the voltage or current waveform compared against the fundamental
component of the voltage or current wave:
√ 2+ 2+ 2……..+ 2
THD= 2 3 4 *100
1

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 CHAPTER2
THE MULTILEVEL CONVERTER CONCEPT

2.1 . Introduction

Multilevel converters are power-conversion systems composed by an array of power

semiconductors and capacitive voltage sources that, once properly controlled and
connected, we can generate a multiple-step voltage waveform with controllable and
variable frequency, amplitude, and phase. The stepped wave is synthesized by choosing
completely different voltage levels generated by the proper connection of the different
capacitive voltage sources to the load. This connection is performed by the power
semiconductors with proper switching. The number of levels of a converter can be
defined as the number of steps or constant voltage values that can be generated by the
converter between the any arbitrary internal reference node and output terminal within the
converter. Typically, it is a dc-link node, and it is usually denoted by N and called neutral.
To be known as multilevel converter, every section of the converter should generate at
least 3 completely different voltage levels. This differentiates the classic 2 level voltage
supply converter (2L-VSC) from the multilevel family. Some single-phase examples of
this concept and their respective waveforms are given in Fig. 2.1 for different number of
levels. It is worth mention that, generally, the different voltage levels are equidistant from
each other in multiples of Vdc. Two-level converters can generate a variable frequency
and amplitude voltage waveform by adjusting a time average of their two voltage levels.
This is usually performed with pulse-width modulation (PWM) techniques. On the
another side, multilevel converters add a new degree of freedom, allows the use of the
voltage levels as an additional control element and giving a lot of alternatives to generate
the output waveform. For this reason, multilevel inverters have intrinsically improved
power quality, characterized by: lower voltage distortion (more sinusoidal waveforms),
reduced dv=dt, and lower common-mode voltages, which reduce or even eliminate the
need of output filters. When considering a three-phase system, the levels of one phase are
combined with those of the other phases, generating more different levels in the line-to-
line voltage. For a converter with np phase to neutral voltage levels, nll ¼ 2np -1 levels
can be found in the line-to-line voltage (a zero level is redundant). Something similar
happens in the

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three-phase load voltage, where combinations of the line voltages are produced,
obtaining n load ¼ 2nll -1 voltage levels. However, only np is used to refer to the
number of levels of the converter, since these are the levels generated by the converter
independently of the number of phases or the load connection type.

Figure 2.1 Converter output voltage waveform: a) two level, b) three level, c) nine
level.

Multilevel topologies provide a clever way of connecting switches in series,

thus enabling the processing of voltages that are higher than the device rating. The
industry need for the medium voltage drives has triggered considerable research in
this field, during this most applications include drives for pumps, compressors,
conveyors blower, and the like. In General, multilevel converters are effective means
that of reducing dv/dt of the output voltages and harmonic distortion, that makes this
technology applicable to utility interface and drives. There are a limited number of
topologies that can provide multilevel voltages and also suitable for medium voltage
applications. The most known topologies are the neutral-point clamped (NPC)
multilevel converters, the flying capacitor (FC) multilevel converters, and also the
cascaded H-bridge multilevel converters. Alternative topologies like the hybrid
converters have been proposed as well, however they are not absolutely accepted for
industrial applications. The NPC multilevel converter shown in Fig2.2 (a) is a natural

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extension of the three-level converter presented by Nabae. As is seen, the multilevel
NPC converter needs multiple clamping points to synthesize the various voltage
levels across the output. The drawback of multiple clamping points could be a
limitation on the maximum modulation index that is allowed with active power to
assure voltage sharing across all of the dc link capacitors. Another disadvantage of the
multilevel NPC converter is the need for series connection of the clamping diodes.

Power quality is one of the main concerns for the wind Power conversion in
DG systems. A successful operation of grid-connected WT systems is needed to fulfill
the harmonic limit mandated by utility standards. Therefore, passive grid filters are
usually required. But for high power ranges, they are costly, heavy and bulky, and
have the potential resonant risk. In this, a new nine-level ANPC (9L ANPC) converter
is proposed for the grid-side converter of large WTs in DG systems. The aim of this
new topology is to boost the wave and power quality, and therefore reduce or may be
fully taken away the passive grid filters to obtain a filter less grid connection, that
allows to decrease the price, and power density, reliability and increase the efficiency
of the WT system in DG. The topology, operating principles, control strategies, and
characteristics of the proposed converter are analyzed in detail. The method of
floating capacitor voltage balance, which is based on redundant switching states and
capacitor prioritization information, is presented. The hybrid converter concept and
consideration of semiconductor device selection are discussed. The comparison
between the proposed topology and other existing conventional and ANPC 9L
topologies are summarized to illustrate the feature and performance of the new 9L
ANPC converter. The proposed converter is studied in the case of the grid connection
for a 6-MW WT system without using passive grid filters in DG. Simulation and
experiment results are presented to validate the proposed converter concept and
control schemes. The proper operation and fulfillment of harmonic limit standards of
the filter less grid-connected large WT system are verified by simulation results.

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Figure2.2 (a) NPC, (b) floating capacitor, and (c) cascaded H-bridge and basic cell

2.2 Over View of Multilevel Inverters

At first this chapter introduces the basic converter theory of power electronics.
Then three mostly used multilevel inverter topologies and their basic operations as well
as their relative advantages and disadvantages are presented. Finally some very simple
modulation techniques used to control the output voltages of multilevel inverter are
briefly described. The multilevel power conversion has been receiving increasing
attention with in the past few years for large power application. Various topologies are
introduced and studied extensively for utility and drive applications with in the recent
literature. These converters are suitable in high voltage and high power applications due
to their ability to synthesize waveforms with higher harmonic spectrum and attain

14
higher voltage with a limited maximum device rating. There are various current
control methods for two-level converters. Hysteresis control of power converters,
based on instantaneous current errors, is wide used for the compensation of the
distribution system because it has good robustness and dynamic characteristics
against the parameter variations and non-linarite loads.

2.3Unified Converter Theory

In the previous analysis “Switching Power Converters”, Wood introduces the

concept of a unified converter theory. There he states: “Most traditional views of the
field have seemed somewhat disjointed; converters were largely regarded as related
only because they all use semiconductor switches and have certain topological
similarities. the view expounded herein (is that) switching power converters are
related by function and behavior; their basic characteristics do not in any way depend
on the types of switches used, nor on the applications to which they are put, nor on
the topologies in which they are realized”.

According to this unified theory, any power electronic converter can be viewed as a
matrix of switches which connects its input nodes to its output nodes. These nodes
may be either DC or AC, and either inductive or capacitive; and the power flow may
be in either direction.

Two obvious restrictions are enforced by some basic laws of electricity.

1) If one set of nodes (input or output) is inductive, the other set must be
capacitive, so as not to create a cut set of voltage or current sources when the
switches are closed.
2) The combination of open and closed switches should never open circuit an
inductor, or short circuit a capacitor.

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2.4 Inverter Or Rectifier/Voltage Source Or Current Source

This unified set of converters is generally broken into a number of subsets. The term
rectifier is used when the power flow is predominately from the AC port to the DC port
and also the term inverter is used when power flow is predominately from the DC port to
the AC port. The term converter is used once when there is no predominant direction of
power flow or as a general term to encompass both inverters and rectifiers.

In a Voltage Source Converter (VSC), the DC port is the capacitive port and is
voltage stiff (i.e. a large DC bus capacitor). The voltages in such a converter are well
defined by this port and are generally considered independent of the converter’s
operation. The value of the AC side inductance is comparatively small and modulation of
the converter controls these AC side inductor currents. Should the voltage source
converter be responsible for the control of the DC bus capacitor voltage, then this voltage
is indirectly controlled by controlling the net current flow in the capacitor. The switches
in such a converter must block a unidirectional voltage, but be able to conduct current in
either direction if bidirectional power flow is desired.

The converse is true in a Current Source Converter (CSC) — the DC port is

inductive and current stiff. The current in this port (and hence the converter) is well
defined and slow to change. The voltage (particularly at the AC port) is considered
the variable directly controlled by the converter modulation. Since the AC port
usually has significant line or load inductance, line to line capacitors must be placed
on the AC port. The switches must block either voltage polarity, but are only required
to conduct current in one direction.

Since the AC line and AC motor loads are both inductive, Voltage Source
Rectifier Inverter cascades are usually used for small and now increasingly for large
motor drives and similar applications, as GTOs and IGBTs have matured. Larger
converters have traditionally been current source converters, both because this best
suits the characteristics of the thyristors and because it requires a large DC bus
inductor, which was preferred to a large capacitor.

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2.5 Conventional Two-Level And Three-Level Voltage Source Inverter

Switch-mode dc-to-ac inverters are used in ac power supplies and ac motor

drives where the objective is to produce a sinusoidal ac output whose magnitude and
frequency can both be controlled. Practically, we use an inverter in each single-phase
and three-phase ac systems. A half-bridge is that the simplest topology, that is used to
provide a two level square-wave output waveform. A center-tapped voltage supply is
required in such a topology. It may be possible to use a simple supply with two
compatible capacitors in nonparallel to produce the center tap.

The full-bridge topology is used to synthesize a three-level square-wave output

waveform. The full bridge and half bridge configurations of the single-phase voltage
source inverter are shown in Fig. 2.3 and 2.4, respectively.

Figure 2.3 Half-bridge configurations

Figure 2.4 Full-bridge configuration

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 In a single phase half-bridge inverter, only two switches are required. To avoid shoot
through fault, both switches are never turned on at the similar time. S 1 is turned on and S2
is turned off to provide a load voltage, V AO in Fig.2.3, of VS/ 2. To complete one cycle, S 1
is turned off and S2 is turned on to provide a load voltage, V AO, of -VS/ 2.

In full-bridge configuration, turning on S 1 and S4 and turning off S2 and S3

provides a voltage of VS between the point A and B (V AB) in Fig. 2.4, whereas turning off
S1 and S4 and turning on S2 and S3 provides a voltage of –VS. To get zero level in a full-
bridge inverter, the combination can be S 1 and S2 where as S3 and S4 off or contrariwise.
The 3 possible levels referring to above discussion are shown in Table 1.

Conducting Switches Load Voltage VAB

S1, S4 +VS

S2, S3 -VS

S1, S2 or S3, S4 0

Table 2.1 Load voltage with corresponding conducting switches

Note that S1 and S3 must not be closed at the similar time, nor should S 2 and S4.
Otherwise, a short circuit would exist across the dc supply. The output wave form of
full bridge and half bridge of single-phase voltage source inverter are shown in Fig.
1.6 and 1.5, respectively.

Figure 2.5 Output waveform of half-bridge configuration

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 Figure 2.6 Output waveform of full-bridge configuration

2.6 Multilevel Voltage Source Inverter

A multilevel inverter can switch either its input or output nodes (or both)
between multiple (more than two) levels of voltage or current. The multilevel voltage
source inverter is recently applied in several industrial applications like as drive
systems, static VAR compensators, and ac power supplies etc. One of the significant
advantages of multilevel configuration is that the harmonic reduction within the
output wave form without decreasing the inverter power output or increasing
switching frequency. The output voltage waveform of a multilevel inverter is
composed of the number of levels of voltages, usually obtained from condenser
voltage sources. The so-called multilevel starts from three levels. As the number of
levels reach infinity, the output THD approaches zero. The number of the achievable
voltage levels, however, is restricted by voltage unbalance issues, circuit layout,
packaging constraints and voltage clamping requirement.

Here, three mostly used voltage synthesis-based multilevel inverters are

introduced, i.e.

1) Diode-Clamped Multilevel Inverter.

2) Flying-Capacitor Multilevel Inverter.
3) Cascaded-Inverters with Separated DC Sources.

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2.6.1. Diode-Clamped Multilevel Inverter (DCMI)

The diode-clamped multilevel inverter uses capacitors in series to divide up

the dc bus voltage into a group of voltage levels. To produce m levels of the phase
voltage, an m level diode-clamp inverter requires m-1 capacitors on the dc bus. A
single phase 5 level diode clamped inverter, which can produce a nine-level phase to
phase voltage waveform, is shown in Fig. 2.7.

Figure 2.7 A single-phase five-level diode-clamped inverter

The dc bus consists of 4 capacitors, i.e., C 1, C2, C3, and C4. For a dc bus voltage
Vdc, the voltage across the every capacitor is V dc/4, and every device voltage stress will
be restricted to one capacitor voltage level, V dc/4, through clamping diodes. DCMI output
voltage synthesis is relatively straightforward. To explain however the staircase voltage is
synthesized, point O is considered as the output phase voltage reference point. Using the
five-level inverter shown in Fig. 1.7, there are five switch combinations to generate five
level voltages across A and O. Table 2 shows the phase voltage level and their
corresponding switch states. Within the Table, state one represents that the switch is on,
and state zero represents the switch is off. There exist four complementary switch pairs in
every phase, i.e., S1-S5, S2-S6, S3-S7 and S4-S8.

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 Output Switch State

VAO S1 S2 S3 S4 S5 S6 S7 S8

V5=Vdc 1 1 1 1 0 0 0 0

V4=3Vdc/4 0 1 1 1 1 0 0 0

V3=Vdc/2 0 0 1 1 1 1 0 0

V2=Vdc/4 0 0 0 1 1 1 1 0

V1=0 0 0 0 0 1 1 1 1

Table 2.2 Diode-clamped five-level inverter voltage levels and their switch states

However, it seems to have many disadvantages, particularly when extended

beyond three level topology. Many of these issues in practice limit the diode-clamped
topology to a maximum of five levels:

Although the transformer can be eliminated, extra components (diodes) are required
to ensure load current continuity. The number of extra components rises sharply as
the number of levels increase.
1) These extra components do not necessarily ensure equal voltage sharing for all
switches.
2) Switch utilization is not equal, outer switches receiving a lower average load.
This becomes particularly apparent as the number of levels increase and the
modulation depth is small.
3) Similarly, the power flows to and from the different capacitors in the capacitor
string are not balanced.
4) Not all switch states are allowed. The disallowed states must be re-mapped to
their equivalent allowed states.
5) Different equivalent states slew the capacitor voltages in different directions.
This should be used to control the capacitor voltages.
For the above reasons, a more complicated, dedicated modulation strategy must be
used, which has been specifically tailored to the topology of the converter.

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2.6.2. Flying-Capacitor Multilevel Inverter (FCMI)

Probably the most important multilevel topology to appear recently is the

flying capacitor inverter, or imprecated cells multilevel inverter, proposed by
Maynard and Foch. A FCMI shown in Fig.2.8 uses a ladder structure of dc side
capacitors where the voltage on each capacitor differs from that of the next capacitor.
To generate m-level staircase output voltage, m-1 capacitors in the dc bus are needed.
Each phase-leg has an identical structure. The size of the voltage increment between
two capacitors determines the size of the voltage levels in the output waveform.

Figure 2.8A single-phase five-level flying-capacitor inverter

Here the switch pair-capacitor ‘cell’ is isolated and inserted within a similar
cell hence the term imprecated cells inverter. This inner pair of switches and their
associated capacitor now ‘flies’ as the outer pair of devices switch. The combination
of conducting switches and capacitors ensures that the voltage across any blocking
switch is always well defined. Table 3.3 shows the switch combination of the voltage
levels and their corresponding switch states. In fact, there is more than one
combination to produce output voltages V2, V3, and V4. That makes the FCMI more
flexibility than DCMI.

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 Output S1 S2 S3 S4 S5 S6 S7 S8

VAO

V5=Vdc 1 1 1 1 0 0 0 0

V4=3Vdc/4 1 1 1 0 0 0 0 1

1 1 0 1 0 0 1 0

1 0 1 1 0 1 0 0

0 1 1 1 1 0 0 0

V3=Vdc/2 1 1 0 0 0 0 1 1

1 0 1 0 0 1 0 1

1 0 0 1 0 1 1 0

0 1 1 0 1 0 0 1

0 1 0 1 1 0 1 0

0 0 1 1 1 1 0 0

V2=Vdc/4 1 0 0 0 0 1 1 1

0 1 0 0 1 0 1 1

0 0 1 0 1 1 0 1

0 0 0 1 1 1 1 0

V1=0 0 0 0 0 1 1 1 1

Table 2.3 Switch combination of the voltage levels and their corresponding switch
states

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The flying capacitor family of converters appears very attractive:

1) The flying capacitor concept can be applied to a number of different converter

types - current or voltage source, DC-DC, DC-AC or AC-AC.
2) Any switch combination is valid and ensures voltage sharing, so long as
switch pairs receive complementary drive signals. Most modulation strategies
are easily applied to this topology simply by phase shifting the drive signals.
3) The voltages of the capacitors are automatically balanced by this conventional
modulation strategy. If desired, the capacitor voltages can be actively
controlled by an appropriate modification of the control signals.
4) The load is by default equally shared among the switches.
5) The topology is modular and not reliant on a transformer.

There are some significant disadvantages, which are not at first apparent:

1) The topology requires a lot of high voltage capacitors — many more than
other topologies. These capacitors need to conduct the full load current for at
least part of the switching cycle. Fortunately, if the switch frequency is high,
these capacitors can usually be relatively small in capacitance value.
2) Since these capacitors initially have zero voltage across them, starting the
converter safely may be a non-trivial task.
3) The topology is not inherently fault tolerant.

2.6.3 Cascaded-Inverters with Separated DC Sources

The last structure introduced here is a multilevel inverter, which uses

cascaded inverters with separate dc sources (SDCSs). The general function of this
multilevel inverter is the same as that of the another two previous inverters. The
multilevel inverter using cascaded-inverter with SDCSs synthesizes a desired voltage
from many independent sources of dc voltages, which can be obtained from the
batteries, solar cells or fuel cells. This configuration recently becomes more popular
in adjustable speed drive and ac power supply applications. This inverter can avoid
extra clamping diodes or voltage balancing capacitors. A single phase two cell series
configuration of such an inverter is shown in Fig2.8

24
 Figure 2.9 Single-phase structure of a two-cell cascaded inverter.

Each SDCS is associated with a single-phase full-bridge inverter. The ac

terminal voltages of different level inverters are connected in series. By different
combinations of the four switches, S1-S4, every inverter level will generate three
completely different voltage outputs, +Vdc, -Vdc, and zero. The ac output of each of
the different level of full-bridge inverters are connected in series such that the
synthesized voltage waveform is that the sum of the inverter outputs. Note that the
number of output phase voltage levels is defined in different way from those of two
previous inverters. In this topology, the number of output phase voltage levels is
defined by m=2s+1, where s is the number of dc sources

Table 2.4 Two-cell cascaded-inverter voltage levels and their switch states.

Output S1 S2 S3 S4 S5 S6 S7 S8

VAO

V5=2Vdc 1 0 0 1 1 0 0 1

V4=Vdc 1 0 0 1 1 0 1 0

V3=0 0 0 0 0 0 0 0 0

V2=-Vdc 0 1 1 0 0 1 0 1

V1=-2Vdc 0 1 1 0 0 1 1 0

25
This multilevel converter structure has some very significant advantages, if its
limitations are acceptable. Its advantages are:

1) It has perhaps the simplest architecture and the lowest component count. No
transformer is needed, so capital costs are low.
2) Again, the converter is very modular and easy to understand. This applies not
only to its structure, but also to its control.
And the limitations are:

1) There is only limited access to DC bus capacitors, which limits its area of
application to either those with only reactive power flow, or those where the
power source or load can be both modular and isolated.
2) Should a module fail (or be removed), it must fail short circuit, or be bypassed.
The converter can continue to operate, at full current capacity, but at reduced
voltage rating. These will in practice mean that if fault tolerance is required, the
converter will need a more conservative voltage rating — a potential cost
penalty.
2.7 H – Bridge Inverter
“H” topology has several redundant combinations of switches positions to
produce the similar voltage levels. As an example, the level “zero” is generated with
switches in position S1 and S2, or S3 and S4, or S5 and S6, and so on.

Another characteristic of “H” converters is that they only produce an odd number of
levels, which ensures the existence of the “0V” level at the load .For example, a 51-
level inverter using an “H” configuration with transistor-clamped topology needs 52
transistors, but when using a single leg only 25 power supplies instead of the 50
required. Therefore, the problem related with increasing the number of levels and
complexity and reducing the size has been partially solved, since power supplies have
been decreased to 50%.

The single-phase H – Bridge of cascaded inverter. The ac terminal voltages of every

bridge are connected in series not like the diode clamp or flying capacitors inverter,
the cascaded inverter does not need any voltage-clamping diodes or voltage balancing
capacitors.

26
 This configuration is more preferable for constant frequency applications like
active power filters, active front-end rectifiers and reactive power compensation. In this
case, the power supply could also be voltage regulated dc capacitor. The circuit diagram
consists of 2 cascade bridges. The load is connected in such the way that the sum of
output of these bridges can seem across it. The ratio of the power supplies between the
auxiliary bridge and therefore the main bridge is 1:3. One of the important characteristic
of multilevel converters using voltage step up is that switching frequency and electric
power distribution are present advantages for the implementation of these topologies.

2.8 Multilevel Current Source Inverter

The inverters which were focused upon in the previous section were voltage
source inverters, with multilevel voltage waveforms. These inverters divide the total
input voltage among a number switches, and allow a reduction of the voltage
harmonics. As mentioned, these are the most commonly used and best understood
multilevel inverters. As we broaden the scope of multi-level again, it is important to
see the distinction between these two aspects of a multilevel inverter — the
application of the inverter (voltage source or current source) and the internal
topology of the inverter (multilevel voltage or multilevel current).

If the capacitive port were an AC port and the inductive port current stiff and DC,
then this would be classified as a current source, multilevel current inverter. Two
multilevel current inverters are shown in Fig 2.10 and 2.11 below. In both of these
examples they present a multilevel current waveform to the capacitive port. The
voltage rating of the inverter is limited to that of the switches, however, the input
current is divided between the multiple switches.

27
 Figure 2.10 The flying inductor inverter – multilevel current inverter

Figure 2.11The isolated flying bridge inverter – formed from current source bridges
placed in parallel.

Current source inverters have a number of advantages:

1) Current is well controlled — short term over-current protection is inherently

provided by the DC bus inductor; long term by the current control loop.

2) The DC bus energy storage component is a large inductor, rather than a large
capacitor. A large power inductor is arguably simpler, cheaper and most
importantly, more reliable.
3) Current source inverters are suited to the high power devices such as thyristors
and GTOs, which can block voltage in either direction, but conduct current
only in the forward direction.
4) Soft switching is either intrinsic to such devices, or easily ensured.

28
Equally, they have disadvantages:

1) Inductors have higher losses than capacitors.

2) Switch voltages are poorly defined. Most semiconductor switches tolerate
transient over-current better than transient over-voltages.
3) There are more potential resonance problems in input and output filters than
for voltage source.
4) When used as a back to back rectifier inverter pair, a more complex and
expensive controlled rectifier with closed loop control is required as a current
source. An uncontrolled diode rectifier is often suitable for voltage source
converters.
Voltage source inverters have become the dominant configuration, even at high
power levels. The direction of semiconductor technology has reflected this, with
asymmetrical or reverse conducting thyristors (RCTs) and GTOs being developed
specifically for VSC rather than CSC applications.

29
 CHAPTER- 3

CONTROL TECHNIQUES FOR MULTILEVEL VOLTAGE

SOURCE INVERTERS

3.1 Introduction

From the past few decades we have been studying the two level inverters Pulse
Width Modulation (PWM) techniques. The following are the agenda to be achieved using
Multiple PWM methods. They are wide linear modulation range, reduced switching loss,
less total harmonic distortion in the spectrum of switching waveform, simple
implementation, less memory space and less computation time. The carrier based PWM
(sine-triangle PWM or SPWM) technique and the space vector based PWM technique are
the most popular pulse width modulation techniques. The space vector based PWM
(SPWM) technique is very easy to implement, but the maximum peak of the fundamental
component in the output voltage is limited to 50% of the DC link voltage and the
extension of the SPWM schemes in the over-modulation range is difficult. In SVPWM
schemes, a reference space vector is sampled at regular intervals for determination of the
inverter switching vectors and their time durations in a sampling interval. A space phasor
based PWM scheme for multi-level inverters requires the instantaneous amplitudes of
reference phase voltages. The SVPWM scheme presented for multi-level inverters can
also work in the over-modulation range, using only the instantaneous amplitudes of
reference phase voltages. In the recent days the multilevel power converters have gain
more interest in the field of high voltage and high power applications field in industries.
The multilevel inverter approach allows the use of high power and high voltage electric
motor drive systems. Using the multilevel inverter concept, a divide and conquer
approach offers more flexibility and control over the discrete components that makeup
the system. For high voltage applications two or more power devices will be connected in
series to achieve the specified voltage ratings and in parallel to obtain the current ratings.
Multilevel inverters can increase the power by (m-1) times than that of 2 level inverter
through the series connection of power semiconductor devices. This work focuses on the
different control strategies and a suitable modulation strategy is selected based on the
outputs obtained through the simulations on the MATLAB SIMULINK software
environment.

30
Based on the applications of PWM signals to multilevel inverters, the multilevel
sinusoidal PWM can be classified according to carrier and modulating signals as
shown in Figure 3.1.

Sinusoidal Pulse

Modulating Signal Carrier Signal

Pure Sinusoidal Phase Disposition

Third Harmonic Phase Opposition

Dead Band Alternate POD

Other Techniques Hybrid (H)

Phase Shift (PS)

Superimposed

Figure 3.1 Classification of SPWM

3.2 Multicarrier PWM Techniques

Multicarrier PWM techniques does the natural sampling of a single

modulating or reference waveform (sinusoidal) which are same as that of output
frequency of the inversion system, through several carrier signals ( triangular
waveforms) of higher frequencies of several kilo Hertz discussed by McGrath et al
(2002) and Samir Kouro et al (2008). They can be categorized as follows.

31
 3.2.1Alterative Phase Opposition Disposition (APOD)
This technique needs each of the (m – 1) carrier waveforms, for an m-level
0
phase waveform, to be phase displaced from each other by 180 alternately as
shown in Figure 3.2. The important harmonics are centered in sidebands around
the carrier frequency fc and hence there will be no harmonics occur at fc.

Magnitude (pu)
(Seconds)Time

Figure 3.2 APOD carrier technique

3.2.2 Phase Opposition Dispositions (POD)

Taking the zero as the reference the graph shows the carrier waveform
0
will be above or below the reference value, but these waveforms will be in 180 phase
shift which is shown in Figure 3.3. The significant harmonics are located around the
carrier frequency fc for both the phase and line voltage waveforms. The three
disposition PWM techniques that are APOD, PD and POD generate similar phase and
line voltage waveforms. For all these techniques, the average frequency of the
decision signals is lower than the carrier frequency.

Figure 3.3 POD carrier technique

32
3.2.3 Hybrid (H)
It is a combine technique of disposition method and phase shifted multicarrier
technique. The bands are used for only two modulations, however, every time the lthe
power converter levels are increased, and phase shifted and more triangular carriers
are introduced accordingly. The two carriers above zero have the same frequency f c
0
and the same peak to peak value. However, there is an 180 phase shift between them.
The same applies for the two carriers below zero within the case that the number of
0
converter levels is higher, the carriers are phase shifted accordingly, that is 120 for a
0
seven level system and 90 for a nine level system and so on and so forth.
Here, the significant harmonics are mainly concentrated around multiples of (m
- 1)/2 of the carrier frequency fc. As an example, for a five level converter, the
harmonics are located around 2fc, for a seven level around 3f c and for a nine level
around 4fc. The gap between the fundamental and the first significant harmonics
increases accordingly as shown in Figure3.4.

Figure 3.4 H carrier technique

33
Modulating Signal

Sinusoidal PWM is the most widely accepted PWM technique, where a

triangular wave is compared with a sinusoidal reference known as the modulating
signal, shown in Figure 3.5.

Figure 3.5 Pure sinusoidal modulating signal control technique

3.3 Third Harmonic Injection PWM (THIPWM)

This method to increase the gain of the pulse width modulator in a

multilevel inverter to inject a third harmonic. This method is derived from
conventional sinusoidal PWM with the addition of a 17% third harmonic component
to the sine reference waveform as shown in Figure 3.7. Here the 15% increase in gain
over the SPWM technique is achieved at the cost of introducing third harmonics on
the line to neutral waveforms. However for a balanced load with a floating neutral
point, third harmonic current can not flow and therefore third harmonic voltages are
not present on the line to line wave forms. Although, the above mentioned switching
patterns for PWM converters provide increased gain compared with the conventional
SPWM technique, they also imply the reference or modulating waveforms have to be
continuous regardless of their shape.

As a result they do not provide any reduction in switching frequency

compared with the SPWM. For third harmonic injection PWM, the reference
waveform is defined as f(ω,t)=1.15Masin(ωot) + 0.19Masin(3ωot); 0≤ωot≤ 2π Where,
Ma is the modulation index ratio. The zero sequence voltage can be expressed as,

34
 Vzero=[max(Va,Vb,Vc)+min(Va,Vb,Vc)]/2

Figure 3.6 Third harmonic injection modulating signal control technique

A modulation scheme is presented by Aziz et al (2004), where a fixed common mode

voltage, is added to the reference phase voltage throughout the duration range. It has
been shown that this common mode addition will not result in a SVPWM like
performance, as it will not center the middle inverter vectors in a sampling interval.

3.4 Proposed Multilevel Inverter

Cascaded Multilevel Inverters

It is one of several multilevel configurations. It is formed by connecting

several single phase H-bridge inverters in series as shown in Figure. Each H-bridge has its
own is DC source. Each separated DC sources is connected to H-bridge inverter and can
produce voltages of 0, +V and –V, where V is the voltage of the DC bus.

Each inverter generates quasi-square wave voltage wave form with completely different
duty cycle ratios, which together form the staircase output voltage wave form as shown in
Figure 3.7. The synthesized voltage waveform is the sum of the inverter outputs. The
number of output phase voltage levels in a cascade multilevel inverter is then 2s+1, where
s is the number of isolated dc sources. A CHB multilevel inverter consists of single phase
H-bridge circuits in series connection. High modularity degree is easily achieved due to
the use of individual bridges in terms of circuitry, control and modulation. This modular
structure grants CHB configuration higher voltage and power levels as well as more
reliable and easy maintenance compared with other common multilevel inverters such as
diode clamped and flying capacitor types.

35
 Figure3.7 a) Configuration of an individual leg b) Output phase voltage waveform

The number of switching angles or DC link voltages (L) determines the number of
levels associated with the output voltage waveform which is equal to 2L+1. For
example, with three modules (L=3), a 7-level output voltage will be generated.
Individual switches in the H-bridges change their status at most two times per
fundamental waveform cycle. Corresponding output phase voltage of CHB inverter is
depicted in Figure. This waveform consists of six particular variables including
switching angles (θ1, θ2 and θ3) along with asymmetrical DC levels (Vdc1, Vdc2 and
Vdc3). The output voltage signal is set according to Fourier series expansion.

36
 = 1/ [ 1(cos 1) + 2(cos 2) + … … … + (cos )] (1)
Along with (1), for a 7-level inverter, five other equations can be expressed with the
purpose of mitigating 2L-1 harmonics given by
= 1/3[ 1(cos 1) + 2(cos 2) + 3(cos 3)] 0=[ 1(5 cos 1) + 2(5 cos 2) + 3(5cos 3)] 0=[
1(7cos 1) + 2(7cos 2) + 3(7cos 3)] 0=[ 1(11 cos 1) + 2(11cos 2) + 3(11 cos 3)] 0=[ 1(13 cos
1) + 2(13 cos 2) + 3(13cos 3)] 0=[ 1(17 cos 1) + 2(17cos 2) + 3(17 cos 3)]

The self-suppressing feature of zero-sequence harmonics in three phase systems

gives a computational advantage as no additional measure with respect to these harmonic
components is necessary. Transcendental equations can be solved subsequently through
applying an appropriate optimization algorithm to obtain desired solutions

S.NO CONDUCTING SWITCHES AMPLITUDE OF THE OUTPUT

VOLTAGE
1 S2,S7,S3 +Vdc
2 S2,S7,S4 +2Vdc
3 S2,S7,S5 +3Vdc
4 - 0
5 S1,S6,S3 -Vdc
6 S1,S6,S4 -2Vdc
7 S1,S6,S5 -3Vdc

Table3.1 Switching Conditions

37
3.5 Proposed Multilevel Inverter Simulink Diagram

A CHB multilevel inverter consists of single phase H-bridge circuits in series

connection. High modularity degree is easily achieved due to the use of individual
bridges in terms of circuitry, control and modulation. This modular structure grants CHB
configuration higher voltage and power levels as well as superior reliability and easy
maintenance compared with other common multilevel inverters such as diode clamped
and flying capacitor types. The number of switching angles or DC link voltages (L)
determines the number of levels associated with the output voltage waveform which is
equal to 2L+1.For example, with three modules (L=3), a 7-level output voltage will be
generated (see Fig.3.9). Individual switches in the H-bridges change their status at most
two times per fundamental waveform cycle. This waveform consists of six particular
variables including switching angles (θ1, θ2 and θ3).where Vn is the magnitude of nth
harmonic. Switching angles are in the range of 0 to π/2 (0≤ θi <π/2) while voltage levels
are left free to float between per unit values of 0 to 1. The even order components are
equal to zero for such quarter-wave symmetrical signals.

Figure 3.8 Simulink Model of Seven Level Cascaded Multilevel Inverter

38
3.6 Simulation results of Preposed CHB MLI

In proposed seven level cascaded multilevel inverter we obtained seven level

rd
output as shown in the below figure.We obtain the high amount of 3 order harmonic
componenent compared with other order components.As we know that lower order
harmonics have the most dominent role in outputwave distortion, So the total THD
value of the normal seven level cascaded H-bridge multilevel inverter was 21.705%.

Figure 3.9 Simulated phase voltage waveform and their corresponding frequency
spectrum

39
 rd th
So, in order to reduce the most dominant lower order harmonics (3 ,5 ,and
th
7 ) the proposed PSO approach reduces the computational burden to find the optimal
solution compared With iterative methods and the resultant theory approach. The
proposed method solves the asymmetry of the transcendental equation set, which has
to be solved in cascade multilevel inverters. Simulation and experimental results are
provided for a 7-level cascaded multilevel inverter to show the validity of the
proposed method. The inverters with a large number of steps can generate high quality
voltage waveforms. The THD depends on the switching angles for different units of
multilevel inverters.

40
 CHAPTER4

PSO (PARTICLE SWARM OPTIMIZATION)

4.1 Harmonic Elimination Theory

The output voltage can be applied by using Fourier series. This is an infinite
sum of the trigonometric functions that are economically.

∞
( ) = 0 + ∑( 0cos(2π 0) +
=1
)

Where

N=integer multiple,

=initial phase for nth harmonic,

0And 0 are four coefficients

The output voltage equation derived for various voltage sources is given below

∞
( )=∑4 ( 1 cos( 1 ) + 2 cos( 1 )…. cos( 1 ))sin( )
=1,3,5

Where

S= Number of dc sources connected per phase

t
V1,V2, V3=Level of DC voltage

For the above fundamental peak voltage v(t), it is required to determine the switching
angles 0< 1< 2< 3......< <2 and some lower order harmonics of the phase voltages
One switch can be used as a fundamental voltage selection from a number of
switching angles. remaining (s-1) switching angles are needed to eliminate lower order
harmonics. In a balanced three phase (3-ϕ) system, when line to line voltages are used the
triplet harmonics are eliminated automatically by using line to line voltages so only non-
triplet odd harmonics are present.
41
11.5
In order to achieve a wide range of modulation indexes with minimized THD for the
synthesized wave forms, a generalized selective harmonic modulation method was
proposed, which is called virtual stage PWM An output wave form is shown in Figure
3.4

Fig.4.1 Output waveform of virtual stage PWM control

The modulation index gives the relation between the fundamental voltage and the
voltage which is maximum. It is given by m1, is the ratio of fundamental voltage v1 to
the maximum voltage.

The maximum voltage is given by

=4 s
1
M= 1 (3)
4

For an seven level inverter, per each phase there will be three H-bridges are
used so, s=3 i.e., hence there is an availability of three degrees, the fundamental
rd th th th th
voltage magnitude is controlled by the one degree and the 3 , 5 , 7 ,11 , and 13
order harmonic components are eliminated by the remaining degrees respectively.

42
 The above statements are given by
cos( 1)+cos( 1)+……+cos( )=4 1
cos(5 1)+cos(5 1)+……+cos(5 )=0
cos(7 1)+cos(7 1)+……+cos(7 )=0
cos(11 1)+cos(11 1)+……+cos(11 )=0
The above equations are transcendal equations known as Selective Harmonic Elimination.
Here 1, 2, 3, 4 … . are the unknown values. These are determined with PSO algorithm.

4.2 PSO (Particle Swarm Optimization)

Particle swarm optimization (PSO) is a population based metaheuristic

optimization technique developed by Dr. Kennedy and Dr. Eberhart in 1995, inspired
by social behavior of fish schooling or bird flocking.

4.2.1 Evolutionary Algorithms: PSO

From the past few years, Evolutionary Technique has become an evaluating and
interesting research field. It is not mainly because of its efficiency to find an optimum
but also because of its affinity along with the natural social systems. All these
technological evaluations are biological because all these are inspired by the nature.
Methods like mutation, reproduction, natural selection and recombination are used to
produce solutions required by the candidate. Generally the problem space which
consists of ordination under goes operations like combination, mutation etc. The
values that are to be obtained are decided on the basis of a cost function which in turn
regulates the suitability of resulting candidate solutions. These operations are then
applied repeatedly. Because of the natural selection most developed optimum solution
can be achieved.

The basic idea and main features of EAs as in is presented as a competition

between a population of individuals the competition adds strength to the theory of
“survival of fittest” under environmental influence leading to rise in fitness of
population. The main features of Evolutionary Algorithms are as follows,

• They process all the date of the candidate at a time as they EAs are population
based.

43
 • A recombination is used by EAs to combine the whole information which we
can get from a candidate solutions.
• These EAs are the optimizing tools
This model firstly introduced by John Holland and his students in 1975. These
algorithms are helpful in encoding the potential solutions of the problem on to
chromosomes. While safeguarding their information we can then apply recombination
on to these chromosomes. In other words, GA utilizes selection and recombination
operators to produce new sample points in sample space. It can be obtain near optimal
solution without the complete knowledge of task domain, by only manipulating
chromosomes. For solving any problems related to the optimization this feature has
become more popular.

The concept of particle swarms was originated by Kennedy, a social psychologist

and an electrical engineer, Eberhart to develop utilizing the existing natural interactive
systems, and the idea of computational intelligence. The first simulations were
influenced by involved analogues and social behavior of bird flocks searching for
corn. This soon developed into a powerful optimization method, Particle Swarm
Optimization (PSO). PSO attempts to mimic the goal-seeking behavior of biological
swarms.

In PSO algorithm, the collection of particles in search space aim to optimize a

fitness function, in such a way similar to movement of flocks of birds in natural
environment in search of food. The particles are placed randomly in search space and
they evaluate their quality or fitness at that particular position. Then, for a predefined
number of iterations, each particle moves to a new location which gives better fitness
compared with the previous position. This movement is based on the history of
particles own best and current locations with those of the best positions attained by
other particles in the swarm, with some random perturbations. Thus in subsequent
iterations the swarm achieves the most optimum solution to the fitness function in the
problem space, with a defined number of particles working together. The objective
function or fitness in PSO algorithm is a performance evaluation criterion that
depends on the application area of the algorithm. The performance criterion is usually
defined by the mathematical formulation to quantify the system performance achieved
through the performance index.

44
 The motivation behind the Genetic algorithm and some other techniques which
works based on population are by evolution cause it occurs in nature. Contrary to
other techniques PSO is based on analogies with social behavior of birds and animal.
All the particles of the swarm are retained throughout the search process as there will
be no selection operation. The velocity and position of each of the particles in every
iteration is updated, along with the group’s best positions and particles own attained
so far.

4.2.2 Basic Particle Swarm Optimization Algorithm

The basic particle swarm optimization algorithm consists of a swarm of “n”

particles, and the position of each particle represents a possible solution of the fitness
function in D dimensional search space. The particle changes its condition under the
influence of these three factors:

Its own inertia.

Swarm’s most optimal position.

Personal most optimal position.

General Scheme of Evolutionary Algorithms

BEGIN
Initialize each candidate in the population randomly,

Evaluate fitness of each candidate,

REPEAT UNTIL (Termination Condition is satisfied)

DO

SELECT parents;

RECOMBINE their pairs;

MUTATE the resulting off springs;
EVALUATE new candidate solutions;
SELECT individuals for next generation based on fitness of evaluated candidate
solutions;
END

45
In PSO algorithm, the position and speed of each of the particles in the swarm change
according to the following equations
+
+
= + ( − )+ +
( − ) (1)
= + (2)

Where,
+
and represents velocity and position of i th particle (out of n particles) at d-
dimension (out of D dimensions) in kth iteration respectively.

and represents personal best position and global best position (i.e. group’s
th th
best) of i particle (out of n particles) at d-dimension (out of D dimensions) in k
iteration respectively.

Represents inertial weight attached to the particle’s previously attained position.

Represent acceleration constants.

, Represent random numbers in the range of.
1 2

• Momentum: It shows the tendency of particle which tries to move in the

same direction as it was moving in the previous iteration. It incorporates the
effect of previous velocity on current velocity of the particle.
• Cognitive part: It represents the pull to particle’s velocity towards its own
personal best (pbest).Referred to as “remembrance” “memory”, or “self-
knowledge”.
• Social part: It represents the pull to particle’s velocity towards swarm’s best
(gbest). Referred to as “shared information”, “cooperation”, or “social
knowledge”.

46
 Figure 4.2 Illustrates the flowchart of PSO algorithm

A. Inertia Weight

In the search of space particle’s velocity in which every dimension is hold onto a
maximum velocity, Vmax. This maximum velocity calculates the intent or resolution with
which regions between the target position and represent position which is better so far can
be sorted out. Although some problems may arise by using the hard bound. For example a
very low Vmax is there then we cannot get some good far locations, if a very high V max is
there then particles might slip away from some good food locations. Thus in order to
reduce the importance of Vmax, and to sharpen the foraging ability of particles, and better
to say in order to knock out it altogether, a weight term was added to the PSO’s update
equations. This weight term is called inertia weight (w) and it controls the effect which
the last iteration speed has on the current speed. Smaller value of w improves the partial
search capability and larger value of w improves global search capability of PSO
algorithm. Generally, it is equal to one, but eventually the search ability decreases

47
and the particle get stuck at a non optimum location. In experimental work, w is kept
in between 0.4 to 0.9 and the values are decreased linearly so that the algorithm
allows the particles to explore wider areas in beginning and nearby areas in later
stages with reduced speeds. This setting gives a greater likelihood of reaching the
target optimum position as early as possible.

Note that if we interpret then,

( −)+( − ) as the external force fi, acting on a particle, then the change in a
particle’s velocity (i.e., the particle’s acceleration) can be written as (3);

Δvi = fi − (1 − ω)vi (3)

Thus we can say that the constant (1 – ω) acts effectively as a friction

coefficient. Hence ω is said to be the fluidity of medium in which a particle moves.
Perhaps this is the reason why researchers have found that the best performance is
obtained by setting ω initially to some relatively high value (e.g., 0.9).the high value
ω of corresponds to a system where particles move in a low viscosity medium and
perform extensive exploration. When ω is gradually reduced to a much lower value
(e.g., 0.4), the system becomes more exploitative and dissipative and would be better
at homing into local optima. It is even possible to start from values of ω >1, but that
will make the swarm doddery and unsteady until and unless the value is reduced
sufficiently to bring the swarm in a stable region.

B. Acceleration constants c1 and c2

These constants are related to the speed of flying of particles to the most optimist
position of swarm and its own best position. They regulate the time and length taken
by particle to reach most optimum position. So that the particle land in a correct
position, these constants must be properly selected. For too small values, the particle
will not be able to reach the target position and for too big a value of acceleration
constants, the particle may fly past the correct position. Generally each of these
constants are set to two(2) to make the times taken to move towards the best and
particle’s personal best swarm’s global as equal and half the total time. These
acceleration constants represent the weighing of acceleration terms towards gbest and
pbest locations.
48
C. Random numbers r1 and r2

The pull on the particles towards gbest and pbest positions are regulated by adding
random numbers in the update rules.

These are random fiction and determine the magnitude of random forces towards the
two best positions. They add a random component to the PSO algorithm and help
prevent the algorithm from getting stuck at a non optimal local maximum or
minimum solution.
D. Size of population

This is usually set on the perceived difficulty of a problem and basis of the
dimensionality. Values in the range 20–50 are quite common. Swarm size varies from
one application to the other and so is problem dependent.

Advantages and Disadvantages of PSO Algorithm

The PSO algorithm used in various optimization problems has certain advantages
and disadvantages given below;

Advantages
1.PSO algorithm does not involve selection operation or mutation calculation. The
search can be carried out by repeatedly varying particle’s speed.
2.By learning from group’s experiences, particles fly only to good areas (where there
is a possibility of finding food).
3.PSO algorithm is based on artificial intelligence and thus, can be applied into both
scientific research and engineering applications.
4.Simple calculations are involved in PSO algorithm and with development of newer
evaluation techniques they are be done easily. Disadvantages

1.Standard PSO suffers from a substantial rise in search complexity with increase in
dimension of search space.
2.The method is vulnerable to partial optimism, which leads to a much less accurate
regulation of its speed and the direction.
3.Due to the lack of dimensionality this method cannot be used for problems of non-
coordinate system, such as the solution to the energy field and the moving rules of the
particles in the energy field

49
 When an application task involves many parameters and the parameter dimensions
are increasing in order to match the increase in task complexity, the solution space is
expected to grow exponentially. Consequently the search becomes more and more
hazardous and baffling. Time to time the PSO algorithms has been modified and altered
to obtain better solutions than the standard PSO. But the search quality of these modified
versions declines soon for complex tasks with high dimensional and multimodal objective
functions. In addition to it the distribution and density of these optimal solutions often
vary from function to function making it more difficult to design a general or universal
strategy for all complex situations. This is mainly because the PSO has a high
convergence speed and this often results in the loss of diversity during the optimization
process. The undesirable and premature situation leads the particles to get trapped in local
optimums. Hence it is unable to gain the best solution. To overcome the search difficulties
described above, a new PSO approach with two special features was proposed; one with
dimension partition and other with adaptive velocity control.

The most important reason for this premature convergence is the velocity update
rule which only depends on information on same dimension. Thus when a specific
dimension starts losing its diversity in position or gets trapped in local minima the
search capability in that dimension decreases and so the overall search ability is
hindered.

Table 4.1 Parameters of proposed PSO algorithm

Parameter Symbol Value

Acceleration coefficient C1 2
C2 2
Maximum velocity ∆xmax 0.2
Inertia weight extremes [wmin,wmax] [0,1]
Size of swarm P 100
Maximum number of iterations J 100

50
 4.3 Simulation Results

Figure 4.3Simulated phase voltage waveform and their

corresponding frequency spectrum at M=0.6

rd th th
So, in order to reduce the most dominant lower order harmonics (3 ,5 , and 7 )the
proposed PSO approach reduces the computational burden to find the optimal solution
compared With iterative methods and the resultant theory approach. The proposed
methodology solves the asymmetry of the transcendental equation set that has to be
solved in cascade multilevel inverters. Simulation and experimental results are provided
for a 7-level cascaded multilevel inverter to indicates the validity of the proposed method.
The inverters with a large number of steps will generate high quality

51
voltage waveforms. The Total Harmonic Distortion depends on the switching angles
for various units of multilevel inverters.

In preposed seven level cascaded multilevel inverter we obtained seven level

rd
output as shown in the below figure.We obtain the high amount of 3 order harmonic
componenent compared with other order components.As we know that lower order
harmonics have the most doninent role in outputwave distortion, So the total THD
value of the normal seven level cascaded H-bridge multilevel inverter was 21.705%.

So, with PSO technique we obtain the switching angles in order to reduce low order harmonics.
We have the switching angles as from PSO was as follows 1=11.8, 2=41.7, 3=85.7 respectively
with modulation index 0.60. The THD value with this PSO based selective harmonic elimination
is 13.80%. We reduced the total THD value and with this Technique mostly third order harmonic
component magnitude was controlled.

52
 CHAPTER-5

CONCLUSION

Recently for the control of CHB multilevel inverters a new technology has been
introduced. For solving the nonlinear equation which is generally set by the gaining an
additional degree of freedom in the optimized technology. The targeted third and fifth
harmonics can be eliminated, PSO performs appealingly in the perspectives of THD and
low-order harmonic mitigation compared with other scenarios. Accordingly. Using SHE
technology in multilevel inverters gives an efficient performance in wider
applications.45% of the modulation range will be tracked by the SHE. While 3rd, 5th and
7th harmonics are marginally diminished by PSO based SHE. Generally designed in
proposed seven level cascaded multilevel inverter we obtained seven level output with the
rd
high amount of 3 order harmonic component compared with other order components.
So the total THD value of the normal seven level cascaded H-bridge multilevel inverter
was 21.705%. But with the PSO based selective dominant harmonics are deleted. Then
we get the total THD value13.80% respectively. All remarked enhancements are verified
through simulations and laboratory implementations. Such an approach appears to be
particularly favorable for photovoltaic systems in future studies.

53
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