2012 IEEE Vehicle Power and Propulsion Conference, Oct.

9-12, 2012, Seoul, Korea

Neutral-Point Voltage Control for Grid-connected

Three-Level Inverters using
a Discontinuous Pulse Width Modulation
Hyun-Hee Lee, Ui-Min Choi, and Kyo-Beum Lee
Division of Electrical and Computer Engineering
Ajou University, Suwon, Korea
E-mail: kyl@ajou.ac.kr

Abstract- This paper proposes a method for neutral-point

voltage balancing control for a three-level inverter that uses
discontinuous pulse width modulation (DPWM). DPWM is the
method that only 2 phases are involved to switching among 3
phases. In the case of unbalanced neutral-point voltage in
inverter using DPWM, the conventional neutral-point voltage
control method adding offset voltage to the reference voltage has
restriction due to the small vector in the non-switching period.
Furthermore, if the offset voltage is comparatively big value, the
conventional method may have problem distorting output
voltage because discontinuous switching period would be
overlapped by another phase’s discontinuous switching period.
The proposed method is implemented by adjusting the Fig. 1. Schematic diagram of a three-level T-type inverter
discontinuous pulse width of in positive and negative cycle. The
TABLE I
method maintains low switching loss and effective voltage SWITCHING STATES IN THREE-LEVEL T-TYPE INVERTER
balance, without the need for complex calculations. Simulation
Device Switching Status Output
results confirm the feasibility and effectiveness of the proposed Switching
method. (x = a, b, c) Voltage
State
Sx1 Sx2 Sx3 Sx4 Vxz
I. INTRODUCTION
P ON ON OFF OFF VDC/2
Three-level inverters are employed widely in the heavy
industry [1]-[2]. Compared to traditional two-level inverters, O OFF ON ON OFF 0

three-level inverters have the advantages. The harmonic
contents of a three-level inverter are less than that of a two-
level at the same switching frequency. Besides voltage stress
of each main switch is reduced to half of the dc bus voltage
[3]. when using discontinuous pulse width modulation
(DPWM), the switching loss is reduced and better harmonic
characteristics are obtained at a high modulation index as
compared with an inverter using continuous pulse width
modulation (CPWM) [4]. The DC-link voltage of a three-
level inverter is divided by capacitors in series. Therefore, the
neutral-point voltage may be unbalanced, which can lead to
failure of the switching devices and an increase in the total
harmonic distortion (THD) of the output current because low-
order harmonics will appear in the output voltage of a grid
connected system [5]. For maximize the performance of a
three-level inverter the neutral-point potential of the DC-link
capacitors should be kept balanced [6]. However, a deviation
in the DC-link voltage can occur by the several reasons
described in [7].
Generally, the conventional balancing method is to add the
offset voltage to the reference voltages. However, when using
DPWM applied, it is impossible to balance the neutral-point
N OFF OFF ON ON -VDC/2
voltage by this conventional method. In DPWM method
during each sampling period, each of the phases ceases the
modulation and the associated phase is clamped to positive dc
bus or negative dc bus. The neutral-point current is limited to
control because turn-on and turn-off switching are maintained
at regular intervals.
This paper proposes the neutral-point voltage balancing
control for the three-level inverter using DPWM. The
proposed algorithm is possible to control the neutral-point
current through the adjustment of discontinuous pulse width.
It is also able to maintain the low switching loss and it can be
effectively balanced without complicated calculation [8]-[9].
II. THREE-LEVEL T-TYPE INVERTER
A. Three-Level T-type Inverter Configuration
In the past, many studies about three-level NPC (Neutral
Point Clamped) inverter have been implemented [10]-[11].
Currently, the active researches of improved topologies are
on process. Among improved topologies, three-level T-type
inverter is used in this paper. The T-type inverters use IGBT

978-1-4673-0954-7/12/$31.00 ©2012 IEEE

638
  
 
 
 

Fig. 2. Relationship between small vector and neutral-point current

TABLE II
SWITCHING STATES OF SMALL VECTOR
Switching state
Fig. 3. Change in small vector dwell time when offset voltage is added
P-type [POO], [PPO], [OPO], [OPP], [OOP], [POP]
N-type [NOO], [NNO], [ONO], [ONN], [OON], [NON]

as a main switch same as the conventional 2-level inverters.

A bi-directional switch is connected between the neutral-
point and each output. The switching loss and the switching
noise of three-level inverter are reduced comparatively to the
conventional 2-level inverter’s because the devices operate
under half of dc-link voltage. The conduction loss of T-type
inverter is same as 2-level inverter’s but lower than the NPC
inverter’s because the current is conducted through a single
switch. Hence, within medium switching frequency
(5~20kHz) range, the total loss in T-type inverter is the Fig. 4. 60° DPWM.
lowest among the NPC, T-type and conventional 2-level
inverters. Fig. 1 shows a schematic of a three-level T-type
inverter. The switching states and output voltages are listed
in Table I.
B. Deviation Effect of Switching Stage of Neutral-Point
Voltage
In the P-type switching state [POO], since the three-phase
load is connected between the positive DC-bus and the
neutral-point, an neutral current flows into the neutral-point,
causing VZ to increase. However, the N-type switching state
[ONN] causes VZ to decrease. A P-type small vector causes Fig. 5. Added offset voltage.
VZ to increase whereas an N-type small-vector causes VZ to vector [ONN] is increased after adding the offset voltage.
decrease. To minimize the neutral-point voltage deviation, Hence, the neutral-point voltage decreases owing to the
dwell time of a given small vector can be equally distributed decrease in the current flowing into the neutral-point.
between the P- and N- type switching states over a sampling
period. Table II lists the switching states of small vectors with B. Problem of Method adding the offset voltage for Three-
their relevant neutral currents. Level Inverter using DPWM
The typical DPWM is a 60° DPWM, which means that the
III. NEUTRAL-POINT VOLTAGE BALANCING
output of each inverter leg is alternately tied to the positive or
A. Method adding the offset voltage negative rail of the DC-link for one-third of the electrical
Generally, the offset voltage is added to the reference fundamental period [13]. This modulation has several
voltage in the conventional method [12]; Fig. 3 illustrates this advantages such as it reduces the average switching
method. If a negative offset is added to Voffset, the dwell time frequency by 33% as well as it reduces the switching loss. Fig
of a small vector will change. The neutral-point current 4 shows the 60° DPWM. If the neutral-point voltage becomes
changes depending on the dwell time of a given small vector. unbalanced when using the 60° DPWM, the conventional
The dwell time of a P-type small-voltage vector [PPO] is voltage balancing method is ineffective. Fig. 5 shows that the
decreased and the dwell time of an N-type small-voltage effect of adding the offset voltage for a three-level inverter

639
Fig. 6. Proposed method: (a) control when the upper capacitor voltage is
higher, (b) control when the lower capacitor voltage is higher.

Fig. 8. Adjustments in discontinuous Pulse width for neutral-point voltage

balance
method has limited effectiveness when 60°DPWM is used. In
DPWM, two phase switches among the three phase switches
are operated. When a high offset voltage is added, the
modulation index is distorted because the discontinuous pulse
width overlaps with the other phase, which also means that
the output current is distorted.
C.
Proposed Method
This paper proposes a method that adjusts the width of the
positive and negative discontinuous sections in inverse
proportion to each other and varies the small vectors. If the
Fig. 7. The change of voltage vector when the proposed method is used positive-clamped section is lengthened, its switching state has
a longer section maintained in the P state, which results in an
with DPWM. When the upper capacitor voltage is higher than increase in the P-type small vector. Moreover, the negative-
the lower capacitor voltage and when CPWM is used, the clamped section is shortened because it is in inverse
current flowing into the neutral-point increases by as much as proportion to the positive-clamped section, and the switching
the increment in the P-type small vector dwell time. However, state of the clamped phase has a shorter section maintained in
when DPWM is applied and the offset voltage is added, each the N state, which leads to a decrease in the N-type small
phase is clamped to the negative DC-bus for 60°. The current vector. Likewise, when the negative-clamped section is
flowing out of the neutral-point is steady because the N-type lengthened, the N-type small vector decreases and the P-type
small vector switching states [NOO], [ONO], and [OON] small vector increases by a corresponding amount. This
exist for 60°. Hence, even though the threshold offset voltage inversely proportional adjustment in the width of the
is added to the reference voltages, the resulting change in the discontinuous section in the positive and negative cycles
small vectors’ dwell time is not large enough to balance for reduces the switching loss and prevents overlap of the
the neutral-point voltage. In other words, the conventional discontinuous section with the other phases. Fig. 6(a) shows

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 TABLE III
ADJUSTMENTS IN DISCONTINUOUS PULSE WIDTH ACCORDING TO
UNBALANCE STATUS OF NEUTRAL-POINT VOLTAGE
Parameter Value
DC-link voltage 600V
DC-link capacitance 1230 μF
Switching frequency 12.5 kHz
Control period 160 μs
Frequency 60 Hz
Grid line- line voltage 380 V
err(threshold) 5V
Fig. 9. Added the offset voltage at three-level inverter using CPWM: (a) two
DC-link voltages, (b) current of phase a, (c) Output voltage of phase a .
the control when the upper capacitor has a higher voltage than
the lower one, and Fig. 6(b) shows the control when the lower
capacitor has a higher voltage. When the upper capacitor
voltage is higher, the output voltage is adjusted, as shown in
Fig. 7, to balance the neutral-point voltage. The P-type small
vector increases and the N-type small vector decreases in
comparison with 60° DPWM.
Fig. 8 shows the adjustments in the discontinuous pulse
width for neutral-point voltage balance. The value of the
difference between the two half-bus voltages (Vdc1-Vdc2) is
defined as Verr(k). The old value of Verr(k) is denoted by
Verr(k-1). The threshold of the neutral-point voltage deviation
can be represented as err. When Verr(k) > err and Verr(k) >
Verr (k-1), θ is added to the positive discontinuous pulse width
and subtracted from the negative discontinuous pulse width to
increase the current flowing into the neutral-point. When Verr
(k) > err and Verr (k) = Verr (k-1), the operation is the same as
above. However, if the control is performed as in the two
mentioned cases when Verr (k) > err and Verr (k) < Verr (k-1),
Verr may miss the balanced point and increase inversely.
Therefore θ is subtracted from the positive discontinuous
pulse width and is added to the negative discontinuous pulse
Fig. 10. Added the offset voltage at three-level inverter using DPWM: (a)
two DC-link voltages, (b) current of phase, (c) Output voltage of phase a .
Fig. 11. Proposed method: (a) two dc-link voltage, (b) output current of
phase a, (c) output voltage of phase a.
width. When –err < Verr(k) < err, θ is subtracted from the
positive discontinuous pulse width and is added to the
negative discontinuous pulse width, or it is added to the
positive discontinuous pulse width and is subtracted from the
negative discontinuous pulse width, according to the
relationship between Verr (k) and Verr (k-1). When Verr (k) <
err, the necessary adjustment is the reverse of that when Verr
(k) > err.
IV. SIMULATION RESULTS
Simulations are carried out to confirm the validity of the
proposed algorithm. The proposed algorithm is applied at
0.5s. The simulation parameters related to the grid-connected
three-level Type inverter and neutral point voltage balancing
scheme are represented in Table I.
Fig. 9 shows the waveforms when the conventional neutral-
point voltage control method is applied to a three-level
inverter with CPWM. The offset voltage is added for neutral-
voltage balance and it is 30 V. Fig. 9(a) shows the two half-
bus voltages across the upper and lower capacitors. The offset
voltage is added at 0.5 s and the neutral-point voltage is
balanced at 0.63s. Fig. 9(b) shows the current of phase a. The
641
current is disappeared after 0.63s. Fig. 9(c) shows the output active power filter,” IEEE Trans. Ind. Electron., vol. 23, no. 6, pp.
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increased. Fig. 10 shows the result when the same offset Pulsewidth Modulation for Three-Level NPC Converter With the
voltage is added to the waveform in comparison with Fig. 10. Neutral Point Voltage Control,” IEEE Trans. Ind. Electron., vol. 58, no.
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voltage is shortened. This indicates an increase in the P-type
small vector and a decrease in the N-type small vector.
Therefore, the upper capacitor voltage is decreased and the
lower capacitor voltage is increased.
V. CONCLUSION
This paper has proposed the neutral-point voltage balancing
control of DPWM three-level inverter. The proposed
algorithm is possible to control the small voltage vector
through the adjustment of discontinuous pulse width because
the neutral-point voltage is influenced by the small voltage
vector. It is able to maintain the low switching loss because
the discontinuous pulse width is reversely adjusted. The
simulation results confirm the feasibility and effectiveness of
the proposed method compared with the conventional method.
ACKNOWLEDGMENT
This work was supported by KETEP (20111020400030-11-
1-000) which is funded by MKE (Ministry of Knowledge
Economy).
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