Programa en VHDL para pasar de binario a display 7 segmentos

Utilizando la tarjeta Nexys 3. Entrada con switches, salida a display cero.

Código en VHDL

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity bin2seg is
Port ( SEG : out STD_LOGIC_vector (7 downto 0 );
AN : out STD_LOGIC_vector (3 downto 0 );
BIN: in std_logic_vector(3 downto 0));
end bin2seg;

architecture Behavioral of bin2seg is

begin
SEG<= x"01" when BIN = x"0" else
x"4F" when BIN = x"1" else
x"12" when BIN = x"2" else
x"06" when BIN = x"3" else
x"4C" when BIN = x"4" else
x"24" when BIN = x"5" else
x"20" when BIN = x"6" else
x"0F" when BIN = x"7" else
x"00" when BIN = x"8" else
x"0C" when BIN = x"9" else
x"08" when BIN = x"A" else
x"60" when BIN = x"B" else
x"31" when BIN = x"C" else
x"42" when BIN = x"D" else
x"30" when BIN = x"E" else
x"38";

AN<="1110";
end Behavioral;

Código UCF

NET "AN[0]" LOC = N16;

NET "AN[1]" LOC = N15;
NET "AN[2]" LOC = P18;
NET "AN[3]" LOC = P17;

NET "SEG[0]" LOC = L14;

NET "SEG[1]" LOC = N14;
NET "SEG[2]" LOC = M14;
NET "SEG[3]" LOC = U18;
NET "SEG[4]" LOC = U17;
NET "SEG[5]" LOC = T18;
NET "SEG[6]" LOC = T17;

net "BIN[0]" loc = t10;

net "BIN[1]" loc = t9;
net "BIN[2]" loc = v9;
net "BIN[3]" loc = m8;