Sogi PDF

Grid synchronization for power converters
Grid synchronization for power

converters
Marco Liserre
liserre@poliba.it
Marco Liserre liserre@ieee.org

Outline
• Grid requirements for DG inverters

• PLL Basics, PLL in power systems
• Design of PLL
• PLL for single-phase systems
– Methods to create the orthogonal component
– Methods using adaptive filters
• PLL for three-phase systems
• Conclusions
• Reference papers

Grid
Distrurbances
Grid disturbances are not

at all a new issue, and
the utilities are aware of
them. However, they
have to take a new look
because of the rapidly
changing customers’
needs and the nature of
loads (CIGRE WG14-31,
1999)
Thomsen,1999; CIGRE WG14-31, 1999

Grid requirements for DG inverters

The following conditions should be met, with voltages in RMS and
measured at the point of utility connection.
When the utility frequency is outside the range of +/- 1 Hz the inverter
should cease to energize the utility line within 0.2 seconds.
The PV system shall have an average lagging power factor greater
than 0,9 when the output is greater than 50% rated.
Thus the grid voltage and frequency should be

estimated and monitored fast and accurate enough in
order to cope with the standard
Grid synchronization requirements

A good synchronization of the current with the grid voltage is
necessary as:
 the standards require a high power factor (> 0.9)

 a ”clean” reference for the current is necesarry in order to cope with the
harmonic requirements of grid standards and codes
 grid connection transients needs to be minimized in order not to trip the
inverter
 Distributed Generation systems of higher power have also requirements in

terms of voltage support or reactive power injection capability and of
frequency support or active power droop
 Micro-grid distributed generation systems have wider range of voltage and

frequency and the estimated grid voltage parameters are often involved in
control loops

Grid synchronization options and challenges

There are two basical synchronization methods:
 Filtered Zero Cross Detection (ZCD)
 PLL
Single-phase systems:
The classical solution for single-phase systems was Filtered ZCD as for the PLL
two orthogonal voltages are required.
The trend now is to use the PLL technique also by creating ”virtual”
orthogonal components using different techniques!
Three-phase systems:
 Three-phase PLL should deal with unbalnace hence with negative sequence
 Moreover in three-phase systems dynamics would be better if synchronizing
to all three phase voltages, i.e. based on space vectors rather then on a scalar
voltage

Zero Cross Detection (ZCD) circuits

Dual point interpolation circuit
Resistive feedback hysteresis

circuit
Dynamic hysteresis comparator

circuit
Source: R.W. Wall, “Simple methods for detecting

zero crossing,” IEEE IECON’03, pp. 2477-2481
Filtered Zero Cross Detection (ZCD) based

monitoring and synchronization


v v fil
uk T  I

2
RST x
sin 
v v fil 
Filter  ZCD I V
 1
Vmax
2
f max  f max
f  f min f
 OF/UF
f min  Vmin
TRIP
Vmax 

1 V OV/UV
 x
2
dt
T

RMS CALC Vmin 
Filtering introduces delay. There are digital predictive FIR filters without
delay bu with high complexity (very high order!)
The RMS voltage and frequency are calculated once in a period  poor
detection of changes (sags, dips, etc.)

PLL basis
Basic idea of synchronization based on a phase-locked loop:
 Phase-locked technology is broadly used in military, aerospace, consumer electronics systems

where some kind of feedback is used to synchronize some local periodic event with some
recognizable external event
 Many biological processes are synchronized to environmental events. Actually, most of us
schedule our daily activities phase-locking timing information supplied by a clock.
 A grid connected power converter should phase-lock its internal oscillator to the grid voltage
(or current), i.e., an amplitude and phase coherent internal signal should be generated.
200
100
v
v [V]
0
in
-100
-200
Event based synchronization Phase-locked synchronization

(simple, discontinuous, …) (continuous, predictive,…)

PLL basis
Basic blocks:
 Phase Detector (PD). This block generates an output signal proportional to the phase
difference between its two input signals. Depending on the type of PD, high frequency ac
components appear together the dc phase difference signal.
 Loop Filter (LF). This block exhibits low pass characteristic and filters out the high frequency ac
components from the PD output. Typically this is a 1-st order LPF or PI controller.
 Voltage Controlled Oscillator (VCO). This block generates at its output an ac signal whose
frequency varies respect a central frequency as a function of the input voltage.
v vd vf Voltage
Phase Loop
Controlled v
Detector Filter
Oscillator

PLL in power systems

In 1968 Ainsworth proposed to use a voltage
controlled oscillator (VCO) inside the control loop RL LL
of a High Voltage Direct Current (HVDC)
transmission system to deal with the novel, at that
time, harmonic instability problem. T1 T3 T5
va LS ia
vb +
vdc E -
vc
Subsequently, analog phase locked T4 T6 T2

loops (PLL) were proposed to be used as
measurement blocks, which provide frequency
adaptation in motor drives.

Phase Locked Loop tuning

PD LF
A sin  int  in   vd se

kd k p  ki 
VCO
 
cos( x)  ko
c
Reference: vin  A sin  ωint  in 

VCO output: vVCO  cos  ωc t  out 
VCO angle:   c t  ko  se dt  out  ko  se dt
sin   in  c  t  in  out   sin   in  c  t  in  out  

Akd
PD/Mixer output: vd  Akd sin  ωint  in  cos  ωct  out  
2 
Akd
ωc  in, then vd  sin  2int  in  out   sin  in  out  ,
2 
if
Small signal
analysis:
sin  2  int , in     in  out  

Akd
in  out, then sin  in  out    in  out  v 
if 2 
d
Akd
The average value is vd   in  out 
2
Phase Locked Loop tuning

assuming
PD LF - HPI VCO ko  1 km  1
in  vd  1  se 1 out then kp
km k p 1   ko kps 
 Ti s  s out ( s ) Ti
H  ( s)  
in ( s ) kp
s2  k p s 
Ti
out ( s) 2n s  n2

that can be written as H  ( s)   with   kp

k pTi
in ( s) s 2  2n s  n2 n
Ti
;
2
4.6
ts 
n
The PLL can be tuned as function of the
damping and of the settling time
9.2 ts 2
kp  ; Ti 
ts 2.3
1.8
tr 
n
Key parameters of the PLL

 The hold range DH is the frequency range at which a PLL is able to maintain lock statically.
DH  ko km LF (0)
For the PI, LF(0)=∞ and the hold range is only limited by the frequency range of the VCO
 The pull-in range DP is the frequency range at which a PLL will always became locked, but
the process can become rather slow. For the PI loop filter this range trends to infinite.
400
300
 [rad/s]
200
Pull-in time:
100
2 Din2 0
TP  80 0.5 1 1.5 2 2.5
16 3n
t [s]
6
 [rad]
0
0 0.5 1 1.5 2 2.5
t [s]
 The lock range DL is the frequency range within which a PLL locks within one-single beat
note between the reference frequency and the output frequency.
kp 2
DL  2n  2 Lock-in time: TL 
Ti n

Phase Locked Loop: the need of the orthogonal

component
Akd
To eliminate the 2° harmonic oscillation from sin  2int  in  out   sin  in  out  
2 
Akd
and obtain sin  in  out   it should be considered that
2 
sin  in - out   sin in cos out  cos in sin out
cos
Vsin  int  in 
X
Vsin  in - out  int  out
+  1  1
K p 1   ++
-  sTi  s
Vcos  int  in  in
X
sin

Park transformation in the PD

Park transformation:
vd   cos(out ) sin(out )  v  v   sin(in ) 
v      v   V  
 q    sin(out ) cos(out )   v      cos(in ) 
vd   sin  in  cos  out   cos  in  sin  out    sin  in  out  
v   V   V  
 q   sin  in  sin  out   cos  in  cos   
out    cos  in  out 
Assuming in=out :
vd   sin  in  out   
v   V   q v  V sin(in )
 q   cos  in  out   v v
d
LF
out
VCO
PD
vq v
v vd  1  vf out
k p 1 
1 
vin  
Quadrature
Signal
 Ti s  c
s vd
Generator v
dq
vq in
out

Park transformation in the PD

PI on vd  q
LF VCO
PD
v vd  1  vf 1 out  in v  V sin(in ) ; vd  0
 k p 1  
vin Quadrature
 Ti s  s out  0
Signal c t0
Generator v
dq d
vq   v 
out
in  0
PI on vq t0
v
PD
v vd  v 
vin Quadrature  LF VCO

Signal
 out  in 
Generator v vq 1  vf 1 2 v  V sin(in ) ; vq  0
dq k p 1  
 Ti s  c
s
out
q


From here on, it will be considered: out  
2 t0
in  0
vin  v  V sin  in  and PI on vq,, i.e., vq  0 t0
v
Therefore:
out  in and vd  v  V d

Methods to create the orthogonal component

 Transport Delay T/4
LF VCO
PD
vin v vd  1  se 1 
 k p 1  
 Ti s 
c
s
Delay
v vq
T/4
dq vin

 The transport delay block is easily implemented through the use of a first-in-first-out
(FIFO) buffer, with size set to one fourth the number of samples contained in one
cycle of the fundamental frequency.
 This method works fine for fixed grid frequency. If the grid frequency is changing
with for ex +/-1 Hz, then the PLL will produce an error
 If input voltage consists of several frequency components, orthogonal signals
generation will produce errors because each of the components should be delayed
one fourth of its fundamental period.

 Inverse Park Transformation
LF VCO
PD
vin v vd  1  se 1 
 k p 1  
 Ti s 
c
s
v vq
dq vin

v vd
 LPF
v dq
vq
LPF
 A single phase voltage (v) and an internally generated signal (v’) are used as inputs to a Park
transformation block (αβ-dq). The d axis output of the Park transformation is used in a control loop to
obtain phase and frequency information of the input signal.
 v’ is obtained through the use of an inverse Park transformation, where the inputs are the d and q-
axis outputs of the Park transformation (dq-αβ). fed through first-order low pass filters.
 Although the algorithm of the PLL based on the inverse Park transformation is easily implemented,
requiring only an inverse Park and two first-order low-pass filters

20
 Second Order Generalized Integrator D()
Magnitude (dB)
0
f d -20
  -40
q -60
  d s 
90 k=0.1
k=1
Phase (deg)
S ( s)  ( s)  2
45 k=4
s   2
SOGI
f 0
-45
q  2
T ( s)  ( s)  2 -90
f s   2 10
-1
10
0
10
1
10
2
10
3
10
4
20 Frequency (Hz)
v v Q()
Magnitude (dB)
0
k   -20
-40
q v   -60
SOGI 0 k=0.1
Phase (deg) k=1
-45
v k s
k=4
D( s )  ( s )  2 -90
v s  k s   2 -135
qv k  2
-180
Q( s )  ( s)  2 -1 0 1 2 3 4
s  k s   2
10 10 10 10 10 10
v Frequency (Hz)

Methods using adaptive filters

 Adaptive Notch Filter (ANF)
vout s 2   2
OSCILLATOR ANF ( s)  ( s)  2
 cos
vin s  ks   2
 k
vin v vout
 vout=0 when:
   t    
 k  vout can not be directly used as
 PD in the PLL
sin
vin  A cos t  in 

OSCILLATOR
 cos  vout=0 when:    t  in
 k
vin v vout
 vout can be used as PD in the
PLL


 ANF-based PLL VCO
PD
cos
1
k LF
s
vin v vd se 1 
kc
s
Adaptive Notch Filter c
 Very sensible to frequency variation

 ANF+PLL  EPLL
cos
1 LF
k PD VCO
s
vin v vd  1  se 1 
k p 1  
 Ti s  c
s
Adaptive Notch Filter
 sin
Conventional PLL structure
Combination of an ANF with a  More robust
conventional PLL gives rise to the
Enhanced PLL (EPLL)  Faster dynamic response

 Enhanced PLL (EPLL)
v v V( ) v
v k  v’
PD ABPF
ju u
 sin cos
LF  ff
vd  
PI
 VCO
BPAF LP VCO
v + e + + 1 θ
× Kp s
- + +
90° ω0
1
× Ki s Δω sin
y
1 ×
s A Original structure of the EPLL


 SOGI-PLL
Adaptive band-pass filter:
v ks Damping factor is a function of
ABPF ( s )  1  ANF ( s )  ( s)  2
v s  ks   2 the detected frequency value
Second order generalized integrator follower:

If ’ can change, SOGI follower can be seen
v k s
D( s )  ( s )  2 as an adaptive band-pass filter with damping
v s  k s   2 factor set by k and unitary gain
v v v
k 
 As in the EPLL, a standard PLL can be qv
used to detect grid frequency and angle 
 ju is 90º-leading v’ when the PLL is
synchronized in steady state
 SOGI
PD LF VCO
 ju=-qu and qu  qv’
 
 It seems intuitive to use -qu (instead ju) as v PI

the feedback signal for the PD of the PLL  ff ju
 sin
Conventional PLL structure


 SOGI-based Frequency Locked Loop (SOGI-FLL)
 Does not need any trigonometric function since

v v v neither synchronous reference frame nor voltage
k  controlled oscillator are used in its algorithm.
 Is frequency-adaptive by using a FLL and not a
qv SOGI
 PLL.
 Is highly robust in front of transient events
 since grid frequency is more stable than voltage
qv phase-angle.
1 FLL  Attenuates high-order harmonics of the grid
voltage.
v 
  Entails light computational burden, using only
 ff five integrators for detection of both sequence
components.

Three-phase grid synchronization

Distorted and unbalanced voltage vector
VS1   VSn   2VS1VSn cosn  1t 

b 2 2
 vS 
VS

VS1

VS5 
 VSn sin n  1t  
  t  tan 1  1 
V S5
a  S
V  V S
n
cos n  1t  
V S1
c
Neither constant amplitude nor
rotation speed

b
V S1 
VS1 
VS
V S1

v S  (VS1 ) 2  (VS1 ) 2  2VS1VS1 cos(2 t   1 )
t 
 t a
VS1
 VS1 sin(2 t   1 ) 
VS1  V S1
   t  tan  1
1
1 
V S1  V S1  S
V  VS
1
cos( 2 t   )
c

Characterization of voltage dips
Type C Type D
VSa  F VSa  V
 Phase-voltages from
characteristic parameters VSb   12 F  2
3
jV VSb   12 V  2
3
jF
VSb   12 F  2
3
jV VSb   12 V  2
3
jF
Type C Type D
 Sequence components from 

VS1  12 V  F   
VS1  12 V  F
characteristic parameters 
VS1   12 V  F  VS1  12 V  F 
1.5 1.5 1.5
V=0.5<-20 ;F=0.75<-40 V+=0.61589<-32.0197 ;V-=0.16411<108.5995 V=0.5<-20 ;F=0.75<-40 V+=0.61589<-32.0197 ;V-=0.16411<108.5995 V=0.5<-20 ;F=0.75<-40 V+=0.61589<-32.0197 ;V-=0.16411<108.5995
1 1 1
0.5 0.5 0.5

vabc [pu]
[pu]
v [pu]
0 0 0


v
-0.5 -0.5 -0.5
-1 -1 -1
-1.5 -1.5 -1.5

0 0.02 0.04 0.06 0.08 0.1 0 0.02 0.04 0.06 0.08 0.1 -1.5 -1 -0.5 0 0.5 1 1.5
t [s] t [s] v [pu]


Three-phase Synchronous Reference Frame PLL
vSa vSd vSd  vˆ S
vSb
v Sc
T  dq vSq ̂ 1 ˆ vS
vSd 
    VS 

1 cos( t   )
ˆ

 S 
V

1 cos( t  
1
 ˆ) 

 sin( t  ˆ)   sin( t    ˆ) 
1
PI ( dq )  vSq 
s
ˆ
150 7 150
vS
6
100
100
5
50
Balanced 4 vSd  v S
0 50
voltage -50
3
vSq  0
ˆ   t
2
0
-100
1
-150 0 -50
0 25 50 75 100
t [ms]
150 7 150
vS 6
ˆ
100
100
5
50
Unbalanced 4
50
0
voltage 3
vSd  v S
-50
2
t
0
-100 1
vSq  0
-150 0 -50
0 25 50 75 100
t [ms]

vSa vSd vSd  vˆ S Near of synchronization:  '  t

vSb
v Sc
T dq vSq ̂ 1 ˆ sin(t   ')  t   ' cos(t   ')  1 t   '  2t
PI
s  1  cos(2t ) 
ˆ vS  VS1    VS1  
( dq ) t   '  sin(2t ) 
  *
vSq 1 ̂ 1 ˆ
k
VS1 kp  i  V 1 
s s vSq  VS1 t  S1 sin(2t )   '  VS1    '
 VS 
1
V
ˆ 2c s  c 2   t  S1 sin(2t )
P( s )  ( s)  2 VS
 s  2c s  c 2
k p VS1 The SRF is not able to track instantaneous evolution
 c  VS1ki
2 ki of the voltage vector when the PLL bandwidth is low
150 7 150 150
vS 6
t vˆ S1
100 100
100
5
50 50
4 vSd
0 50 0
3
-50
vSq -50
2
0
ˆ   t
-100 -100
1
-150 0 -50 -150

Marco Liserre 0 25 50
t [ms]
liserre@ieee.org
75 100

150 7 150 150
vS vSd
100
6
100 vˆ S1
100
5
50 50
4 vSq
0 50 0
3
-50 -50
2
0
-100 -100
1
-150 0 -50 -150

0 25 50 75 100
t [ms]
Setting a low PLL bandwidth and using a low-pass filter it is possible to obtain a
reasonable approximation of the positive sequence voltage but the dynamic is too slow.
Advanced filtering strategies can be used to cancel out the double frequency oscillation
keeping high locking dynamics, e.g., a repetitive controller based on a DFT algorithm.
Additional improvements are added to these filters to make them frequency adaptive.
vSd
vSa vSd  vˆ S
vSb
v Sc
T 
dq vSq ̂ 1 ˆ
PI
s
ˆ Repetitive
controller


Decoupled Doubled SRF-PLL. Decoupling
q 1  q 1 vSd 1  cos( t  ˆ)  cos( t   1  ˆ) 
  Tdq1   v S  VS 
 
vS  1
  VS 
1

̂ ˆ ˆ
 sin( t   )   sin( t     ) 
1 v 1
̂ v S
( dq 1 )  Sq 
1 ( )
 vSd 1  
1 cos( t   )
ˆ 
1 cos( t  
1
 ˆ) 
v S ̂ vS    
 Tdq1  v S  VS    VS  
( dq 1 )  vSq1    ( )
 sin( t  ˆ)   sin( t    ˆ) 
1
t d 1
 ˆ  Near of synchronization:  '  t
 ˆ
 t   1 d 1  1  This terms act as
1  cos( 2 t   ) 
1
1
v S1 ̂ V  
ˆ  S  sin(2 t   1 )  interferences on
vS V
 t   
S
( dq 1 )
vSqm
the SRF dqn
vSd m
cos(2 t ) 
1 1  cos( ) 
1
rotating at n
dm qm vS V    VS  1 
S
  sin( )  frequency and
*
vSd n d n d n* vSd n ( dq 1 )  sin(2 t ) 
viceversa
vSq n q n q n* vSq
*
n
Generic decoupling cell:
vSd n  VSn cos( n )   cos((n  m)t )   sin((n  m)t ) 

v    n n 
 VSm cos( m )    VSm sin( m )  
 Sqn  VS sin( )    sin((n  m)t )  cos((n  m)t ) 
cos sin
vSd m  VSm cos( m )  n  cos(( n  m)t )  n   sin(( n  m)t ) 
n v    m   V n
cos( )  sin((n  m)t )   V n
sin( ) .
 Sqm  VS sin( )   cos((n  m)t ) 
m S S
DC    
n-m m
ˆ
ˆ

Decoupled Doubled SRF-PLL
PLL input normalization

* 
* vSq1
vSq 1
k p  ki  ̂ ˆ
v v 
2 2
vq d q
f
v Sd 1 *
vSd 1  vˆ S1
1 v
  1 1*
T  v
y d Sd 1
DC   d LPF
Sq 1
  1
1 1 *
dq
q vSq 1 v Sq 1
. 1*
1 q LPF
vS vS ˆ d 1 q
abc   
T 
vSd 1 *
v Sd 1
1 vSd
T 
1 1 1
d d q 1*
vSq 1 d LPF
dq 1 1
q   1 *
vSq v Sq 1
DC   q
1
1*
  1
LPF
ˆ
f

Conclusions
 PLL is a very useful method that enable the grid inverters to:
 Create a "clean" current reference synchronized with the grid
 Comply with the grid monitoring standards
 The PLL generate is able to track the frequency and phase of the input
signal in a designed settling time
 By setting a higher settling time a "filtering" effect can be achieved in order
to obtain a "clean" reference even with a polluted grid.
 Some PLLs need two signals in quadrature at the input.
 For single-phase systems as there is only one signal available, the
orthogonal signal needs to be created artificially.
 Transport Delay, Inverse Park Transformation, or Second Order
Generalized Integrators are some the methods used for quadrature signal
generation.
 Adaptive notch filters canceling fundamental utility frequency are used as
phase detectors in PLLs
 FLL based on a SOGI is a very effective method for single phase
synchronization
References
1. J. D. Ainsworth, “The phase-locked oscillator-a new control system for controlled static
convertors,” IEEE Transactions on Power Apparatus and Systems, vol. 87, no. 3, pp. 859-865,
Mar. 1968.
2. G. C. Hsieh, J. C. Hung, Phase-locked loop techniques – A survey, IEEE Trans. On Ind.
Electronics, vol.43, pp.609-615, Dec.1996.
3. F. M. Gardner, Phase Lock Techniques. New York: Wiley, 1979.
4. L. D. Zhang, M. H. J. Bollen Characteristic of voltage dips (sags) in power systems, IEEE Trans.
Power Delivery, vol.15, pp.827-832, April 2000.
5. F. Blaabjerg, R. Teodorescu, M. Liserre, and A. V. Timbus, “Overview of Control and Grid
Synchronization for Distributed Power Generation Systems”, IEEE Trans. on Ind. Electronics, Vol.
53, Oct. 2006 Page(s):1398 – 1409
6. M. K. Ghartemani, M.R. Iravani, “A method for synchronization of power electronic converters in
polluted and variable-frequency environments,” IEEE Trans. Power Systems, vol. 19, pp. 1263-
1270, Aug. 2004.
7. M.K. Ghartemani, M.R. Iravani, “A Method for Synchronization of Power Electronic Converters in
Polluted and Variable-Frequency Environments,” IEEE Trans. Power Systems, vol. 19, Aug. 2004,
pp. 1263-1270.
8. H.-S. Song and K. Nam, “Dual current control scheme for PWM converter under unbalanced input
voltage conditions,” IEEE Trans. On Industrial Electronics, vol. 46, no. 5, pp. 953–959, 1999.

References
1. P. Rodríguez, A. Luna, I. Candela, R. Teodorescu, and F. Blaabjerg, “Grid Synchronization of
Power Converters using Multiple Second Order Generalized Integrators,” IECON’08, Nov.
2008.
2. P. Rodríguez, J. Pou, J. Bergas, J.I. Candela, R. Burgos and D. Boroyevich, “Decoupled
Double Synchronous Reference Frame PLL for Power Converters Control,” IEEE Trans. on
Power Electronics, March 2007.
3. P. Rodriguez, R. Teodorescu, R.; I. Candela, I.; A.V. Timbus, M. Liserre, F. Blaabjerg, “New
Positive-sequence Voltage Detector for Grid Synchronization of Power Converters under
Faulty Grid Conditions,” PESC '06, June 2006.
4. M Ciubotaru, Teodorescu, R., Blaabjerg, F., “A New Single-Phase PLL Structure Based on
Second Order Generalized Integrator”, PESC’06, June 2006.
5. P. Rodríguez, A. Luna, M. Ciobotaru, R. Teodorescu, and F. Blaabjerg, “Advanced Grid
Synchronization System for Power Converters under Unbalanced and Distorted Operating
Conditions,” IECON’06, Nov. 2006.
6. S.-K. Chung, “Phase-Locked Loop for grid-connected three-phase power conversion
systems,” IEE Proceedings on Electronic Power Applications, vol. 147, no. 3, pp. 213–219,
2000.
7. Francisco Daniel Freijedo Fernández, “Contributions to Grid-Synchronization Techniques for
Power Electronic Converters”, PhD Thesis, Vigo University, Spain, 2009

Acknowledgment
Part of the material is or was included in the present and/or past editions
of the
“Industrial/Ph.D. Course in Power Electronics for Renewable Energy

Systems – in theory and practice”
Speakers: R. Teodorescu, P. Rodriguez, M. Liserre, J. M. Guerrero,
Place: Aalborg University, Denmark
The course is held twice (May and November) every year

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Grid synchronization for power converters

Grid synchronization for power

Marco Liserre liserre@ieee.org

• Grid requirements for DG inverters

Marco Liserre liserre@ieee.org

Grid disturbances are not

Thomsen,1999; CIGRE WG14-31, 1999

Marco Liserre liserre@ieee.org

Grid requirements for DG inverters

Thus the grid voltage and frequency should be

Grid synchronization requirements

 the standards require a high power factor (> 0.9)

 Distributed Generation systems of higher power have also requirements in

 Micro-grid distributed generation systems have wider range of voltage and

Marco Liserre liserre@ieee.org

Grid synchronization options and challenges

Marco Liserre liserre@ieee.org

Zero Cross Detection (ZCD) circuits

Resistive feedback hysteresis

Dynamic hysteresis comparator

Source: R.W. Wall, “Simple methods for detecting

Filtered Zero Cross Detection (ZCD) based

Marco Liserre liserre@ieee.org

 Phase-locked technology is broadly used in military, aerospace, consumer electronics systems

Event based synchronization Phase-locked synchronization

Marco Liserre liserre@ieee.org

Marco Liserre liserre@ieee.org

PLL in power systems

Subsequently, analog phase locked T4 T6 T2

Marco Liserre liserre@ieee.org

Phase Locked Loop tuning

A sin  int  in   vd se

Reference: vin  A sin  ωint  in 

VCO angle:   c t  ko  se dt  out  ko  se dt

sin   in  c  t  in  out   sin   in  c  t  in  out  

sin  2  int , in     in  out  

Phase Locked Loop tuning

out ( s) 2n s  n2

Key parameters of the PLL

Marco Liserre liserre@ieee.org

Phase Locked Loop: the need of the orthogonal

Marco Liserre liserre@ieee.org

Park transformation in the PD

Marco Liserre liserre@ieee.org

Park transformation in the PD

Marco Liserre liserre@ieee.org

Methods to create the orthogonal component

Methods to create the orthogonal component

Methods to create the orthogonal component

 Second Order Generalized Integrator D()

Marco Liserre liserre@ieee.org

Methods using adaptive filters

vin  A cos t  in 

Marco Liserre liserre@ieee.org

Methods using adaptive filters

 Very sensible to frequency variation

Methods using adaptive filters

Marco Liserre liserre@ieee.org

Methods using adaptive filters

Second order generalized integrator follower:

Conventional PLL structure

Methods using adaptive filters

 Does not need any trigonometric function since