library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

entity Ejemplo2Case is

port (sw0, sw1, sw2, sw3: in std_logic ;

swddx: in std_logic_vector (1 downto 0);
lddx: out std_logic_vector (1 downto 0);
led0: out std_logic);

end Ejemplo2Case;

architecture Behavioral of Ejemplo2Case is

begin

process(sw0, sw1, sw2, sw3, swddx)

begin

lddx <= swddx;

case swddx is

when "00" => led0<= sw0;

when "01" => led0<= sw1;
when "10" => led0<= sw2;
when "11" => led0<= sw3;

end case;

end process;

end Behavioral;