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F -X C h a n ge F -X C h a n ge

PD PD

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Introduction of ADC& DAC

Presented by:
M. Khoirul Effendi ST. MSc. (Eng.)
F -X C h a n ge F -X C h a n ge
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Review of Control System (1/2)

p
Control element

r e = r-b
controller Process

Summing
points c

Measurement
b
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Review of Control System (2/2)

PROSES YANG INGIN OPERATIONAL


DIKONTROL SENSOR
AMPLIFIER

FINAL ELEMENT
ANALOG TO DIGITAL
CONVERTER (ADC)

ACTUATOR

DIGITAL TO ANALOG
CONVERTER (DAC) CONTROLLER SET POINT
F -X C h a n ge F -X C h a n ge
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Analog to Digital Converter (ADC)


F -X C h a n ge F -X C h a n ge
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What is an ADC (1/2)


F -X C h a n ge F -X C h a n ge
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Why it should be digitalized?

Computer/controller uses digital data to be processed for controlling a process.


The advantages using computer in process control are
1. Able to control multivariable in the control system
2. Linearization
3. The difficult equation able to solve as quickly as possible, and it can be
modified.
4. Computer network able to solve control issues in large scales
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Analog to Digital Converter (ADC)

Most signals are analog


• e.g. speech, biological signals, seismic signals, radar signals,
sonar signals, etc.
ADC is applied to process analog signals by digital means
ADC has a three-step process
• Sampling
• Quantization
• Coding
A/D
Converter

Xa(t) X(n) Xq(n) 01011


Sample and Quantizer Coder …
Hold (S/H)

Analog Signal Discrete-Time Quantized Digital Sinyal


Signal Signal
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Sample and Hold (S/H)

1. Electronic switch is opened


isolating capacitor from input.
2. Capacitor will hold (stay
charged) switch is opened.
3. The voltage of Capacitor will be
used as voltage input of ADC
but does not discharge because
the high resistance of voltage
follower.
F -X C h a n ge F -X C h a n ge
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Commercially Available S/H


F -X C h a n ge F -X C h a n ge
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Sampling Definition
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Sampling Theorem
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Sampling Theorem
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Sampling Theorem
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Sampling Theorem
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An Ilustration of Aliasing

In physics, a moiré pattern is an interference pattern


created, for example, when two grids are overlaid at an
angle, or when they have slightly different mesh sizes.
F -X C h a n ge F -X C h a n ge
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Sampling Theorem
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Sampling Rate of DSP
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Applications

Aplikasi fmax fs

Geophysical 500 Hz 1 kHz

Biomedical 1 kHz 2 kHz

Mechanical 2 kHz 4 kHz

Speech 4 kHz 8 kHz

Audio 20 kHz 40 kHz

Video 4 MHz 8 MHz


F -X C h a n ge F -X C h a n ge
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Sampling Formulation (1/3)


• X(n) = xa(nT); - < n <
• t = nT = n/Fs
– Fs = Sampling rate
– T = Sampling period
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Sampling Formulation (2/3)

Relationship Among Frequency Variables

Continuous-Time Discrete-Time Signals


Signals
=2 F =2 f
(radians/sec) Hz (radians/sample) (cycles/sample)
= T, f = F/Fs -
= /T, F = f Fs -½ f ½
- < < -
- <F< -Fs/2 F Fs/2
F -X C h a n ge F -X C h a n ge
PD PD

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Sampling Formulation (3/3)

Sampling Theorem
If the highest freq. contained in an analog signal xa(t) is Fmax = B and the
signal is sampled at a rate Fs > 2 Fmax 2B, then xa(t) can be exactly
recovered from its sample values using the interpolation function
g(t) = (sin 2 Bt)/(2 Bt)
F -X C h a n ge F -X C h a n ge
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Sampling Example 1 (1/3)


F -X C h a n ge F -X C h a n ge
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Sampling Example 1 (2/3)


F -X C h a n ge F -X C h a n ge
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Sampling Example 1 (3/3)


F -X C h a n ge F -X C h a n ge
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Sampling Example 2
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Sampling Example 3 (1/4)


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Sampling Example 3 (2/4)


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Sampling Example 3 (3/4)


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Sampling Example 3 (4/4)


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Quantization
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Quantizing (1/2)

Quantizing breaking down analog value into a set of finite states


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Quantizing (2/2)
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Coding
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Coding assigning a digital word or number to each state.


F -X C h a n ge F -X C h a n ge
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Dithering
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F -X C h a n ge F -X C h a n ge
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LSB (Least Significant Bits)


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LSB (Least Significant Bits)


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Accuracy
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Accuracy Resolution
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Accuracy Sampling rate


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Accuracy (Resolution &
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Sampling rate)
F -X C h a n ge F -X C h a n ge
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Commonly Used Methods of ADC

Numerous methods are used for converting analog signals to


digital form. Five most commonly used methods are listed
below:

• Counter ADC
• Tracking ADC
• Successive approximation
• Dual slope
• Voltage to frequency
• Parallel (or flash)
F -X C h a n ge F -X C h a n ge
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Counter Type ADC


Operation
Reset and Start Counter
DAC convert Digital output of Counter
to Analog signal
A clock pulse is used to increment the
counter value increase Vi
Compare Analog input and Output of
DAC
• Vi < VDAC
– Continue counting
• Vi = VDAC
– Stop counting
Digital Output = Output of Counter

Disadvantage
Conversion time is varied
• 2n Clock Period for Full Scale input
F -X C h a n ge F -X C h a n ge
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Tracking Type ADC

Tracking or Servo Type Can be used as S/H circuit


Using Up/Down Counter to By stopping desired instant
track input signal Digital Output
continuously Long Hold Time
• For slow varying input Disabling UP (Down) control,
Converter generate
Minimum (Maximum) value
reached by input signal over a
given period
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PD PD

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Successive Approximation
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ADC
Most Commonly used in Block Diagram
medium to high speed
Converters
Based on approximating the
input signal with binary code
and then successively revising
this approximation until best
approximation is achieved
SAR(Successive
Approximation Register) holds
the current binary value
F -X C h a n ge F -X C h a n ge
PD PD

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Successive Approximation
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ADC
Circuit waveform Conversion Time
n clock for n-bit ADC
Fixed conversion time
Serial Output is easily
generated
Bit decision are made in
serial order
Logic Flow
F -X C h a n ge F -X C h a n ge
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ADC Formulation
F -X C h a n ge F -X C h a n ge
PD PD

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An Example of SAR Calculation (1/5)


F -X C h a n ge F -X C h a n ge
PD PD

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An Example of SAR Calculation (2/5)


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PD PD

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.d o .c .d o .c
c u -tr a c k c u -tr a c k

An Example of SAR Calculation (3/5)


F -X C h a n ge F -X C h a n ge
PD PD

!
W

W
O

O
N

N
y

y
bu

bu
to

to
k

k
lic

lic
C

C
w

w
m

m
w w
w

w
o

o
.d o .c .d o .c
c u -tr a c k c u -tr a c k

An Example of SAR Calculation (4/5)


F -X C h a n ge F -X C h a n ge
PD PD

!
W

W
O

O
N

N
y

y
bu

bu
to

to
k

k
lic

lic
C

C
w

w
m

m
w w
w

w
o

o
.d o .c .d o .c
c u -tr a c k c u -tr a c k

An Example of SAR Calculation (5/5)


F -X C h a n ge F -X C h a n ge
PD PD

!
W

W
O

O
N

N
y

y
bu

bu
to

to
k

k
lic

lic
C

C
w

w
m

m
w w
w

w
o

o
.d o .c .d o .c

Dual Slope Integrating ADC


c u -tr a c k c u -tr a c k

Operation T1 Excellent Noise Rejection


Integrate 0 vi dt High frequency noise cancelled
t2
Reset and integrate Vr dt out by integration
0
Thus T v tV Proper T1 eliminates line noise
1 i ( AVG ) 2 r
t2 Easy to obtain good resolution
vi ( AVG ) Vr
T1 Low Speed
Applications If T1 = 60Hz, converter
DPM(Digital Panel Meter), throughput rate < 30 samples/s
DMM(Digital Multimeter), …
F -X C h a n ge F -X C h a n ge
PD PD

!
W

W
O

O
N

N
y

y
bu

bu
to

to
k

k
lic

lic
C

C
w

w
m

m
w w
w

w
o

o
.d o .c .d o .c
c u -tr a c k c u -tr a c k

Voltage to Frequency ADC

VFC (Voltage to Frequency Low Speed


Converter) Good Noise Immunity
Convert analog input voltage High resolution
to train of pulses
For slow varying signal
Counter
With long conversion time
Generates Digital output by
counting pulses over a fixed Applicable to remote data
interval of time sensing in noisy environments
Digital transmission over a
long distance
F -X C h a n ge F -X C h a n ge
PD PD

!
W

W
O

O
N

N
y

y
bu

bu
to

to
k

k
lic

lic
C

C
w

w
m

m
w w
w

w
o

o
.d o .c .d o .c
c u -tr a c k c u -tr a c k

Parallel or Flash ADC

Very High speed conversion


Up to 100MHz for 8 bit
resolution
Video, Radar, Digital
Oscilloscope
Single Step Conversion
2n –1 comparator
Precision Resistive Network
Encoder
Resolution is limited
Large number of comparator in
IC
F -X C h a n ge F -X C h a n ge
PD PD

!
W

W
O

O
N

N
y

y
bu

bu
to

to
k

k
lic

lic
C

C
w

w
m

m
w w
w

w
o

o
.c .c

Advantages AND Disadvantages


.d o .d o
c u -tr a c k c u -tr a c k

Type of ADC Speed Price Noise Conversion


Immunity Time
Voltage to Constant
frequency
Dual slope Vary
Staircase Vary
ramp 2n
Tmax
f
Successive Constant
approximation n
T
f
Parallel (or Constant
flash) Not feasible
for high
resolution
F -X C h a n ge F -X C h a n ge
PD PD

!
W

W
O

O
N

N
y

y
bu

bu
to

to
k

k
lic

lic
C

C
w

w
m

m
w w
w

w
o

o
.d o .c .d o .c
c u -tr a c k c u -tr a c k

An Example of ADC

In practice, an ADC is usually in form of an integrated circuit (IC).


ADC0808 and ADC0809 are two typical examples of 8-bit ADC with 8-
channel multiplexer using successive approximation method for its
conversion.
ADC0809
National
Semiconductor

For more information,


http://www.national.com/ads-cgi/viewer.pl/ds/AD/ADC0808.pdf
F -X C h a n ge F -X C h a n ge
PD PD

!
W

W
O

O
N

N
y

y
bu

bu
to

to
k

k
lic

lic
C

C
w

w
m

m
w w
w

w
o

o
.d o .c .d o .c
c u -tr a c k c u -tr a c k

Clock
Block Diagram Start

8-bit ADC
End of Conversion
Control & Timing

8 Channels
8 Analog Inputs Multiplexing
Switches S.A.R.

Comparator
Output
Latch 8-bit Output
Buffer

Switch Tree

3-bit Address Address


Latch and
Address Latch Decoder
Enable 256R Resistor Ladder

VCC GND +Vref -Vref Output


Enable
F -X C h a n ge F -X C h a n ge
PD PD

!
W

W
O

O
N

N
y

y
bu

bu
to

to
k

k
lic

lic
C

C
w

w
m

m
w w
w

w
o

o
.d o .c .d o .c
c u -tr a c k c u -tr a c k

ADC on EWB

(EOC = End of Conversion)

(SOC = Start of Conversion)


F -X C h a n ge F -X C h a n ge
PD PD

!
W

W
O

O
N

N
y

y
bu

bu
to

to
k

k
lic

lic
C

C
w

w
m

m
How It is works?
w w
w

w
o

o
.d o .c .d o .c
c u -tr a c k c u -tr a c k

When this ADC is connected to a computer, the sequence of operation is


listed below:

1. The computer reads the EOC to check the ADC is busy or not.
2. If the ADC is not busy when the computer selects the input channel
and send out the “Start” signal. Otherwise, step (1) is repeated.
3. The computer monitors the EOC.
4. When the EOC is activated, the computer reads the digital output.

When there is more than one ADCs being linked to the computer, they
can be connected in parallel. Using the ‘output enable’ can do the
selection of ADC output.
F -X C h a n ge F -X C h a n ge
PD PD

!
W

W
O

O
N

N
y

y
bu

bu
to

to
k

k
lic

lic
How to select and use an
C

C
w

w
m

m
w w
w

w
o

o
.d o .c .d o .c
c u -tr a c k c u -tr a c k

ADC
Range of commercially Guidelines for using
available ADCs ADCs
Use the full input range of
the ADC
Use a good source of
reference signal
Look out for fast input
signal changes
Keep analog and digital
grounds separate
Minimize interference and
loading problem
F -X C h a n ge F -X C h a n ge
PD PD

!
W

W
O

O
N

N
y

y
bu

bu
to

to
k

k
lic

lic
C

C
w

w
m

m
w w
w

w
o

o
.d o .c .d o .c
c u -tr a c k c u -tr a c k

Selection of ADC

The parameters used in selecting an ADC are very similar to those


considered for a DAC selection.

• Error/Accuracy: Quantising error represents the difference


between an actual analog value and its digital representation.
Ideally, the quantising error should not be greater than ± ½
LSB.
• Resolution: V to cause 1 bit change in output
• Output Voltage Range Input Voltage Range
• Output Settling Time Conversion Time
• Output Coding (usually binary)
F -X C h a n ge F -X C h a n ge
PD PD

!
W

W
O

O
N

N
y

y
bu

bu
to

to
k

k
lic

lic
Commercially available
C

C
w

w
m

m
w w
w

w
o

o
.d o .c .d o .c
c u -tr a c k c u -tr a c k

monolithic ADCs
F -X C h a n ge F -X C h a n ge
PD PD

!
W

W
O

O
N

N
y

y
bu

bu
to

to
k

k
lic

lic
Commercially available
C

C
w

w
m

m
w w
w

w
o

o
.d o .c .d o .c
c u -tr a c k c u -tr a c k

hybrid ADCs
F -X C h a n ge F -X C h a n ge
PD PD

!
W

W
O

O
N

N
y

y
bu

bu
to

to
k

k
lic

lic
C

C
w

w
m

m
w w
w

w
o

o
.d o .c .d o .c
c u -tr a c k c u -tr a c k

DAS (Data Acquisition System)

DAS performs the Applications


complete function of Simple monitoring of a
converting the raw single analog variable
outputs from one or more Control and Monitoring of
sensors into equivalent hundreds of parameters in
a nuclear plant
digital signals usable for
further processing, control,
or displaying applications
F -X C h a n ge F -X C h a n ge
PD PD

!
W

W
O

O
N

N
y

y
bu

bu
to

to
k

k
lic

lic
C

C
w

w
m

m
w w
w

w
o

o
.d o .c .d o .c
c u -tr a c k c u -tr a c k

Single Channel System


S/H (Sample and Hold)
Transducer Reduce uncertainty error in
the converted output when
Generate signal of low input changes are fast
amplitude, mixed with compared to the conversion
undesirable noise time
Amplifier, Filters In Multi-channel system
• To hold a sample from one
Amplify channel while multiplexer
Remove noise proceed to sample next one
Linearize • Simultaneous sampling of
two signal
F -X C h a n ge F -X C h a n ge
PD PD

!
W

W
O

O
N

N
y

y
bu

bu
to

to
k

k
lic

lic
C

C
w

w
m

m
w w
w

w
o

o
.d o .c .d o .c
c u -tr a c k c u -tr a c k

Multi-channel System

Analog multiplexer and a Local ADCs and digital


ADC multiplexer
Low cost Higher sampling rate
F -X C h a n ge F -X C h a n ge
PD PD

!
W

W
O

O
N

N
y

y
bu

bu
to

to
k

k
lic

lic
C

C
w

w
m

m
w w
w

w
o

o
.d o .c .d o .c
c u -tr a c k c u -tr a c k

Worked Examples

Question 1. Calculate the maximum conversion time of (a) a 8-bit


staircase ramp ADC and (b) a successive approximation ADC, if
the clock rate is 2MHz.
Solution:
(a) For a 8-bit staircase ramp ADC, the maximum number of
count is
nc = 28 = 256
Therefore, the maximum conversion time is
nc 256 6
Tc 6
128 10 s 128 s
f 2 10
F -X C h a n ge F -X C h a n ge
PD PD

!
W

W
O

O
N

N
y

y
bu

bu
to

to
k

k
lic

lic
C

C
w

w
m

m
w w
w

w
o

o
.d o .c .d o .c
c u -tr a c k c u -tr a c k

(b) For a 8-bit successive approximation ADC, the conversion


time is constant and equal to

n 8
Tc 4 10 6 s 4 s
f 2 106

It can be noted that the conversion speed of successive


approximation ADC is much faster than the staircase ramp
type.
F -X C h a n ge F -X C h a n ge
PD PD

!
W

W
O

O
N

N
y

y
bu

bu
to

to
k

k
lic

lic
C

C
w

w
m

m
w w
w

w
o

o
.d o .c .d o .c
c u -tr a c k c u -tr a c k

Question 2.

Find out the percentage resolution of a DAC of n bits, and hence


determine the value for n = 12.

Solution:
1
Percentage resolution = n
100%
2
For n = 12,

Percentage resolution =

1
12
100% 0.0244% 244ppm (part per million)
2
F -X C h a n ge F -X C h a n ge
PD PD

!
W

W
O

O
N

N
y

y
bu

bu
to

to
k

k
lic

lic
C

C
w

w
m

m
w w
w

w
o

o
.d o .c .d o .c
c u -tr a c k c u -tr a c k

An example of ADC (1/3)

Suatu alat pengukur temperatur menggunakan suatu sensor dengan persamaan


output 6,5 mV/C. Sebuah ADC 6 bit dengan tegangan referensi 10 V digunakan
dalam peralatan ini.
a. Rancang sebuah sirkuit yang menghubungkan sensor dengan ADC
b. Cari resolusi dari sensor temperatur tsb!
F -X C h a n ge F -X C h a n ge
PD PD

!
W

W
O

O
N

N
y

y
bu

bu
to

to
k

k
lic

lic
C

C
w

w
m

m
w w
w

w
o

o
.d o .c .d o .c
c u -tr a c k c u -tr a c k

An example of ADC (2/3)


F -X C h a n ge F -X C h a n ge
PD PD

!
W

W
O

O
N

N
y

y
bu

bu
to

to
k

k
lic

lic
C

C
w

w
m

m
w w
w

w
o

o
.d o .c .d o .c
c u -tr a c k c u -tr a c k

An example of ADC (3/3)


F -X C h a n ge F -X C h a n ge
PD PD

!
W

W
O

O
N

N
y

y
bu

bu
to

to
k

k
lic

lic
C

C
w

w
m

m
w w
w

w
o

o
.d o .c .d o .c
c u -tr a c k c u -tr a c k

Digital to Analog Converter (DAC)


F -X C h a n ge F -X C h a n ge
PD PD

!
W

W
O

O
N

N
y

y
bu

bu
to

to
k

k
lic

lic
C

C
w

w
m

m
w w
w

w
o

o
.d o .c .d o .c
c u -tr a c k c u -tr a c k

In an electronic circuit, a combination of high voltage (+5V) and


low voltage (0V) is usually used to represent a binary number.
For example, a binary number 1010 is represented by
Weighting 23 22 21 20

Binary Digit 1 0 1 0

State +5V 0V +5V 0V

DACs are electronic circuits that convert digital, (usually binary)


signals (for example, 1000100) to analog electrical quantities
(usually voltage) directly related to the digitally encoded input
number.
F -X C h a n ge F -X C h a n ge
PD PD

!
W

W
O

O
N

N
y

y
bu

bu
to

to
k

k
lic

lic
C

C
w

w
m

m
w w
w

w
o

o
.d o .c .d o .c
c u -tr a c k c u -tr a c k

DACs are used in many other applications, such as voice


synthesizers, automatic test system, and process control actuator.
In addition, they allow computers to communicate with the real
(analog) world.
Input Binary
Number
Analog Voltage
Output
Resistive
Register

Summing Amplifier
Voltage Network
Switch
F -X C h a n ge F -X C h a n ge
PD PD

!
W

W
O

O
N

N
y

y
bu

bu
to

to
k

k
lic

lic
C

C
w

w
m

m
w w
w

w
o

o
.d o .c .d o .c
c u -tr a c k c u -tr a c k

Register: Use to store the digital input (let it remain a constant


value) during the conversion period.

Voltage: Similar to an ON/OFF switch. It is ‘closed’ when the


input is ‘1’. It is ‘opened’ when the input is ‘0’.

Resistive Summing Network: Summation of the voltages


according to different weighting.

Amplifier: Amplification of the analog according to a pre-


determined output voltage range. For example, an operation
amplifier
F -X C h a n ge F -X C h a n ge
PD PD

!
W

W
O

O
N

N
y

y
bu

bu
to

to
k

k
lic

lic
C

C
w

w
m

m
w w
w

w
o

o
.d o .c .d o .c
c u -tr a c k c u -tr a c k

The three most popular types of resistive summing networks are:

Weighted binary resistance type, and

Ladder resistance (R-2R) type

Multiplying ADC
F -X C h a n ge F -X C h a n ge
PD PD

!
W

W
O

O
N

N
y

y
bu

bu
to

to
k

k
lic

lic
C

C
Weighted Binary Resistance
w

w
m

m
w w
w

w
o

o
.d o .c .d o .c
c u -tr a c k c u -tr a c k

Type (1/3)
F -X C h a n ge F -X C h a n ge
PD PD

!
W

W
O

O
N

N
y

y
bu

bu
to

to
k

k
lic

lic
C

C
Weighted Binary Resistance
w

w
m

m
w w
w

w
o

o
.d o .c .d o .c
c u -tr a c k c u -tr a c k

Type (2/3)
F -X C h a n ge F -X C h a n ge
PD PD

!
W

W
O

O
N

N
y

y
bu

bu
to

to
k

k
lic

lic
C

C
Weighted Binary Resistance
w

w
m

m
w w
w

w
o

o
.d o .c .d o .c
c u -tr a c k c u -tr a c k

Type (3/3)
F -X C h a n ge F -X C h a n ge
PD PD

!
W

W
O

O
N

N
y

y
bu

bu
to

to
k

k
lic

lic
C

C
w

w
m

m
w w
w

w
o

o
.d o .c .d o .c
c u -tr a c k c u -tr a c k

R2R Ladder Network (1/5)

MSB
V ref
2R

S1
R Vout
2R

Rf
S2
R
2R

S3 R1
R
2R

LSB S4
R
2R

The basic principle of this circuit is formed to overcome great obstacles


that occur when the resistor circuit increases the number of bits
F -X C h a n ge F -X C h a n ge
PD PD

!
W

W
O

O
N

N
y

y
bu

bu
to

to
k

k
lic

lic
C

C
w

w
m

m
w w
w

w
o

o
.d o .c .d o .c
c u -tr a c k c u -tr a c k

R2R Ladder Network (2/5)


F -X C h a n ge F -X C h a n ge
PD PD

!
W

W
O

O
N

N
y

y
bu

bu
to

to
k

k
lic

lic
C

C
w

w
m

m
w w
w

w
o

o
.d o .c .d o .c
c u -tr a c k c u -tr a c k

R2R Ladder Network (3/5)


F -X C h a n ge F -X C h a n ge
PD PD

!
W

W
O

O
N

N
y

y
bu

bu
to

to
k

k
lic

lic
C

C
w

w
m

m
w w
w

w
o

o
.d o .c .d o .c
c u -tr a c k c u -tr a c k

R2R Ladder Network (4/5)


F -X C h a n ge F -X C h a n ge
PD PD

!
W

W
O

O
N

N
y

y
bu

bu
to

to
k

k
lic

lic
C

C
w

w
m

m
w w
w

w
o

o
.d o .c .d o .c
c u -tr a c k c u -tr a c k

R2R Ladder Network (5/5)


F -X C h a n ge F -X C h a n ge
PD PD

!
W

W
O

O
N

N
y

y
bu

bu
to

to
k

k
lic

lic
C

C
w

w
m

m
w w
w

w
o

o
.d o .c .d o .c
c u -tr a c k c u -tr a c k

Multiplying ADC (1/3)


F -X C h a n ge F -X C h a n ge
PD PD

!
W

W
O

O
N

N
y

y
bu

bu
to

to
k

k
lic

lic
C

C
w

w
m

m
w w
w

w
o

o
.d o .c .d o .c
c u -tr a c k c u -tr a c k

Multiplying ADC (2/3)


F -X C h a n ge F -X C h a n ge
PD PD

!
W

W
O

O
N

N
y

y
bu

bu
to

to
k

k
lic

lic
C

C
w

w
m

m
w w
w

w
o

o
.d o .c .d o .c
c u -tr a c k c u -tr a c k

Multiplying ADC (3/3)


F -X C h a n ge F -X C h a n ge
PD PD

!
W

W
O

O
N

N
y

y
bu

bu
to

to
k

k
lic

lic
C

C
w

w
m

m
w w
w

w
o

o
.d o .c .d o .c
c u -tr a c k c u -tr a c k

Selection of DAC
F -X C h a n ge F -X C h a n ge
PD PD

!
W

W
O

O
N

N
y

y
bu

bu
to

to
k

k
lic

lic
C

C
w

w
m

m
w w
w

w
o

o
.d o .c .d o .c
c u -tr a c k c u -tr a c k

Selection of DAC

For the selection of an IC DAC, there are several parameters that


can determine the suitability of a particular device.
Resolution
The number of bits making up the input data word that will ultimately
determine the output step voltage as a percentage of full-scale output
voltage.
Example: Calculate the resolution of an 8-bit DAC.

Solution: Resolution = 8 bits

Percentage resolution =
1 1
8
100% 100% 0.391%
2 256
F -X C h a n ge F -X C h a n ge
PD PD

!
W

W
O

O
N

N
y

y
bu

bu
to

to
k

k
lic

lic
C

C
w

w
m

m
w w
w

w
o

o
.d o .c .d o .c
c u -tr a c k c u -tr a c k

Selection of DAC

Output Voltage Range

This is the difference between the maximum and minimum output


voltages expressed in volts.

Example:

Calculate the output voltage range of a 4-bit DAC if the output voltage
is +4.5V for an input of 0000 and +7.5V for an input of 1111.

Solution:

Output voltage range = 7.5 – 4.5 = 3.0V


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Selection of DAC

Accuracy

The accuracy is usually expressed by the error in output voltage compared with the
expected output voltage. The higher the accuracy, the lower will be the error. Due
to the incremental nature of the digital input word, an error can be tolerated but it
should not exceed ±½LSB or ½resolution.

Example. The error at full-scale for an 8-bit DAC with 10V maximum output is
50mV. Calculate the error and compare it with the resolution.
0.05
Solution: Error = 100% 0.5%
10
1
Resolution = 100% 0.391% ; ½ Resolution = 0.195%
256
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Selection of DAC

The accuracy is not as good as the error = ½ resolution, but for


many applications, it is quite satisfactory. Some commercially
available DACs have their accuracy specified as worse than ½
resolution.

Sources of errors may be broadly classified under four categories:


Non-monotonicity
Full Scale-factor error
Offset error
Gain error
Diff non linearity error
Settling time and overshoot error
Resolution error
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F -X C h a n ge F -X C h a n ge
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F -X C h a n ge F -X C h a n ge
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Selection of DAC
F -X C h a n ge F -X C h a n ge
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Selection of DAC

LSB = Least Significant Bit The LSB is the smallest level that an ADC can
convert, or is the smallest increment a DAC outputs
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Selection of DAC

Input coding

The digital input can be in binary format or it can be in binary coded


decimal format depending on the application. Binary format is more
commonly used.

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