Documentos de Académico
Documentos de Profesional
Documentos de Cultura
Introduction :
Over the past decades the computing technology has made tremendous progress. The computing
power of computers have grown by leaps and bounds, the size of the computers have got reduced
from that of a big hall to palm size, and the cost of computers have become more affordable. The
result is – it has invaded every walk of our lives. This tremendous progress in computers has
come from the advances in the technologies used to build computers as well as from the
innovations made in computer design. However the basic principles on which a computer is built
have essentially remained the same. In this chapter we will take an overview of these basic
principles.
Architecture and Organization are two terms with meanings that are context dependent and are
relative in nature. In the context of a computer also experts have defined these terms somewhat
differently. However, broadly, we can say that the terms- Computer Architecture and Computer
Organization – are used to define two levels of abstractions that are used for designing or
understanding a computer system.
The term Computer Architecture refers to those aspects of a computer system that are
visible to a programmer or those parameters that have a direct impact on the logical execution of
a program. Examples of architectural attributes include the instruction set, the specification of
the data, the number of bits used to represent different data types, Input/Output mechanisms, and
the mechanisms used for addressing memory.
The term Computer Organization refers to the functional units of a computer, their
interconnection and interaction processes so as to realize the architectural specifications.
Examples of organizational attributes include those hardware details that are apparent to the
programmer, such as the functional units like the arithmetic and logical units, control signals,
interfaces between the computer and peripherals, the instruction execution processes etc.
This course deals with the architectural elements of computers as well as the aspects of
computer organization and discusses how a computer, the bare machine, is built.
Basic Computer Model
o Input Unit
o Output Unit
o Memory Unit
Data
Flow
CPU Control/
Signal
The job of the Central Processing Unit or the Processor is to control the operation of all the
functional units of the computer to execute a program. It consists of two basic modules:
o The Decoder and Control Unit (DCU) that interprets the instructions of a program
and emits control signals to the different functional units within the CPU and also the rest
of the computer for execution of the individual instructions.
o The Arithmetic and Logic Unit (ALU) that performs the arithmetic and logical
operations required for execution of the instructions.
In addition, the CPU generally has a set of registers for temporary storage of data and to maintain
the state information of the computer and the data paths that interconnect the different
components of the processor.
B. Input Unit:
Through the Input Unit data and instructions can be fed to memory unit of the computer under
the control of the CPU.
Examples of input devices: Keyboard, Mouse, Track ball, Joystick, Scanner, Digitizer etc.
C. Output Unit:
Through the Output Unit results of the computation are provided to the user from the memory
unit under the control of the CPU.
D. Memory Unit:
The Memory Unit is used to store the data and the program fed through the input unit. The CPU
processes the data as per the instructions in the program. The results produced are stored back in
the memory unit to be finally transferred to the output unit.
The Primary Memory can be thought to be an array of data slots each capable of holding a byte
of data. These slots are called memory locations. Each of these memory locations is identified by
a number. This identifying number is called its address.
. .
. .
. .
N-2
N-1
To access any of the memory locations one has to specify the address and the operation (i.e. read
or write) to be performed. There are address lines through which the address is specified.
Through the command lines the operation is specified. Data lines are provided to input/output the
data. In case of a write operation the data to be written is fed through the data lines. On
completion of the operation the memory unit emits Memory Function Complete (MFC) signal
for information of the operation initiator.
. Command
.
N-1 MFC
Working Principle of a Computer
A computer understands a set of instructions. Any task that needs to be performed by the
computer is specified in terms of the instructions within this set. This specification of the task
therefore takes the form of an ordered set of instructions that is called a Computer Program or
just a Program. The information to be processed and the variable parameters of the task are
specified in terms of Data.
The model of a computer that we discuss here is known as the Von Neumann Stored
Program Computer. This model was developed by Von Neumann in 1946 while building a
computer at the Institute of Advanced Studies (IAS) at Princeton University. In this model of a
computer the program under execution and its data are stored in the primary memory of the
computer. The instructions in the program are stored in the memory unit in the order in which
they are to be executed.
For execution of a program the Program Counter (PC) is loaded with the address of the
first instruction of the program. The processor then follows the steps below:
Decoder &
Control Unit
(DCU)
GPR
Arithmetic &
Logic Unit
(ALU)
SR
SP
In a Register Transfer Language (RTL) the above process can be described as-
Repeat
MAR ← PC
PC++
Read
IR ← MDR
Execute
Until IR = Halt
The first four steps in the process above constitute the Instruction Fetch Cycle while the fifth
step constitutes the Instruction Execution Cycle. The instruction execution cycle can be further
divided into following sub cycles-
1. Operand Fetch Cycle: During this the operands of the instruction are fetched into
the processor from the memory unit.
2. Execution Cycle: Perform the desired operation.
3. Operand Store Cycle: During this cycle transfer the result(s) of the instruction to
desired location.
Activities during these sub cycles vary from instruction to instruction while the Instruction Fetch
Cycle remains the same for every instruction.
Instruction Set Architecture
A. Instruction Types:
a. Data Manipulation Instructions:
i. Arithmetic: For arithmetic operations such as- Add, Subtract, Multiply,
Divide etc.
ii. Logical: Logical operations such as- AND, OR, NOT, etc.
iii. Bit Manipulation: Binary operations such as- Shift, Rotate, Set, Clear etc.
iv. Compare & Test: Performing operations such as- Compare, Test etc.
GPRs
GPRs
ALU
ALU
Accumulator
ALU
Stack
Stack Based m/c
:: SA,SB,SS1+S2,SC,SS1*S2,SD,SS2/S1, SE,SS2-S1,RS1
Addressing Modes:
i. Immediate:
Instruction
The operand is specified
Opcode Operand
as part of the instruction.
Operand
iii. Register:
Instruction
Memory
GPRs
Instruction
Displacement
PC
Operand
+
Memory
GPRS
- Base Register
Instruction
Memory
GPRS
The operand is
placed in a
memory location. Base
The sum of the
Address
contents of an
index register and + Operand
a base register
gives the location Index
of the operand.
Program Control Instructions:
. Branch/ Jump Instructions:
i. Unconditional Branch: Branch, Jump etc.
ii. Conditional Branch: Branch if Equal (BEQ), Branch if Not Equal (BNE) Branch if
Greater Than (BGT) etc.
The format of a typical branch instruction is-
Return Code
The return instruction does not specify any return address. This address is
remembered by the processor by saving it in the processor stack while executing the
subroutine call instruction. The use of the stack for saving the return address allows deep
nesting of subroutines as the stack is a Last-In-First-Out (LIFO) structure.
The Call Subroutine instruction performs a Push(PC) operation to save the current
PC in the Stack and then modify the PC to point to the called subroutine. The Return
instruction placed at the end of a subroutine performs a Pop operation to restore the last PC
saved in the Stack. The resulting effect in case of a set of nested subroutines is as depicted in
the figure below:
Main
----------- Sub1 Sub2 Sub3 Sub4
----------- ----------- ----------- ----------- -----------
-----------
Nested of Subroutines
P4
P3 P3
P2 P2 P2
P1 P1 P1 P1
At Main At Sub1 At Sub2 At Sub3 At Sub4
Word length is 16 bits with the leftmost, most significant bit (MSB) being bit 15. There
are eight general registers of 16 bits each. Register 7 is the program counter (PC) and Register 6
is the stack pointer (SP). There is also a Processor Status Register/Word (PSW) which indicates
the 4 condition code bits (N, Z, V, C), the Trace Trap bit, processor interrupt priority, and 4 bits
for current and previous operating modes.
Addressing for the Single Operand, Double Operand and Jump instructions is achieved
via six bits:
_ _ _ _ _ _
|m|m|m|r|r|r|
|Mode |Reg |
Although not special cases, when dealing with R7 (the PC), some of these modes are
called different things:
_ _ _ _ _ _
|m|m|m|1|1|1|
|Mode | R7 |
Mainstream instructions are broken into Single operand and Double operand instructions,
which in turn can be word or byte instructions.
Bit 15, b, generally selects between word-sized (b=0) and byte-sized (b=1) operands. In the table
below, the mnemonics and names are given in the order b=0/b=1.
Bit 15, b, generally selects between word-sized (b=0) and byte-sized (b=1) operands. In the table
below, the mnemonics and names are given in the order b=0/b=1. Unless otherwise stated, the
operand is read for the data to operate on, and the result is then written over that data.
The single operand instructions are:
Note that SWAB is actually a bit pattern from the range reserved for branches. This
particular pattern is otherwise unused, as it would be a modification of BR, Branch
Always, which has no obvious semantics.
MTPS is only on LSI-11s, and is used to move a byte to the processor status word. This is
needed because the LSI-11 does not support accessing registers via memory addresses.
MFPS copies the processor status byte to the indicated register. This only exists on LSI-
11s, and is needed there because those systems don't support accessing registers via
memory addresses.
Branches
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
|b|0|0|0|b|b|b|b|d|d|d|d|d|d|d|d|
| Branch Code | Destination |
The destination of a branch is +127 to -128 words from the word following the branch
instruction itself. This seems slightly odd, until you realize the sequence of events: the branch
instruction is read from memory and the PC incremented. If the branch is to be taken, the offset
is then added to the current value of the PC. Since the PC has already been incremented, the
offset is thus relative to the following word. Note that all branch instructions are one word long.
The various branches test the values of specific condition codes, and if the tests succeed,
the branch is taken. The condition codes are N (negative), Z (zero), C (carry), and V (overflow).
In the table below, the branch tests are shown as boolean expressions. `x' stands for exclusive-
OR. `v' stands for inclusive-OR.
General opcode 000240x. Set/Clear corresponding bits depending on sense of bit 04 (set=1,
clear=0). Codes 240 and 260 set/clear no bits and are, thus, used as NOP. Although specific
mnemonic are provided for each flag and all flags, any combination may actually be set or
cleared at a time.
Thus, it loads the calling address into the specified link register (after saving the original
contents). It then jumps to the destination. The fun part is (as usual with the PDP-11) that
the PC is a general register, and the description above is the result when the PC is used as
the source.
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
|0|0|0|0|0|0|0|0|1|0|0|0|0|L|L|L|
| Opcode |Link_|
MOV <Link>,PC
MOV (R6)+,<Link>
This is the reverse of JSR. Obviously, the finesse here too is that you can use the PC, to
get what people normally consider a CALL/RETURN function.
...
JSR R0,FOO
.WORD A
.WORD B
MOV R1,C
...
This type of parameter passing is used extensively in the PDP-8 and PDP-10), for
example. Also, the FORTRAN runtime system on the PDP-11 do it this way. (It is fairly
easy to write a compiler that generates such a calling sequence, and then have a library of
functions which expect this calling convention.)
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
|0|0|0|0|0|0|0|0|0|1|d|d|d|d|d|d|
| Opcode |Destination|
00 00 07 .. 00 00 77
00 02 10 .. 00 02 27
00 70 00 .. 00 77 77
07 50 40 .. 07 67 77
10 64 00 .. 10 64 77
10 67 00 .. 10 77 77
Other arithmetic and floating point instructions were added to the basic set over the years, but
those listed above form the core PDP-11 instruction set.