a High Speed, Low Noise Quad

Operational Amplifier
OP471
FEATURES PIN CONFIGURATIONS
Excellent Speed: 8 V/
s Typ
14-Lead 14-Lead
Low Noise: 11 nV/÷Hz @ 1 kHz Max
Hermetic Dip Plastic Dip
Unity-Gain Stable
(Y-Suffix) (P-Suffix)
High Gain Bandwidth: 6.5 MHz Typ
Low Input Offset Voltage: 0.8 mV Max
Low Offset Voltage Drift: 4
V/C Max OUT A 1 14 OUT D OUT A 1 14 OUT D
High Gain: 500 V/mV Min –IN A 2 13 –IN D –IN A 2 13 –IN D
Outstanding CMR: 105 dB Min +IN A 3 12 +IN D +IN A 3 12 +IN D
Industry Standard Quad Pinouts V+ 4 OP471 11 V– V+ 4 OP471 11 V–

GENERAL DESCRIPTION +IN B 5 10 +IN C +IN B 5 10 +IN C

The OP471 is a monolithic quad op amp featuring low noise, –IN B 6 9 –IN C –IN B 6 9 –IN C

11 nV/÷Hz Max @ 1 kHz, excellent speed, 8 V/ms typical, a OUT B 7 8 OUT C OUT B 7 8 OUT C
gain bandwidth of 6.5 MHz, and unity-gain stability.
The OP471 has an input offset voltage under 0.8 mV and an 16-Lead SOIC
input offset voltage drift below 4 mV/∞C, guaranteed over the full (S-Suffix)
military temperature range. Open-loop gain of the OP471 is over
500,000 into a 10 kW load ensuring outstanding gain accuracy
and linearity. The input bias current is under 25 nA limiting OUT A 1 16 OUT D

errors due to signal source resistance. The OP471’s CMR of –IN A 2 15 –IN D

over 105 dB and PSRR of under 5.6 mV/V significantly reduce +IN A 3 14 +IN D
errors caused by ground noise and power supply fluctuations. V+ 4 OP471 13 V–

The OP471 offers excellent amplifier matching which is important +IN B 5 12 +IN C

for applications such as multiple gain blocks, low-noise instru- –IN B 6 11 –IN C

mentation amplifiers, quad buffers and low-noise active filters. OUT B 7 10 OUT C

NC 8 9 NC
The OP471 conforms to the industry standard 14-lead DIP
pinout. It is pin-compatible with the LM148/LM149, HA4741, NC = NO CONNECT
RM4156, MC33074, TL084 and TL074 quad op amps and can
be used to upgrade systems using these devices.
For applications requiring even lower voltage noise the OP470
with a voltage density of 5 nV/÷Hz Max @ 1 kHz is recommended.
V+

BIAS

OUT
–IN +IN

V–

Figure 1. Simplified Schematic

REV. A
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
may result from its use. No license is granted by implication or otherwise Tel: 781/329-4700 www.analog.com
under any patent or patent rights of Analog Devices. Fax: 781/326-8703 © Analog Devices, Inc., 2002
OP471–SPECIFICATIONS
ELECTRICAL CHARACTERISTICS (@ V = 15 V, T = 25C, unless otherwise noted.)
S A

OP471E OP471F OP471G

Parameter Symbol Conditions Min Typ Max Min Typ Max Min Typ Max Unit
Input Offset Voltage VOS 0.25 0.8 0.5 1.5 1.0 1.8 mV
Input Offset Current IOS VCM = 0 V 4 10 7 20 12 30 nA
Input Bias Current IB VCM = 0 V 7 25 15 50 25 60 nA
1
Input Noise Voltage en p-p 0.1 Hz to 10 Hz 250 500 250 500 250 500 nV p–p
Input Noise en fO = 10 Hz 9 16 9 16 9 16 nV/÷Hz
Voltage Density2 fO = 100 Hz 7 12 7 12 7 12 nV/÷Hz
fO = 1 kHz 6.5 11 6.5 11 6.5 11 nV/÷Hz
Input Noise in fO = 10 Hz 1.7 1.7 1.7 pA÷Hz
Current Density fO = 100 Hz 0.7 0.7 07 pA÷Hz
fO = 1 kHz 0.4 0.4 0.4 pA÷Hz
Large-Signal AVO V = ± 10 V
Voltage Gain RL = 10 kW 500 700 300 500 300 500 V/mV
RL = 2 kW 350 550 175 275 175 275 V/mV
Input Voltage Range3 IVR ± 11 ± 12 ± 11 ± 12 ± 11 ± 12 V
Output Voltage Swing VO RL ≥ 2 kW ± 12 ± 13 ± 12 ± 13 ± 12 ± 13 V
Common-Mode CMR VCM = ± 11 V 105 120 95 115 95 115 dB
Rejection
Power Supply PSRR VS = 4.5 V to 18 V 1 5.6 5.6 17.8 5.6 17.8 mV/V
Rejection Ratio
Slew Rate SR 6.5 8 6.5 8 6.5 8 V/ms
Supply Current ISY No Load 9.2 11 9.2 11 9.2 11 mA
(All Amplifiers)
Gain Bandwidth GBW Av = 10 6.5 6.5 6.5 MHz
Product
Channel Separation1 CS VO = 20 V p-p 125 150 125 150 125 150 dB
fO = 10 Hz
Input Capacitance CIN 2.6 2.6 2.6 pF
Input Resistance RIN 1.1 1.1 1.1 MW
Differential-Mode
Input Resistance RINCM 11 11 11 GW
Common-Mode
Settling Time tS AV = 1
To 0.1% 4.5 4.5 4.5 ms
To 0.01 % 7.5 7.5 7.5 ms
NOTES
1
Guaranteed but not 100% tested.
2
Sample tested.
3
Guaranteed by CMR test.

–2– REV. A
 OP471
(Vs = ±15 V, –25 C £ TA £ 85C for OP471E/F, –40C £ TA £ 85 for OP471G,


ELECTRICAL CHARACTERISTICS unless otherwise noted.)

OP471E OP471F OP471G
Parameter Symbol Conditions Min Typ Max Min Typ Max Min Typ Max Unit
Input Offset Voltage VOS 0.3 1.1 0.6 2.0 1.2 2.5 mV
Average Input TCVOS 1 4 2 7 4 mV/∞C
Offset Voltage Drift
Input Offset Current los VCM = 0 V 5 20 8 40 20 50 nA
Input Bias Current IB VCM = 0 V 13 50 25 70 40 75 nA
Large-Signal VO = ± 10 V
Voltage Gain Avo RL = 10 kW 375 600 200 400 200 400 V/mV
RL = 2 kW 250 400 125 200 125 200
Input Voltage Range* IVR ± 11 ± 12 ± 11 ± 12 ± 11 ± 12 V
Output Voltage Swing VO RL ≥ 2 kW ± 12 ± 13 ± 12 ± 13 ± 12 ± 13 V
Common-Mode CMR VCM = ± 11 V 100 115 90 110 90 110 dB
Rejection
Power Supply PSRR VS = ± 4.5 V to ± 18 V 3.2 10 18 31.6 18 31.6 mV/V
Rejection Ratio
Supply Current
(All Amplifiers) ISY No Load 9.3 11 9.3 11 9.3 11 mA
*Guaranteed by CMR test.

ABSOLUTE MAXIMUM RATINGS 1 Package Type JA* JC Unit

Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 18 V
Differential Input Voltage2 . . . . . . . . . . . . . . . . . . . . . . ± 1.0 V 14-Lead Hermetic DIP(Y) 94 10 ∞C/W
Differential Input Current2 . . . . . . . . . . . . . . . . . . . . ± 25 mW 14-Lead Plastic DIP(P) 76 33 ∞C/W
Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . Supply Voltage
Output Short-Circuit Duration . . . . . . . . . . . . . . . Continuous 16-Lead SOIC (S) 88 23 ∞C/W
Storage Temperature Range *␪JA is specified for worst-case mounting conditions, i.e., ␪JA is specified for device
P, Y-Package . . . . . . . . . . . . . . . . . . . . . . –65∞C to +150∞C in socket for TO, CERDIP, PDIP packages; ␪JA is specified for device soldered to
Lead Temperature Range (Soldering, 60 sec) . . . . . . . . 300∞C printed circuit board for SO packages.
Junction Temperature (Ti) . . . . . . . . . . . . . –65∞C to +150∞C
Operating Temperature Range ORDERING GUIDE
OP471E, OP471F . . . . . . . . . . . . . . . . . . . –25∞C to +85∞C
OP471G . . . . . . . . . . . . . . . . . . . . . . . . . . . –40∞C to +85∞C TA = 25∞C Package Options Operating
NOTES VOS MAX Temperature
1
Absolute Maximum Ratings apply to packaged parts, unless otherwise noted. (mV) 14-Lead CERDIP Plastic Range
2
The OP471’s inputs are protected by back-to-back diodes. Current limiting
800 OP471EY IND
resistors are not used in order to achieve low noise performance. If differential
voltage exceeds ± 1.0 V, the input current should be limited to ± 25 mA. 1,500 OP471FY* IND
1,800 OP471GP XIND
1,800 OP471GS XIND
*Not for new design. Obsolete April 2002.
For military processed devices, please refer to the standard
microcircuit drawing (SMD) available at
www.dscc.dla.mil/programs/milspec/default.asp
5962-88565022A - OP471ARCMDA
5962-88565023A - OP471ATCMDA
5962-8856502CA - OP471AYMDA

CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although WARNING!
the OP471 features proprietary ESD protection circuitry, permanent damage may occur on
devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions
ESD SENSITIVE DEVICE
are recommended to avoid performance degradation or loss of functionality.

REV. A –3–
OP471–Typical Performance Characteristics
100 10
TA = 25C TA = 25C AT 10Hz
5mV 1s
VS = 15V

NOISE VOLTAGE – 100nV/DIV

40 100

VOLTAGE NOISE – nV/ Hz

VOLTAGE NOISE – nV/ Hz

30 8 90

20
AT 1kHz

10 6

5 10
4 0% TA = 25C
3 I/F CORNER = 5Hz 4
VS = 15V
2

0 2 4 6 8 10
1 2 TIME – Seconds
1 10 100 1k 0 5 10 15 20
FREQUENCY – Hz SUPPLY VOLTAGE – V

TPC 1. Voltage Noise Density TPC 2. Voltage Noise Density TPC 3. 0.1 Hz to 10 Hz Noise
vs. Frequency vs. Supply Voltage

100 400 20
TA = 25C VS = 15V TA = 25C
18

CHANGE IN OFFSET VOLTAGE –
V

VS = 15V VS = 15V
INPUT OFFSET VOLTAGE –
V

40 16
300
VOLTAGE NOISE – nV/ Hz

30
14
20
12

10 200 10

8
5
4 6
3 100
I/F CORNER = 5Hz 4
2
2

1 0 0
1 10 100 1k –75 –50 –25 0 25 50 75 100 125 0 1 2 3 4 5
FREQUENCY – Hz TEMPERATURE – C TIME – Minutes

TPC 4. Current Noise Density TPC 5. Input Offset Voltage vs. TPC 6. Warm-Up Offset
vs. Frequency Temperature Voltage Drift

20 10 10
VS = 15V VS = 15V TA = 25C
9
VCM = 0V VCM = 0V VS = 15V
INPUT OFFSET CURRENT – nA

8 9
INPUT BIAS CURRENT – nA
INPUT BIAS CURRENT – nA

15
7

6 8

10 5

4 7
3
5
2 6
1

0 0 5
–75 –50 –25 0 25 50 75 100 125 –75 –50 –25 0 25 50 75 100 125 –12.5 –7.5 –2.5 2.5 7.5 12.5
TEMPERATURE – C TEMPERATURE – C COMMON-MODE VOLTAGE – V

TPC 7. Input Bias Current vs. TPC 8. Input Offset Current vs. TPC 9. Input Bias Current vs.
Temperature Temperature Common-Mode Voltage

–4– REV. A
 OP471
130 10 10
TA = 25C VS = 15V
120 TA = +25C
VS = 15V 9

TOTAL SUPPLY CURRENT – mA

TOTAL SUPPLY CURRENT – mA
110
100 8 TA = +125C 8

90 7
CMR – dB

80 TA = –55C
70 6 6

60
5
50
40 4 4

30
3
20
10 2 2
1 10 100 1k 10k 100k 1M 0 5 10 15 20 –75 –50 –25 0 25 50 75 100 125
FREQUENCY – Hz SUPPLY VOLTAGE – V TEMPERATURE – C

TPC 10. CMR vs. Frequency TPC 11. Total Supply Current TPC 12. Total Supply Current
vs. Supply Voltage vs. Temperature
140 140 80
130 TA = 25C TA = 25C TA = 25C
130
VS = 15V VS = 15V VS = 15V
120 120
110 110 60

CLOSED-LOOP GAIN – dB
OPEN-LOOP GAIN – dB

100 100
90 90
40
PSR – dB

80 80
–PSR
70 70
60 60 20
50 +PSR 50
40 40
30 30 0
20 20
10 10
0 0 –20
1 10 100 1k 10k 100k 1M 10M 100M 1 10 100 1k 10k 100k 1M 10M 100M 1k 10k 100k 1M 10M
FREQUENCY – Hz FREQUENCY – Hz FREQUENCY – Hz

TPC 13. PSR vs. Frequency TPC 14. Open-Loop Gain vs. Frequency TPC 15. Closed-Loop Gain
vs. Frequency
25 80 2000 80 8
TA = 25C TA = 25C VS = 15V

GAIN-BANDWIDTH PRODUCT – MHz

20 VS = 15V 100 RL = 10k GBW
PHASE MARGIN – Degrees
OPEN-LOOP GAIN – V/mV
PHASE SHIFT – Degrees

PHASE
OPEN-LOOP GAIN – dB

1500 70 6
15 120

10 140
GAIN PHASE MARGIN 1000 60 4
5 = 57 160

0 180
500 50 2

–5 200

–10 220 0 40 0
1 2 3 4 5 6 7 8 9 10 0 5 10 15 20 –75 –50 –25 0 25 50 75 100 125 150
FREQUENCY – MHz SUPPLY VOLTAGE – V TEMPERATURE – C

TPC 16. Open-Loop Gain, TPC 17. Open-Loop Gain vs. TPC 18. Gain-Bandwidth Product,
Phase Shift vs. Frequency Supply Voltage Phase Margin vs. Temperature

REV. A –5–
OP471
28 20 360
TA = 25C TA = 25C TA = 25C
VS = 15V 18
24 VS = 15V VS = 15V
PEAK-TO-PEAK AMPLITUDE – V

THD = 1% 300
16

OUTPUT IMPEDANCE – 
MAXIMUM OUTPUT – V
20 POSITIVE
14 240
SWING
12
16
10 NEGATIVE 180
12 SWING
8
120
8 6
AV = 100
4
60
4
2 AV = 1
0 0 0
1k 10k 100k 1M 10M 100 1k 10k 100 1k 10k 100k 1M 10M 100M
FREQUENCY – Hz LOAD RESISTANCE –  FREQUENCY – Hz

TPC 19. Maximum Output Swing TPC 20. Maximum Output Voltage TPC 21. Closed-Loop Output
vs. Frequency vs. Load Resistance Impedance vs. Frequency

9.0 170 1
TA = 25C TA = 25C
160
VS = 15V

TOTAL HARMONIC DISTORTION – %

VS = 15V
8.5 150 VO = 20V p-p TO 100kHz
CHANNEL SEPARATION – dB

VO = 10V p-p
140 RL = 2k
–SR
SLEW RATE – V/
s

8.0 130 0.1

+SR
120
7.5 110
100
7.0 90 0.01
80 AV = 10
6.5 70
60 AV = 1
6.0 50 0.001
–75 –50 –25 0 25 50 75 100 125 10 100 1k 10k 100k 1M 10M 10 100 1k 10k
TEMPERATURE – C FREQUENCY – Hz FREQUENCY – Hz

TPC 22. Slew Rate vs. Temperature TPC 23. Channel Separation vs. TPC 24. Total Harmonic Distortion
Frequency vs. Frequency

TA = 25C TA = 25C
VS = 15V VS = 15V
100 100
AV = 1 AV = 1
90 90

10 10
0% 0%

5V 5µs 50mV 0.2µs

TPC 25. Large-Signal Transient TPC 26. Small-Signal Transient

Response Response

–6– REV. A
 OP471
5k 100

500

1/4
OP471 V1 20V p-p

TOTAL NOISE – nV/ Hz

OP11

50k 10 OP400

50 OP471

1/4
OP471 V2
OP470
RESISTOR
NOISE ONLY

V1 1
CHANNEL SEPARATION = 20 LOG
V2 / 1000 100 1k 10k 100k
RS – SOURCE RESISTANCE – 
Figure 2. Channel Separation Test Circuit
Figure 4. Total Noise vs. Source Resistance (Including
Resistor Noise) at 1 kHz
+18V
2 4 6 100
1 7
A B
3 5
+1V 11 +1V

–18V

TOTAL NOISE – nV/ Hz

OP11

OP400

9 13 10
8 14 OP471
C D
10 12
–1V –1V
OP470

RESISTOR
Figure 3. Burn-In Circuit NOISE ONLY

1
100 1k 10k 100k
APPLICATIONS INFORMATION RS – SOURCE RESISTANCE – 

Voltage and Current Noise Figure 5. Total Noise vs. Source Resistance (Including
The OP471 is a very low-noise quad op amp, exhibiting a typical Resistor Noise) at 10 Hz
voltage noise of only 6.5 Hz @ 1 kHz. The low noise character-
istic of the OP471 is, in part, achieved by operating the input Figure 4 shows the relationship between total noise at 1 kHz
transistors at high collector currents since the voltage noise is and source resistance. For RS < 1 kW the total noise is domi-
inversely proportional to the square root of the collector current. nated by the voltage noise of the OP471. As RS rises above 1 kW,
Current noise, however, is directly proportional to the square total noise increases and is dominated by resistor noise rather
root of the collector current. As a result, the outstanding voltage than by voltage or current noise of the OP471. When RS exceeds
noise performance of the OP471 is gained at the expense of current 20 kW, current noise of the OP471 becomes the major contributor
noise performance which is typical for low noise amplifiers. to total noise.
To obtain the best noise performance in a circuit, it is vital to Figure 5 also shows the relationship between total noise and source
understand the relationship between voltage noise (en), current resistance, but at 10 Hz. Total noise increases more quickly
noise (in), and resistor noise (et). than shown in Figure 4 because current noise is inversely pro-
portional to the square root of frequency. In Figure 5, current
Total Noise and Source Resistance noise of the OP471 dominates the total noise when RS > 5 kW.
The total noise of an op amp can be calculated by:
From Figures 4 and 5, it can be seen that to reduce total noise,
En = (e n ) + (inR S ) + (et )
2 2 2 source resistance must be kept to a minimum. In applications
with a high source resistance, the OP400, with lower current
noise than the OP471, will provide lower total noise.
where:
En = total input referred noise
en = op amp voltage noise
in = op amp current noise
et = source resistance thermal noise
RS = source resistance
The total noise is referred to the input and at the output would
be amplified by the circuit gain.

REV. A –7–
OP471
1000
OP11
For reference, typical source resistances of some signal sources
are listed in Table I.
OP400
TABLE I.
PEAK-TO-PEAK NOISE – nV

Source
OP471
Device Impedance Comments
< 500 W
100
Strain gauge Typically used in
OP470
low-frequency applications.
RESISTOR
NOISE ONLY
Magnetic < 1,500 W Low IB very important to reduce
tapehead self-magnetization problems
when direct coupling is used.
OP471 IB can be neglected.
10
100 1k 10k
RS – SOURCE RESISTANCE – 
100k
Magnetic < 1,500 W Similar need for low IB in direct
phonograph coupled applications. OP471
Figure 6. Peak-to-Peak Noise (0.1 Hz to 10 Hz) vs. Source cartridges will not introduce any
Resistance (Includes Resistor Noise) self -magnetization problem.
Figure 6 shows peak-to-peak noise versus source resistance over Linear variable < 1,500 W Used in rugged servo-feedback
the 0.1 Hz to 10 Hz range. Once again, at low values of RS, the differential applications. Bandwidth of
voltage noise of the OP471 is the major contributor to peak-to-peak transformer interest is 400 Hz to 5 kHz.
noise. Current noise becomes the major contributor as RS increases.
The crossover point between the OP471 and the OP400 for *For further information regarding noise calculations, see “Minimization of
peak-to-peak noise is at RS = 17 W. Noise in Op Amp Applications,” Application Note AN-15.

The OP470 is a lower noise version of the OP471, with a typical

noise voltage density of 3.2 nV/÷Hz @ 1 kHz. The OP470 offers
lower offset voltage and higher gain than the OP471, but is a slower
speed device, with a slew rate of 2 V/ms compared to a slew rate
of 8 V/ms for the OP471.

R3
1.24k
R1
5

OP471 C1
R2 2
F
5 DUT
OP27E
C4
R6 0.22
F
R5 600k
909
R10 R11
65.4k 65.4k
R4 D1 D2 OP15E R14
200 1N4148 1N4148 4.99k
C3 eOUT
R9 0.22
F OP15E
306k C5
R13 1
F
5.9k
R8
10k C2
R12
0.032
F
10k
GAIN = 50,000
VS = 15V

Figure 7. Peak-to-Peak Voltage Noise Test Circuit (0.1 Hz to 10 Hz)

–8– REV. A
 OP471
Noise Measurements - Peak-to-Peak Voltage Noise 100

The circuit of Figure 7 is a test setup for measuring peak-to-peak

voltage noise. To measure the 500 nV peak-to-peak noise speci- 80
fication of the OP471 in the 0.1 Hz to 10 Hz range, the following
precautions must be observed:
60
1. The device must be warmed up for at least five minutes. As

GAIN – dB
shown in the warm-up drift curve, the offset voltage typically
changes 13 mV due to increasing chip temperature after 40
power-up. In the 10-second measurement interval, these
temperature-induced effects can exceed tens-of-nanovolts.
20
2. For similar reasons, the device must be well-shielded from
air currents. Shielding also minimizes thermocouple effects.
3. Sudden motion in the vicinity of the device can also “feedthrough” 0
0.01 0.1 1 10 100
to increase the observed noise. FREQUENCY – Hz

4. The test time to measure 0.1 Hz to 10 Hz noise should not exceed
10 seconds. As shown in the noise-tester frequency-response curve
of Figure 8, the 0.1 Hz corner is defined by only one pole. The
test time of 10 seconds acts as an additional pole to eliminate
noise contribution from the frequency band below 0.1 Hz.
5. A noise voltage density test is recommended when measuring
noise on a large number of units. A 10 Hz noise voltage density
measurement will correlate well with a 0.1 Hz to 10 Hz
peak-to-peak noise reading, since both results are determined
by the white noise and the location of the 1/f corner frequency.
6. Power should be supplied to the test circuit by well bypassed,
low noise supplies, e.g, batteries. These will minimize output
noise introduced through the amplifier supply pins.
Figure 8. 0.1 Hz to 10 Hz Peak-to-Peak Voltage Noise
Test Circuit Frequency Response
Noise Measurement - Noise Voltage Density
The circuit of Figure 9 shows a quick and reliable method of
measuring the noise voltage density of quad op amps. Each
individual amplifier is series connected and is in unity-gain, save
the final amplifier which is in a noninverting gain of 101. Since
the ac noise voltages of each amplifier are uncorrelated, they
add in rms fashion to yield:
e OUT = 101 Ê e nA 2 + e nB 2 + e nC 2 + e nD 2 ˆ
Ë ¯
The OP471 is a monolithic device with four identical amplifiers.
The noise voltage density of each individual amplifier will
match, giving:

e OUT = 101 Ê 4e n 2 ˆ = 101 (2e n )

Ë ¯

R1 R2
100 10k

1/4
eOUT
OP471
1/4
TO SPECTRUM ANALYZER
OP471
1/4
OP471
1/4
OP471 eOUT (nV Hz) = 101(2en)
VS = 15V

Figure 9. Noise Voltage Density Test Circuit

REV. A –9–
OP471
Noise Measurement - Current Noise Density adds phase shift in the feedback network and reduces stability. A
The test circuit shown in Figure 10 can be used to measure current simple circuit to eliminate this effect is shown in Figure 11. The
noise density. The formula relating the voltage output to current added components, C1 and R3, decouple the amplifier from the
noise density is: load capacitance and provide additional stability. The values of
C1 and R3 shown in Figure 11 are for load capacitances of up
to 1,000 pF when used with the OP471.
( )
2
Ê e nOUT ˆ 2
Á ˜ - 40nV / Hz In applications where the OP471’s inverting or noninverting inputs
Ë G ¯
in = are driven by a low source impedance (under 100 W) or connected
RS to ground, if V+ is applied before V–, or when V– is disconnected,
excessive parasitic currents will flow.
where:
Most applications use dual tracking supplies and with the device
G = gain of 10,000 supply pins properly bypassed, power-up will not present a
RS = 100 kW source resistance problem. A source resistance of at least 100 W in series with all
Capacative Load Driving and Power Supply Considerations inputs (Figure 11) will limit the parasitic currents to a safe level
The OP471 is unity-gain stable and is capable of driving large if V– is disconnected. It should be noted that any source resistance,
capacitive loads without oscillating. Nonetheless, good supply even 100 W, adds noise to the circuit. Where noise is required to
bypassing is highly recommended. Proper supply bypassing be kept at a minimum, a germanium or Schottky diode can be
reduces problems caused by supply line noise and improves the used to clamp the V– pin and eliminate the parasitic current
capacitive load driving capability of the OP471. flow instead of using series limiting resistors. For most applica-
tions, only one diode clamp is required per board or system.
R3
1.24k
Rf
R1 R2
5 100k

OP471
DUT
OP27E en OUT TO
SPECTRUM ANALYZER OP471
R5
8.06k 8V/
s

R4
200
GAIN = 10,000 Figure 12. Pulsed Operation
VS = 15V
Unity-Gain Buffer Applications
Figure 10. Current Noise Density Test Circuit
When Rf £ 100 W and the input is driven with a fast, large signal
pulse (>1 V), the output waveform will look as shown in Figure 12.
V+ C2
10
F
During the fast feedthrough-like portion of the output, the input
+ protection diodes effectively short the output to the input, and a
C3 current, limited only by the output short-circuit protection, will
0.1
F
be drawn by the signal generator. With Rf ≥ 500 W, the output
is capable of handling the current requirements (IL £ 20 mA at
R2 10 V); the amplifier will stay in its active mode and a smooth
C1 transition will occur.
R1
VIN 200pF R3
50
When Rf > 3 kW, a pole created by Rf and the amplifier’s input
OP471 VOUT capacitance (2.6 pF) creates additional phase shift and reduces
100* C4
10
F CL phase margin. A small capacitor (20 pF to 50 pF) in parallel with
+ 1000pF
Rf helps eliminate this problem.
C5
*
0.1
F
APPLICATIONS
Low Noise Amplifier
*SEE TEXT
V– A simple method of reducing amplifier noise by paralleling
PLACE SUPPLY DECOUPLING
CAPACITORS AT OP471 amplifiers is shown in Figure 13. Amplifier noise, depicted in
Figure 14, is around 5 nV/÷Hz @ 1 kHz (R.T.I.). Gain for each
paralleled amplifier and the entire circuit is 100. The 200 W
Figure 11. Driving Large Capacitive Loads
resistors limit circulating currents and provide an effective output
In the standard feedback amplifier, the op amp’s output resistance resistance of 50 W. The amplifier is stable with a 10 nF capacitive
combines with the load capacitance to form a lowpass filter that load and can supply up to 30 mA of output drive.

–10– REV. A
 OP471
High-Speed Differential Line Driver
The circuit of Figure 15 is a unique line driver widely used in
professional audio applications. With ± 18 V supplies, the line

NOISE DENSITY – 0.58nV/ Hz/DIV

100
driver can deliver a differential signal of 30 V p-p into a 1.5 kW 90

REFERRED TO INPUT
load. The output of the differential line driver looks exactly like
a transformer. Either output can be shorted to ground without
changing the circuit gain of 5, so the amplifier can easily be set
for inverting, noninverting, or differential operation. The line
driver can drive unbalanced loads, like a true transformer.
10
+15V 0%

VIN R3
1/4 200
R1 OP471E
50
Figure 14. Noise Density of Low-Noise Amplifier, G = 100
R2
–15V 5k
R4
10k
R6
1/4 200
R4 R11
OP471E 50
50 1/4 –OUT
R5 OP471
5k
VOUT = 100VIN R2 R8
2k 10k
R14
R9 1k
200 IN R7
1/4 2k
R7 OP471E R1 1/4 R13
50 10k OP471 10k
R6 R9
R8 2k
5k 10k R12
1k

R12 R10
200 R3 50
1/4 2k 1/4 +OUT
R10 OP471E OP471
50
R11 R5
5k 10k

Figure 13. Low-Noise Amplifier Figure 15. High-Speed Differential Line Driver
High-Output Amplifier
The amplifier shown in Figure 16 is capable of driving 20 V p-p
into a floating 400 W load. Design of the amplifier is based on a
bridge configuration. A1 amplifies the input signal and drives
the load with the help of A2. Amplifier A3 is a unity-gain inverter
which drives the load with help from A4. Gain of the high output
amplifier with the component values shown is 10, but can
easily be changed by varying R1 or R2.

+15V
C1
10
F R5
+ 5k
C2
0.1
F
R2 R6
9k 5k
R1
1k
R3 R7
1/4 50 50 1/4
OP471E OP471E
A1 A3
VIN
C3
0.1
F
R4 R8
1/4 50 RL 50 1/4
C4
10
F OP471E OP471E
+ A2 A4

–15V

Figure 16. High-Output Amplifier

REV. A –11–
OP471
Quad Programmable Gain Amplifier where n equals the decimal equivalent of the 8-bit digital code
The combination of the quad OP471 and the DAC8408, a quad present at the DAC. If the digital code present at the DAC
8-bit CMOS DAC, creates a space-saving quad programmable gain consists of all zeros, the feedback loop will be open causing the
amplifier. The digital code present at the DAC, which is easily op amp output to saturate. The 20 MW resistors placed in parallel
set by a microprocessor, determines the ratio between the fixed with the DAC feedback loop eliminates this problem with a very
DAC feedback resistor and the impedance the DAC ladder presents small reduction in gain accuracy.
to the op amp feedback loop. Gain of each amplifier is:
VOUT 256
= –
VIN n

DAC-8408ET VDD

RFBA
VINA VREF A

+15V
R1
IOUT1A 20M

DAC A 1/4
OP470E VOUTA

IOUT2A/2B

RFBB –15V
VINB VREFB

R2
IOUT1B 20M
DAC B

1/4
OP470E VOUTB

RFBC
VINC VREF C

R3
IOUT1C 20M

DAC C 1/4
OP470E VOUTC

IOUT2C/2D

RFBD
VIND VREF D

R4
IOUT1D 20M
DAC D

1/4
OP470E VOUTD
DAC DATA BUS
PINS 9 (LSB) – 16 (MSB)

DGND

Figure 17. Quad Programmable Gain Amplifier

–12– REV. A
 OP471
Low Phase Error Amplifier R2 R2 = R1

The simple amplifier depicted in Figure 18 utilizes monolithic R2

matched operational amplifiers and a few resistors to substan- K1

tially reduce phase error compared to conventional amplifier

1/4
designs. At a given gain, the frequency range for a specified phase OP471E V2
accuracy is over a decade greater than for a standard single op A2
amp amplifier.
The low phase error amplifier performs second-order frequency
compensation through the response of op amp A2 in the feed- R1
1/4 R1 K1
back loop of A1. Both op amps must be extremely well matched OP471E
in frequency response. At low frequencies, the A1 feedback loop VIN
A1
forces V2/(K1 + 1) = VIN. The A2 feedback loop forces Vo/(K1 +1) VO
= V2/(K1 + 1) yielding an overall transfer function of VO/VIN = VO = (K1 + 1) V IN
K1 + 1. The dc gain is determined by the resistor divider at
the output, VO, and is not directly affected by the resistor divider ASSUME: A1 AND A2 ARE MATCHED.
around A2. Note that similar to a conventional single op amp 
AO (s) = sT
amplifier, the dc gain is set by resistor ratios only. Minimum
gain for the low phase error amplifier is 10. Figure 18. Low Phase Error Amplifier
Figure 19 compares the phase error performance of the low
phase error amplifier with a conventional single op amp amplifier 0
and a cascaded two-stage amplifier. The low phase error amplifier
–1
shows a much lower phase error, particularly for frequencies where
␻/␤␻T < 0.1. For example, phase error of –0.1∞ occurs at 0.002 ␻/␤␻T

PHASE SHIFT – Degrees

for the single op amp amplifier, but at 0.11 ␻/␤␻T for the low –2 SINGLE OP AMP
(CONVENTIONAL
phase error amplifier. DESIGN)
–3
For more detailed information on the low phase error amplifier, CASCADED
(TWO STAGES)
see Application Note AN-107. –4

–5
LOW-PHASE ERROR
AMPLIFIER
–6

–7
0.001 0.005 0.01 0.05 0.1 0.5 1
FREQUENCY RATIO – 1/, /T

Figure 19. Phase Error Comparison

REV. A –13–
OP471
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).

14-Lead PDIP Package

(N-14)

0.795 (20.19)
0.725 (18.42)

14 8 0.280 (7.11)
1 7 0.240 (6.10)
0.325 (8.25)
PIN 1
0.100 (2.54) 0.300 (7.62)
0.060 (1.52)
BSC
0.015 (0.38) 0.195 (4.95)
0.210 (5.33)
MAX 0.130 0.115 (2.93)
0.160 (4.06) (3.30)
MIN
0.115 (2.93) 0.015 (0.381)
0.022 (0.558) 0.070 (1.77) SEATING 0.008 (0.204)
PLANE
0.014 (0.356) 0.045 (1.15)

14-Lead CERDIP Package

(Q-14)

0.005 (0.13) MIN 0.098 (2.49) MAX

14 8
0.310 (7.87)
PIN 1
0.220 (5.59)
1 7
0.320 (8.13)
0.100 (2.54) BSC 0.290 (7.37)
0.785 (19.94) MAX 0.060 (1.52)
0.200 (5.08) 0.015 (0.38)
MAX 0.150
0.200 (5.08) (3.81)
0.125 (3.18) MIN
0.015 (0.38)
0.023 (0.58) 0.070 (1.78) SEATING 15 0.008 (0.20)
PLANE
0.014 (0.36) 0.030 (0.76) 0

16-Lead SOIC Package

(R-16)

0.4133 (10.50)
0.3977 (10.00)

16 9
0.2992 (7.60)
0.2914 (7.40)
0.4193 (10.65)
1 8
0.3937 (10.00)

PIN 1 0.1043 (2.65)

0.050 (1.27) 0.0291 (0.74)
BSC 0.0926 (2.35) 45
0.0098 (0.25)

8
0.0118 (0.30) 0.0192 (0.49) SEATING 0 0.0500 (1.27)
0.0125 (0.32)
0.0040 (0.10) 0.0138 (0.35) PLANE 0.0157 (0.40)
0.0091 (0.23)

–14– REV. A
 OP471
Revision History
Location Page
Data Sheet changed from REV. 0 to REV. A.
Edits to FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Edits to ELECTRICAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Edits to ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Edits to ORDERING GUIDE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Deleted DICE CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Deleted WAFER TEST CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

REV. A –15–
–16–
PRINTED IN U.S.A. C00307–0–4/02(A)