Lesson 5

Loop Execution and Data Sharing

TOPICS
A. Timing Express VIs
B. Loop Timers
C. Benchmarking Loop Rates
D. Parallel Loop Execution
E. Shared Resources
F. FPGA FIFOs

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A. Timing Express VIs

Loop Timer Express VI

• Times loop rate
Wait Express VI
• Adds explicit delay
• Controls pulse length
• Adds trigger delay
Tick Count Express VI
• Returns current value of FPGA clock
• Benchmarks loop rates
• Creates custom timers

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A. Timing Express VIs
The Timing palette contains most of the FPGA timing Express VIs, except
those related to the Timed Loop. Timing control is critical to your FPGA
application. The timing Express VIs include the Loop Timer, Wait, and Tick
Count Express VIs.
Use the Loop Timer Express VI to control a For Loop or While Loop and set
the iteration rate of the loop. A common use of the Loop Timer Express VI is
to control the acquisition or update rate of an analog or digital I/O function.
The Wait Express VI adds an explicit delay between two operations on the
FPGA. Use the Wait Express VI to control the pulse length of a digital output
or add a trigger delay between the trigger signal and the resulting operation.
The Tick Count Express VI returns the current value of the FPGA clock. Use
the Tick Count Express VI to benchmark loop rates or create your own custom
timers.

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Timing Express VIs (continued)

Size\Units Ticks μs ms
32-bit 1 to 4.29*109 ticks 1 μs to 72 1 ms to 50 days
seconds
16-bit 1 to 65,000 ticks 1 μs to 65 ms 1 ms to 65
seconds
8-bit 1 to 256 ticks 1 μs to 256 us 1 ms to 256 ms

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Each timing Express VI has a configuration dialog box that appears when you first add the VI to
the block diagram or when you right click the VI and select Properties. The dialog box allows
you to configure the timing units and the size of the internal counter. The available Counter Units
include ticks; a single clock cycle, the length of which is determined by the clock rate for which
the VI is compiled; microseconds (µs), and milliseconds (ms). The Size of Internal Counter value
determines the maximum time the timer can track. The free running counter rolls over when the
counter reaches the maximum of Size of Internal Counter specified in the configuration dialog
box. To save space on the FPGA, you should use the smallest Size of Internal Counter possible for
the FPGA VI.
The configuration dialog box for the Loop Timer Express VI includes the following options:
Counter Units—Unit of time the VI uses for the counter.
• Ticks—Sets the counter units to a single clock cycle, the length of which is determined by the
clock rate for which the VI is compiled.
• mSec—Sets the counter units to µs.
• mSec—Sets the counter units to ms.
Size of Internal Counter—Specifies the maximum time (8, 16, or 32 bits) a timer can track. To
save space on the FPGA, use the smallest.

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B. Loop Timers

• Code structure is the same

• Loop Timer does not wait the first time it is called
• Wait Express VI executes every iteration of the While Loop

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B. Loop Timers
You can time your FPGA code using the Loop Timer Express VI
or the Wait Express VI. The Loop Timer and Wait Express VIs
differ in how they affect code execution.
If you use the Loop Timer Express VI, during the first iteration
the code executes right away.
If you use the Wait Express VI, during the first iteration the code
waits for the duration of the specified wait statement.
For both cases, the options for choosing the timing units and the
counter size are available.
The Flat Sequence structure controls the flow of data and ensures
that the wait occurs before the value on the digital output
changes.

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C. Benchmarking Loop Rates
To benchmark FPGA VI speed, use Tick Count Express VIs
• Requires additional code for testing
− Remove additional code in final application
Use Tick Count Express VI to determine execution speed
• Get initial time
• Execute code
• Get final time
• Calculate the difference
− Remove code later
• Timestamp measurements
done in parallel
− Does not affect execution speed

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C. Benchmarking Loop Rates
It is important to benchmark the rate at which a VI runs. Because
the FPGA code runs on the FPGA hardware, you cannot
determine the precise timing until you compile the code. After
you compile the code, the Tick Count Express VI to benchmark
the VI and determine execution speed.
You must be careful of Tick Count rolling over. Because Tick
Count has a maximum representation of 32 bits, the greatest
number of ticks that it can count before returning to 0 is 232 =
4,294,967,296. However, when the clock runs at 40 MHz, the
clock rolls over about every 107 seconds. If the code you are
benchmarking takes more than 107 seconds to execute, the
elapsed time result will be much lower than expected because the
final Tick Count rolled over to 0.

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Benchmarking with the Tick Count Express VI

• Timestamp each iteration

• Calculate the difference
− Remove code later
• Timestamp measurements done
in parallel
− Does not affect execution speed

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The figure above shows an example that uses the Tick Count
Express VI to benchmark the execution speed of a While
Loop.
Timestamp measurements are done in parallel because of the
way the FPGA code is implemented. As long as any new
code is not made within the same combinatorial path as
another set of code the code execution times are independent
from one another. Because of this behavior, whenever you
add code to an FPGA VI for benchmarking, it has no affect
on the loop execution time, provided that the code you are
benchmarking takes longer to execute than the three cycles
required to obtain and observe the loop rate.

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D. Parallel Loop Execution

Dictate Loop Execution Order

• Use FIFOs and occurrences to:
− Determine program flow and loop execution order
− Synchronize the execution of parallel loops
Data Sharing
• Pass data between parallel loops on the FPGA by using FIFOs,
memory, or local and global variables

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D. Parallel Loop Execution
By default, parallel LabVIEW loops execute independently
and in parallel when implemented in FPGA hardware. In
order to time loops off each other, you can affect the
execution order or sequence of events so that each task is
performed when you want. A structure commonly used for
controlling the program flow and synchronizing parallel
loops are local FPGA FIFOs.
You can use FIFOs, memory, or local variables to transfer
data between parallel loops.

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 Exercise 5-1: Custom Triggering

Create a VI that reads and writes to analog I/O and sets a

digital line high when a threshold value is reached.
GOAL

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E. Shared Resources
Before a task can begin using a shared resource, it must wait
until it is free.

Task 1 Shared Task 2

Resource
Running Waiting

After Task 1 finishes, Task 2 can proceed.

Task 1 Shared Task 2

Resource
Waiting Running
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• E. Shared Resources
• Sharing resources between two different tasks or loops can affect the
deterministic execution of the tasks, even when they are in parallel.
Resources that may only be accessed by one task at a time can
prevent code from executing independently and are referred to as
shared resources.
• As shown above, Task 1 runs and accesses a shared resource that can
be accessed by only one task at a time. Task 2 must wait until Task 1
releases the resource before accessing it. After Task 1 finishes, Task 2
can access the shared resource and execute while Task 1 waits for the
shared resource to be free.
• Using shared resources causes jitter within the application. To
maximize the determinism of our VI, we need to avoid shared
resources.

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What Are Shared Resources?

• Digital outputs on most targets

• Analog inputs on most targets
• Analog output on most targets
• Memory and FIFOs
• Non-reentrant subVIs
• Local and global variables
• Digital inputs on some targets

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The following list shows some components that are considered shared resources:
− Digital outputs on most targets
− Analog inputs on most targets
− Analog output on most targets
− Memory and FIFOs
− Non-reentrant VIs
− Local and global variables
− Digital inputs on some targets (such as C Series modules with more than 8 inputs)
• Some LabVIEW FPGA Module applications contain shared resources that are accessed by
multiple objects, such as functions or subVIs, in an FPGA VI. Possible shared resources
include digital output lines, analog lines, memory items, FIFOs, the interrupt line, local and
global variables, and non-reentrant subVIs. Each shared resource contains one or more resource
interfaces. A resource interface communicates between objects and shared resources. Resource
contention occurs when you include two or more objects on the FPGA VI block diagram that
simultaneously request access to the same shared resource through the same resource interface.
• For more details view the LabVIEW Help Topic: Managing Shared Resources (FPGA Module)

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Shared Resources Example

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The figure above contains a shared resource. Can you
find it?
If you guessed the analog input function, you are
correct! Analog inputs from the same channel are shared
resources. While one loop reads from the analog input
channel, the other loop must wait until the top loop
finishes reading from that channel before it can execute.

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Non-Reentrant subVIs

Non-reentrant
• Default for VIs created under
My Computer or an RT target
• VI is shared when used
as a subVI
• Only one instance on the
FPGA device
Reentrant VI (default for FPGA)
• Default for VIs created under an FPGA target
• Separate set of gates on the FPGA device for each instance on the
block diagram (typically uses more space)

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Another common shared resource is a subVI. You can configure a subVI as a single
instance shared among multiple callers, also known as a non-reentrant subVI. You also
can configure a subVI as reentrant to allow parallel execution. By default, VIs created
under an FPGA target are reentrant.
Caution VIs not created under an FPGA target or created using a previous
version of the LabVIEW FPGA Module are non-reentrant by default.
Moving or copying VIs to or from an FPGA target does not change the
reentrancy
If you use a non-reentrant subVI in an FPGA VI, only a single copy of the subVI
becomes hardware and all callers share the hardware resource. If you use a reentrant
subVI in an FPGA VI, each instance of the subVI on the block diagram becomes a
separate hardware resource. For example, if you have five instances of an event counter
configured as a reentrant subVI on the block diagram, LabVIEW implements five
independent copies of the event counter hardware on the FPGA.
In general, configuring a subVI as reentrant improves speed because instances of the
subVI execute in parallel. On the other hand, configuring a subVI as non-reentrant
generally saves space because each instance of the subVI shares the same FPGA
hardware. However, when you use multiple instances of a non-reentrant subVI, extra
FPGA resources are used for arbitration. In some cases, the arbitration resources can
cause a non-reentrant configuration to consume as much or more space on the FPGA as
a reentrant configuration.

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F. FPGA FIFOs

FIFO—First-in first-out buffer

• The first data item written is the
first item read and removed
− FPGA FIFO is similar to a fixed length
queue
• Create target-scoped FIFOs from
the Project Explorer
• Create VI-scoped FIFOs from the
block diagram
− Found in the Memory & FIFO Palette

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F. FPGA FIFOs
A common buffering technique with LabVIEW FPGA is a
FIFO buffer where the first data item written to memory is
the first item read and removed from memory. The
LabVIEW Basics II: Development course describes a similar
structure called a queue.
An FPGA FIFO functions like a fixed-length queue where
multiple data items can be written to and read from memory.
Unlike a queue, an FPGA FIFO ensures deterministic
behavior by imposing a size restriction on the data, and both
the reader and the writer can access the data simultaneously.

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Configuring Target-Scoped FPGA FIFOs

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To create a FIFO, right-click the FPGA target in the Project Explorer window
and select New»FIFO to display the FPGA FIFO Properties dialog box.
Configure the properties of the FIFO in the FPGA FIFO Properties dialog box,
shown above.
Select Target-Scoped from the Type pull-down menu in the Properties dialog
box if you want to use a target-scoped FIFO.
Refer to the Memory Allocation for FPGA FIFO Memory Types section for
more information about DMA FIFOs.
Because of the fixed-size restriction, a FIFO can be a lossy communication
method. Write and read operations typically occur in separate loops. A larger
FIFO gives the read loop more time to catch up if it falls behind; so, use the
largest FIFO possible unless your application is memory constrained.
LabVIEW preserves the existing data when the FPGA FIFO is full. Rather
than overwriting the oldest element, the FIFO Write function returns TRUE in
the Timed Out? output to indicate the FPGA FIFO is full and no new data is
being stored in the FIFO.

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Configuring VI-Scoped FPGA FIFOs

VI-Scoped FIFOs
• Data only shared within that
particular VI
Configuration
• Place VI-Scoped FIFO
Configuration node on block diagram
• Double-click node to open FIFO Properties
• Set Properties and click OK
• For each Clear, Write or Read method, right-click and select the
VI-Scoped FIFO that you created

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VI–scoped FIFOs
Use to transfer data to and from loops. Use VI-scoped FIFOs if you want to create a
FIFO that you can use only within a single VI. If you send an FPGA VI with a VI-
scoped FIFO to another user, you do not need to send the LabVIEW project because the
FIFO does not include a corresponding item in the Project Explorer window. If you
use a VI-scoped FIFO in a reentrant FPGA VI, LabVIEW creates a separate copy of the
FIFO for each instance of the VI, which allows you to create reusable subVIs while
avoiding resource conflicts.
To create a VI-scoped FIFO, place a VI-Scoped FIFO Configuration node on the block
diagram, right-click the node, and select Properties from the shortcut menu. The FPGA
FIFO Properties dialog box appears.
VI-Scoped FIFO Configuration Details
Use the FIFO Read and FIFO Write functions to read from or write to the VI-scoped
FIFO. FIFOs are initially empty. If you reset the FPGA VI, LabVIEW empties the
FIFO.
If you use a VI-scoped FIFO in a reentrant FPGA VI, LabVIEW creates a separate copy
of the FIFO for each instance of the VI, which avoids resource conflicts.
You can create a VI-scoped FIFO with the same name as a target-scoped FIFO or DMA
FIFO. You also can create VI-scoped FIFOs with the same name in different VIs.
However, you cannot create multiple VI-scoped FIFOs with the same name in the same
VI.

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FPGA FIFO Memory Types

Memory types (disabled for DMA FIFOs)

• Flip-Flop—Uses gates on the FPGA to provide the fastest
performance. Recommended only for very small FIFOs < 100 bytes.
• Look-up Table (LUT)—Stores data in a Lookup Table available on the
FPGA. Recommended only for small FIFOs < 300 bytes.
• Block Memory - Use to preserve FPGA gates and LUTs for the VI.

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The Memory Type property specifies the type of storage the FIFO uses on the FPGA. This option
is disabled if you select DMA from the Type pull-down menu.
You cannot use FIFOs with a Memory Type of Flip-Flops or Lookup Table across multiple clock
domains.
The following Memory Types are available:
− Flip-Flops—Store the data with standard flip-flops. This option stores the data using gates
on the FPGA and provides the fastest performance. National Instruments recommends using
this option for small FIFOs, up to 100 bytes.
− Look-up Table—Stores the data in lookup tables available on the FPGA. The FPGA
includes two lookup tables per slice. NI recommends using this option for FIFOs smaller
than
300 bytes.
− Block Memory—Stores the data using embedded blocks of memory. Use this option for
FIFOs larger than 300 bytes. You should block memory (block memory of 80 kB on a 1M
gate FPGA or 192 kB on a 3 M) rather than flip-flops or lookup tables to preserve FPGA
space for your VI.
If you select the Block Memory option, you might not be able to read data in a Target-Scoped
FIFO or VI-Scoped FIFO until up to six clock cycles after you write the data to the FIFO. Use the
Timed Out? output of the FIFO Read or FIFO Write function to determine when the data is ready.

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Reading and Writing FPGA FIFOs
• Add an FPGA FIFO Write or Read
function from the Functions palette
• Right-click the function and
choose Select FIFO
− Associates function with a defined
FIFO

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Use the FIFO Write function to put data in a FIFO. Use
the FIFO Read function to retrieve the data from
another structure or subVI in the FPGA VI. The FIFO
Read function reads the oldest element in an FPGA
FIFO and removes the element from the FIFO. Access
the FIFO Read and FIFO Write functions from the
Memory & FIFO palette, or click a FIFO item in the
Project Explorer and drag it the block diagram to add a
FIFO Read or FIFO Write function to the block
diagram.

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FPGA FIFO Write Parameters

• Element—Inputs the data element to store

• Timeout—Sets number of ticks the function waits for space
if the FIFO is full. 0 (default) = no wait, –1 waits until space
is available
• Timed Out?—True if no room in the FIFO was available.
New element was not added

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The FIFO Write function has the following parameters:
Element—Inputs the data element you want to store in the FIFO.
Timeout—Inputs the number of clock ticks the function waits for
available space in the FIFO if the FIFO is full. The default is 0, or
no wait. A value of –1 prevents the function from timing out.
Wire a constant of zero to Timeout if you use the FIFO Write
function in a single-cycle Timed Loop.
Timed Out?—Returns TRUE if space in the FIFO is not available
before the function completes execution. If Timed Out? is TRUE,
the function does not add Element to the FIFO.
NoteData in the FIFO will not be overwritten; rather, new
data is not added to the FIFO until space is
available.

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Clearing FPGA FIFOs
Clear Method
• FIFOs retain data if the FPGA is
stopped and restarted.
• Use the Clear Method to empty a target- or VI-scoped FIFO
− Or call Reset VI method from the host.

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When you run the FPGA VI with an FPGA target
emulator, FIFOs reset when the VI stops and restarts.
When you run the FPGA VI on an FPGA target using
Interactive Front Panel Communication, FPGA FIFOs
do not reset when the FPGA VI stops and restarts. To
prevent old data from interfering with current operations
make sure to use the Clear Method or Reset VI Method
to clear old or unwanted data from the FIFO.

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 Exercise 5-2: Dataflow in Parallel Loops
Using a FIFO VI

Create parallel loops on the FPGA that pass data using the
GOAL

FPGA FIFO.

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Quiz

1. It is always best to use 2. What is a potential

the Loop Timer function. drawback of using an 8-
a. True bit counter instead of a
b. False 32-bit counter?
a. Decreased FPGA
resources used
b. 32-bit clocks are slower
c. Low terminal count could
lead to rollover

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Quiz

3. The best way to pass 4. You can create FPGA

large amounts of data FIFOs from which of the
between loops is by following:
using: a. LabVIEW Project
a. Shared Variables b. Host VI
b. FPGA FIFOs c. FPGA VI
c. Semaphores d. Notepad
d. Local Variables

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1.False
2.Low terminal count could lead to rollover
3.FPGA FIFOs
4.LabVIEW Project and FPGA VI

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