Documentos de Académico
Documentos de Profesional
Documentos de Cultura
TPA2005D1
SLOS369G – JULY 2002 – REVISED OCTOBER 2015
– Improved CMRR Eliminates Two Input (1) For all available packages, see the orderable addendum at
Coupling Capacitors the end of the datasheet.
2 Applications 6 mm
Ideal for Wireless or Cellular Handsets and PDAs
Application Circuit
To Battery
Internal VDD
Oscillator CS
RI
+ IN–
VO+
_
Differential H–
PWM
Input + Bridge VO–
RI
– IN+
GND
Bias
SHUTDOWN Circuitry
TPA2005D1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TPA2005D1
SLOS369G – JULY 2002 – REVISED OCTOBER 2015 www.ti.com
Table of Contents
1 Features .................................................................. 1 9.2 Functional Block Diagram ....................................... 12
2 Applications ........................................................... 1 9.3 Feature Description................................................. 12
3 Description ............................................................. 1 9.4 Device Functional Modes........................................ 16
4 Revision History..................................................... 2 10 Application and Implementation........................ 20
10.1 Application Information.......................................... 20
5 Device Comparison Table..................................... 3
10.2 Typical Applications ............................................. 20
6 Pin Configuration and Functions ......................... 3
11 Power Supply Recommendations ..................... 24
7 Specifications......................................................... 4
11.1 Power Supply Decoupling Capacitors................... 24
7.1 Absolute Maximum Ratings ...................................... 4
7.2 ESD Ratings ............................................................ 4 12 Layout................................................................... 25
12.1 Layout Guidelines ................................................. 25
7.3 Recommended Operating Conditions....................... 4
12.2 Layout Examples................................................... 26
7.4 Thermal Information .................................................. 4
7.5 Electrical Characteristics........................................... 5 13 Device and Documentation Support ................. 28
7.6 Operating Characteristics.......................................... 5 13.1 Community Resources.......................................... 28
7.7 Typical Characteristics .............................................. 6 13.2 Trademarks ........................................................... 28
13.3 Electrostatic Discharge Caution ............................ 28
8 Parameter Measurement Information ................ 11
13.4 Glossary ................................................................ 28
9 Detailed Description ............................................ 12
9.1 Overview ................................................................. 12 14 Mechanical, Packaging, and Orderable
Information ........................................................... 29
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
• Added ESD Rating table, Feature Description section, Device Functional Modes, Application and Implementation
section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and
Mechanical, Packaging, and Orderable Information section. ................................................................................................ 1
A. The shaded terminals are used for electrical and thermal connections to the ground plane. All the shaded terminals
need to be electrically connected to ground. No connect (NC) terminals still need a pad and trace.
B. The thermal pad of the DRB and DGN packages must be electrically and thermally connected to a ground plane.
Pin Functions
PIN
I/O DESCRIPTION
NAME GQY, ZQY DRB, DGN
A2, A3, B3, C2, C3,
GND 7 I High-current ground
D2, D3
IN- D1 4 I Negative differential input
IN+ C1 3 I Positive differential input
NC B1 2 No internal connection
SHUTDOWN A1 1 I Shutdown terminal (active low logic)
Thermal Pad Must be soldered to a grounded pad on the PCB.
VDD B4, C4 6 I Power supply
VO- A4 8 O Negative BTL output
VO+ D4 5 O Positive BTL output
7 Specifications
7.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
MIN MAX UNIT
In active mode –0.3 6 V
VDD Supply voltage (2)
In SHUTDOWN mode –0.3 7 V
VI Input voltage –0.3 VDD + 0.3 V V
TA Operating free-air temperature –40 85 °C
TJ Operating junction temperature –40 85 °C
Tstg Storage temperature –65 150 °C
2.5 ≤ VDD ≤ 4.2 V 3.2 (Minimum) Ω
RL Load resistance
4.2 < VDD ≤ 6 V 6.4 (Minimum) Ω
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) For the MSOP (DGN) package option, the maximum VDD should be limited to 5 V if short-circuit protection is desired.
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
100 90
RL = 32 W, 33 mH
90 80 VDD = 5 V,
80 RL = 8W, 33mH
RL = 8 W, 33 mH 70 VDD = 2.5 V,
70
RL = 16 W, 33 mH 60 RL = 8W, 33mH
Efficiency - %
60
Efficiency - %
50
50
40
40 Class-AB,
30 VDD = 5 V,
30 Class-AB,
RL = 8 Ω RL = 8 W
20 20
10 10
VDD = 3.6
0 0
0 0.1 0.2 0.3 0.4 0.5 0.6 0 0.2 0.4 0.6 0.8 1 1.2
PO - Output Power - W PO - Output Power - W
PD - Power Dissipation - W
0.5 RL = 4 W, 33 mH
60 RL = 4 W, 33 mH VDD = 3.6 V,
Efficiency - %
RL = 8 W
50 0.4
40 0.3
VDD = 3.6 V,
30
0.2 RL = 8 W, 33 mH
20
0.1
10 VDD = 5 V,
RL = 8 W, 33 mH
0 0
0 0.5 1 1.5 0 0.2 0.4 0.6 0.8 1 1.2
PO - Output Power - W PO - Output Power - W
RL = 8 W, 33 mH 200
150
150 VDD = 5 V,
RL = 8 W, 33 mH
100
100
VDD = 3.6 V,
50 RL = 8 W, 33 mH
50
VDD = 2.5 V,
RL = 32 W, 33 mH RL = 8 W, 33 mH
0 0
0 0.1 0.2 0.3 0.4 0.5 0.6 0 0.2 0.4 0.6 0.8 1 1.2
PO - Output Power - W PO - Output Power - W
Figure 5. Supply Current vs Output Power Figure 6. Supply Current vs Output Power
2 0
2.5 3 3.5 4 4.5 5 5.5 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8
VDD − Supply Voltage − V Shutdown Voltage - V
Figure 7. Quiescent Current vs Supply Voltage Figure 8. Shutdown Current vs Shutdown Voltage
1.6 1.6
RL = 8 W RL = 4 W,
1.4 f = 1 kHz 1.4 f = 1kHz,
Gain = 2 V/V Gain = 2 V/V
1.2 1.2
PO - Output Power - W
PO - Output Power - W
1 THD+N = 10%
THD+N = 10% 1
0.8 0.8
THD+N = 1%
0.6 0.6
THD+N = 1%
0.4 0.4
0.2 0.2
0
0
2.5 3 3.5 4 4.5 5
2.5 3 3.5 4 4.5
VDD - Supply Voltage - V
VDD - Supply Voltage - V
Figure 9. Output Power vs Supply Voltage Figure 10. Output Power vs Supply Voltage
1.4 1.8
f = 1 kHz, f = 1 kHz,
THD+N = 1%, 1.6 THD+N = 10%,
1.2
Gain = 2 V/V Gain = 2 V/V
1.4
PO - Output Power - W
1
PO - Output Power - W
0.6
0.4
0.4
0.2
0.2
VDD = 2.5 V VDD = 2.5 V
0 0
4 8 12 16 20 24 28 32 4 8 12 16 20 24 28 32
RL - Load Resistance - W RL - Load Resistance - W
Figure 11. Output Power vs Load Resistance Figure 12. Output Power vs Load Resistance
1 1 3.6 V
0.5 5V
0.5
0.2 0.2
0.1 0.1
0.01 0.1 1 2 0.01 0.1 1 2
Figure 13. Total Harmonic Distortion + Noise vs Output Figure 14. Total Harmonic Distortion + Noise vs Output
Power Power
30
RL = 16 W, VDD = 5 V
20 5
f = 1 kHz, CI = 2 mF
10 Gain = 2 V/V RL = 8 W
2
Gain = 2 V/V
5 1
0.5
2 2.5 V
0.2
3.6 V 50 mW
1
0.1 1W
0.5 5V 0.05
0.1 0.008
0.01 0.1 1 2 20 100 1k 20 k
PO − Output Power − W f − Frequency − Hz
Figure 15. Total Harmonic Distortion + Noise vs Output Figure 16. Total Harmonic Distortion + Noise vs Frequency
Power
THD+N − Total Harmonic Distortion + Noise − %
THD+N − Total Harmonic Distortion + Noise − %
10
VDD = 3.6 V 10
VDD = 2.5 V
5 CI = 2 mF 5 CI = 2 mF
RL = 8 W RL = 8 W
2 15 mW
Gain = 2 V/V 2 Gain = 2 V/V
1
1 75 mW
0.5
0.5
0.2
500 mW 0.2
0.1 25 mW
0.1 200 mW
0.05 0.05
125 mW
0.02
0.02
0.01 0.01
20 100 1k 20 k 20 100 1k 20 k
f − Frequency − Hz f − Frequency − Hz
Figure 17. Total Harmonic Distortion + Noise vs Frequency Figure 18. Total Harmonic Distortion + Noise vs Frequency
0.02 0.02
200 mW
0.01 0.01
20 100 1k 20 k 20 100 1k 20k
f − Frequency − Hz f - Frequency - Hz
Figure 19. Total Harmonic Distortion + Noise vs Frequency Figure 20. Total Harmonic Distortion + Noise vs Frequency
10 10
5 VDD = 3.6 V, VDD = 2.5 V,
5
R L = 4 W, RL = 4 W,
2 Gain = 2V/V 75 mW
Gain = 2V/V 2
15 mW
1 1
250 mW
0.5 0.5
775 mW
0.2 500 mW 0.2 200 mW
0.1 0.1
0.05
0.05
0.02 0.02
0.01 0.01
20 100 1k 20k 20 100 1k 20k
f-Frequency-Hz f - Frequency - Hz
Figure 21. Total Harmonic Distortion + Noise vs Frequency Figure 22. Total Harmonic Distortion + Noise vs Frequency
10
THD+N - Total Harmonic Distortion + Noise - %
0
− Supply Voltage Rejection Ratio − dB
f = 1 kHz CI = 2 mF
PO = 200 mW −10 RL = 8 W
Vp-p = 200 mV
−20 Inputs ac-Grounded
Gain = 2 V/V
−30
−70
VDD = 3.6 V
SVR
VDD = 5 V
0.1 −80
k
Figure 23. Total Harmonic Distortion + Noise vs Figure 24. Supply Voltage Rejection Ratio vs Frequency
Common Mode Input Voltage
SVR
SVR
k
−100
20 100 1k 20 k 20 100 1k 20 k
f − Frequency − Hz f − Frequency − Hz
Figure 25. Supply Voltage Rejection Ratio vs Frequency 25 Figure 26. Supply Voltage Rejection Ratio vs Frequency
f = 217 Hz
-10
RL = 8 W
-50
-20 Gain = 2 V/V
-30 -100
-40
VDD = 5 V
-90 -150
k
0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 0 400 800 1200 1600 2000
VIC - Common Mode Input Voltage - V f - Frequency - Hz
Figure 27. Supply Voltage Rejection Ratio vs Figure 28. GSM Power Supply Rejection vs Time
Common-mode Input Voltage
0
V DD - Supply Voltage - dBV
0
CMRR − Common Mode Rejection Ratio − dB
VDD = 2.5 V to 5 V
-50 −10 VIC = 1 Vp−p
RL = 8 W
−20 Gain = 2 V/V
-100
−30
VO - Output Voltage - dBV
-100
−60
-150 −70
0 400 800 1200 1600 2000 20 100 1k 20 k
f - Frequency - Hz f − Frequency − Hz
Figure 29. GSM Power Supply Rejection vs Frequency Figure 30. Common-mode Rejection Ratio vs Frequency
-30
-40
VDD = 2.5 V VDD = 3.6 V
-50
-60
-70
-80 VDD = 5 V
-90
-100
0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5
VIC - Common Mode Input Voltage - V
VDD GND
1 mF
+
VDD
±
9 Detailed Description
9.1 Overview
The TPA2005D1 is a high-efficiency filter-free Class-D audio amplifier capable of delivering up to 1.4 W into 8-Ω
loads with 5-V power supply. The fully-differential design of this amplifier avoids the usage of bypass capacitors
and the improved CMRR eliminates the usage of input-coupling capacitors. This makes the device size a perfect
choice for small, portable applications as only three external components are required.
The advanced modulation used in the TPA2005D1 PWM output stage eliminates the need for an output filter.
IN+ C1 D4
150 kW + Deglitch Gate VO+
_ Logic Drive
A1 TTL
SHUTDOWN SD Input Startup Short
Buffer Biases & Thermal Circuit †
Ramp Protection GND
and Detect
Generator Logic
References
OUT+
OUT–
+5 V
Differential Voltage
0V
Across Load
–5 V
Current
Figure 33. Traditional Class-D Modulation Scheme's Output Voltage and Current Waveforms Into an
Inductive Load With no Input
OUT+
OUT–
Output = 0 V
Differential +5 V
Voltage
0V
Across
Load –5 V
Current
OUT+
Differential +5 V
Voltage
0V
Across
–5 V
Load
Current
Figure 34. The TPA2005D1 Output Voltage and Current Waveforms Into an Inductive Load
P
SPKR
+P 1 ǒ* 1
OUT h MEASURED h THEORETICAL
Ǔ
(at max output power)
(5)
R
hTHEORETICAL + L (at max output power)
R ) 2r
L DS(on) (6)
The maximum efficiency of the TPA2005D1 with a 3.6 V supply and an 8-Ω load is 86% from equation
Equation 6. Using equation Equation 5 with the efficiency at maximum power (84%), we see that there is an
additional 17 mW dissipated in the speaker. The added power dissipated in the speaker is not an issue as long
as it is taken into account when choosing the speaker.
Ferrite
Chip Bead
OUTP
1 nF
Ferrite
Chip Bead
OUTN
1 nF
Figure 35. Typical Ferrite Chip Bead Filter (Chip bead example: NEC/Tokin: N2012ZPS121)
33 µH
OUTP
1 µF
33 µH
OUTN
1 µF
RI1
+
Differential
Input 1 RI1 To Battery
– Internal VDD
Oscillator CS
RI2
+ IN–
VO+
_ PWM H–
Differential Bridge
Input 2 + VO–
RI2
– IN+
GND
Bias
SHUTDOWN Circuitry
Filter-Free Class D
Figure 37. Application Schematic With TPA2005D1 Summing Two Differential Inputs
RI1
Differential
RI1 To Battery
Input 1 Internal VDD
Oscillator CS
CI2 R
Single-Ended I2
IN–
Input 2 VO+
_ PWM H–
Bridge
+ VO–
RI2
IN+
CI2
GND
Bias
SHUTDOWN Circuitry
Filter-Free Class D
Figure 38. Application Schematic With TPA2005D1 Summing Differential Input and
Single-Ended Input Signals
CI1 R
I1
Single-Ended
Input 1 To Battery
Internal VDD
Oscillator CS
CI2 R
Single-Ended I2
IN–
Input 2 VO+
_ PWM H–
Bridge
+ VO–
RP
IN+
CP
GND
Bias
SHUTDOWN Circuitry
Filter-Free Class D
Figure 39. Application Schematic With TPA2005D1 Summing Two Single-Ended Inputs
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
To Battery
Internal VDD
Oscillator CS
RI
+ IN–
VO+
_ PWM H–
Differential Bridge
Input + VO–
RI
– IN+
GND
Bias
SHUTDOWN Circuitry TPA2005D1
Filter-Free Class D
(1) CI is only needed for single-ended input or if VICM is not between 0.5 V and VDD - 0.8 V. CI = 3.3 nF (with RI = 150 kΩ) gives a high-
pass corner frequency of 321 Hz.
PO - Output Power - W
1 THD+N = 10%
0.8
0.6
THD+N = 1%
0.4
0.2
0
2.5 3 3.5 4 4.5 5
VDD - Supply Voltage - V
To Battery
Internal VDD
Oscillator CS
CI RI
IN–
VO+
_ PWM H–
Differential Bridge
Input CI + VO–
RI
IN+
GND
Bias
SHUTDOWN Circuitry TPA2005D1
Filter-Free Class D
To Battery
Internal VDD
Oscillator CS
CI RI
Single-ended IN–
Input VO+
_ PWM H–
Bridge
+ VO–
RI
IN+
CI
GND
Bias
SHUTDOWN Circuitry TPA2005D1
Filter-Free Class D
12 Layout
0,28
SD GND GND Vo−
mm
0,38
mm NC GND VDD
Figure 44. TPA2005D1 MicroStar Junior BGA Board Layout (Top View)
OUT -
Decoupling capacitor
placed as close as
SHUTDOWN A1 A2 A3 A4 possible to the device
B1 B3 B4
IN + C1 C2 C3 C4
0.1µF
IN - D1 D2 D3 D4
TPA2005D1
OUT +
Input Resistors
placed as close as
possible to the device
Decoupling capacitor
placed as close as
possible to the device
SHUTDOWN 1 8 OUT -
2 7
0.1µF
IN + 3 6
IN - 4 5 OUT +
TPA2005D1
Input Resistors
placed as close as
possible to the device
Decoupling capacitor
placed as close as
possible to the device
SHUTDOWN 1 8 OUT -
2 7
0.1µF
IN + 3 6
IN - 4 5 OUT +
TPA2005D1
Input Resistors
placed as close as
possible to the device
13.2 Trademarks
MicroStar Junior, PowerPAD, E2E are trademarks of Texas Instruments.
is a trademark of ~ Texas Instruments Incorporated.
All other trademarks are the property of their respective owners.
13.3 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
13.4 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
www.ti.com 24-Sep-2015
PACKAGING INFORMATION
Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples
(1) Drawing Qty (2) (6) (3) (4/5)
TPA2005D1DGN ACTIVE MSOP- DGN 8 80 Green (RoHS CU NIPDAUAG Level-1-260C-UNLIM -40 to 85 BAL
PowerPAD & no Sb/Br)
TPA2005D1DGNG4 ACTIVE MSOP- DGN 8 80 Green (RoHS CU NIPDAUAG Level-1-260C-UNLIM -40 to 85 BAL
PowerPAD & no Sb/Br)
TPA2005D1DGNR ACTIVE MSOP- DGN 8 2500 Green (RoHS CU NIPDAUAG Level-1-260C-UNLIM -40 to 85 BAL
PowerPAD & no Sb/Br)
TPA2005D1DGNRG4 ACTIVE MSOP- DGN 8 2500 Green (RoHS CU NIPDAUAG Level-1-260C-UNLIM -40 to 85 BAL
PowerPAD & no Sb/Br)
TPA2005D1DRBR ACTIVE SON DRB 8 3000 Green (RoHS CU NIPDAU Level-2-260C-1 YEAR -40 to 85 BIQ
& no Sb/Br)
TPA2005D1DRBRG4 ACTIVE SON DRB 8 3000 Green (RoHS CU NIPDAU Level-2-260C-1 YEAR -40 to 85 BIQ
& no Sb/Br)
TPA2005D1GQYR ACTIVE BGA GQY 15 2500 TBD SNPB Level-2-235C-1 YEAR -40 to 85 PB051
MICROSTAR
JUNIOR
TPA2005D1ZQYR ACTIVE BGA ZQY 15 2500 Green (RoHS SNAGCU Level-2-260C-1 YEAR -40 to 85 AAFI
MICROSTAR & no Sb/Br)
JUNIOR
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com 24-Sep-2015
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
• Automotive: TPA2005D1-Q1
• Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com 22-Jun-2015
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com 22-Jun-2015
Pack Materials-Page 2
MECHANICAL DATA
1,50 TYP
2,60 0,50
SQ
2,40
0,25
D
0,50
C
1,50 TYP
B
0,25
A
1 2 3 4
A1 Corner
Bottom View
0,77
0,71 1,00 MAX
Seating Plane
0,35
0,08
0,25 0,25
0,05 M 0,15
4201436/D 01/02
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