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INDEX

CONTENTS Page No

List Of Figures I

List Of Tables III

Abstract IV

CHATER 1 1

INTRODUCTION 2

CHAPTER 2 5

LITERATURE SURVEY 6
2.1 Integer Multiplication And Division on the HP Precision Architecture 6

2.2 Multiplication by Integer Constants 6

2.3 Some Optimizations of Hardware Multiplications by Constant Matrices 6

2.4 Multiple Constant Multiplications: Efficient and Versatile Framework and

Algorithms for Exploring Common Sub expression Elimination 6

2.5 Sub expression Sharing in Filters Using Canonic Signed Digit Multipliers 7

2.6 Existing System 8

2.6.1 NR4SD¯ Encoding Architecture 8

2.6.2 NR4SD+ Encoding Architecture 10

CHAPTER 3 13

PROPOSED SYSTEM 14

3.1 DADDA Multiplier 14

3.2 Pre – Encoded Multipliers Design Using DADDA Multiplier 15


CHAPTER 4 17

HARDWARE REQUIREMENTS 18

4.1 General 18

4.2 Applications Of VLSI 18

4.3 Advantages Of VLSI 19

4.4 VLSI And Systems 20

4.5 Integrated Circuit Manufacturing 20

4.5.1 Mask – Driven Manufacturing 21

4.6 Circuits And Layouts 21

4.7 Manufacturing Defects 22

4.8 Economics 22

4.9 Cost Of Manufacturing 23

4.10 Cost of Design 24

4.11 Types Of Chips 24

4.12 CMOS Technology 26

4.12.1 Power Consumption 26

4.12.2 Design And Testability 27

4.12.3 Testability As A Design Process 28

4.12.4 Reliability 29

4.12.5 Design For Manufacturability 29

4.12.6 Integrated Circuit Design Techniques 30

4.13 Field – Programmable Gate Arrays(FPGA) 31

4.13.1 Lookup Tables 32

4.13.2 Programming A Lookup Table 32

4.13.3 Complex Logic Element 33


4.13.4 Programmable Interconnection Points 33

CHAPTER 5 34

TOOLS 35

5.1 Introduction 35

5.2 Hardware Requirements 35

5.3 Software Requirements 35

5.4 Introduction to FPGA 65

5.5 Interconnects 68

5.6 FPGA Design Flow 68

5.7 Design Entry 69

5.8 Synthesis 69

5.9 Implementation 69

5.9.1 Translate 69

5.9.2 Map 70

5.9.3 Place and Route 70

5.10 Device Programming 71

5.10.1 Design Verification 71

5.10.2 Behavioral Verification (RTL Simulation) 71

5.10.3 Functional Simulation (Post Translate Simulation) 72

CHAPTER 6 73

RESULTS 74

CHAPTER 7 77

CONCLUSION AND FUTURE SCOPE 78

7.1 CONCLUSION 78

7.2 FUTURE SCOPE 78


CHAPTER 8 79

REFERENCES 80
LIST OF FIGURES
Fig No Figure Name Page No
Fig 2.1 Block Diagram of the NR4SD¯ Encoding Scheme at the
(a) Digit and (b) Word Level. 8
Fig 2.2. Block Diagram of the NR4SD+ Encoding Scheme at the
(a)Digit and (b) Word Level. 10
Fig 3.1 System Architecture of the Pre Encoding Multipliers
design Using DADDA Multiplier. 15
Fig 4.1 Lookup Tables 31

Fig 4.2 Programming A Lookup Table 32

Fig 4.3 Programming A Lookup Table 33

Fig 5.1 Project Navigator 36

Fig 5.2 Project Navigator Desktop Icon 44

Fig 5.3 Completed Stopwatch Schematic 46

Fig 5.4 Incomplete Stopwatch Schematic 50

Fig 5.5 New Source Dialog Box 51

Fig 5.6 Create I/O Markers Dialog Box 52

Fig 5.7 Add Symbol Toolbar Button 53

Fig 5.8 Symbol Browser 54

Fig 5.9 Partially Completed time_cnt Schematic 55

Fig 5.10 Add Wire Toolbar Button 56

Fig 5.11 Adding VHDL Test Bench 61

Fig 5.12 Adding Verilog Test Fixture 62

Fig 5.13 Behavioral Simulation Process Properties 64

Fig 5.14 Internal structure of FPGA 66

Fig 5.15 4-input LUT based implementation of logic block 67


Fig 5.16 FPGA Design Flow 68

Fig 5.17 FPGA Synthesis 69

Fig 5.18 FPGA Translate 70


Fig 5.19 FPGA map 70
Fig 5.20 FPGA Place and route 71
LIST OF TABLES
Table no Table Name Page No.
Table 1 NR4SD¯ Encoding 10
Table 2 NR4SD+ Encoding 12
ABSTRACT
The most effective way to increase the speed of a multiplier is to reduce the number of
the partial products because multiplication precedes a series of additions for the partial products.
To reduce the number of calculation steps for the partial products NR4SD encoding is
used mostly where CSA has taken the role of increasing the speed to add the partial products. In
this NR4SDˉ and NR4SD+ are used to reduce no of partial products. To further implement the
Performance of the multiplier we are using the DADDA multiplier. We are adapting the Dadda
multiplier for both NR4SD¯ and NR4SD+ multipliers so that the delay of the partial product
generation and addition of partial products is reduced.
The experimental results have shown that the proposed multiplier outperforms the
conventional multiplier in terms of power and speed of operation. In this paper we used Xilinx-
ISE tool for logical verification, synthesis and Simulation.

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