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A B C D E

COMPAL CONFIDENTIAL
MODEL NAME : HAL00
1 1

PCB NO : LA-2791
COMPAL P/N : 45135631L01

Travis (UMA) Schematics Document 2

uFCPGA Mobile Yonah


Intel Calistoga + ICH7M

2006-01-20
3
REV : 1.0 (DELL: A00) 3

4 4

DELL CONFIDENTIAL/PROPRIETARY
MB PCB
Part Number Description
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL Title
DAA0000040L PCB ZJX LA-2791 BOM NO. 45135631L01 TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, Cover Sheet
REV0 M/B UMA
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD Size Document Number Rev
PCB P/N: DA800002L1L PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
LA-2791 0.6

Date: Tuesday, February 07, 2006 Sheet 1 of 63


A B C D E
A B C D E

Compal confidential
Block Diagram
Model : HAL00

FAN Thermal Pentium-M


FAN1_VOUT GUARDIAN II Yonah-2M
page 18
1 EMC4000 uFCPGA CPU CPU ITP Port Clock Generator 1
+3.3V_SUS page 18 +1.05V_VCCP (1.05V) SLG84450VTR
+VCC_CORE 478pin page 7,8,9 +1.05V_VCCP page 7 +3.3V_RUN page6

H_A#(3..31) H_D#(0..63)
System Bus
FSB 533/667 MHz
RGB CRT CONN
+5V_RUN page 20 RGB INTEL Memory BUS DDRII-DIMM X2
BANK 0, 1, 2, 3, 4 ,5 ,6 ,7 ,8
LVDS CONN Calistoga (DDR2) +1.8V_SUS 533 / 667MHz
page 16,17
on M/B Board page 19 LVDS +1.5V_RUN
+0.9V_DDR_VTT
+1.8V_SUS
DVI DVI Bridge DVO 1466pin BGA +1.8V_SUS
+1.05V_VCCP (1.05V)
SI1362 page 19
+3.3V_RUN
TV +2.5V_RUN Smart Card
page 10,11,12,13,14,15
HUB USB[3]
OZ77C6 SLOT
+3.3V_RUN page 31

2 DMI USB[5,6] REAR USB Ports X2 USB4 on right side of 2

+1.5V_RUN connector, USB6 on left side


PCI BUS +3.3V_RUN 33MHz 100MHz +5V_SUS page 32

48MHz USB[3,4] SIDE USB Ports X2


DOCKING DOCKING CardBus IDSEL:AD17 INTEL +5V_SUS IO/B
PORT BUFFER OZ601 TQFP (PIRQC,D#,GNT#1,REQ#1)
ICH7-M
+3.3V_RUN
PAGE 36 +5VRUN PAGE 35 +3VRUN page 30 Azalia I/F USB0 on the top of connector,
+3.3V_SUS
USB[7] HUB USB[1] 652pin BGA ATA100 USB2 on the bottom
+1.5V_RUN
+3.3V_RUN/ +1.5V_RUN 100MHz PCI Express BUS
+1.05V_VCCP
page 21,22,23,24 SATA

SPI
+3VRUN USB[2]
Mini Card2 Mini Card 1 GIGA Enthernet 33MHz LPC BUS M DC
WLAN WWAN BCM5752 USB[1] +3.3V_SUS
+3.3V_RUN +3.3V_RUN +3VLAN page 33
+1.5VRUN page 34 +1.5VRUN page 34 page 28,29
3 3
HUB USB[1] Cable
SMSC SIO Azalia Codec
USB[0] HUB USB[2] S-HDD D Moudle
HUB USB[4] ECE5018 HUB USB[2] STAC9200
RJ45 +3.3V_RUN
RJ11
IO/B HUB USB[3] +5VHDD +5VMOD
+3VALW page 38 page 25 page 25 +VDDA page 26 IO/B

SPI
1.8V/0.9V 1.5V/1.05V Bluetooth
+3.3V_RUN page 33
MEC5004
+RTC_CELL
page 48 page 47
Power Sequence
+3.3V_ALW page 39
AMP & INT. INT MIC HeadPhone &
page 42
VCORE (IMVP-6) DC IN Speaker +5V_SUS MIC Jack
page 49 page 44 COM +5V_SUS page 27 +3.3V_RUNpage 27
page 37
Power On/Off Int.KBD & ST M25P80
+3.3V_ALW page 39
CHARGER BATT IN SW & LED Stick page 40
page 43
4
page 50 page 45 FIR 4

+3.3V_RUN page 37
Stick Touch Pad
BATT SELECT 3V/5V/15V DC/DC Interface DELL CONFIDENTIAL/PROPRIETARY
+5V_RUN page 33
page 51 page 46 page 41 Compal Electronics, Inc.
Title
Block Diagram
Size Document Number Rev
0.6
LA-2791
Date: Tuesday, February 07, 2006 Sheet 2 of 63
A B C D E
5 4 3 2 1

PCI TABLE
Ceramic Capacitors :
PCI DEVICE IDSEL REQ#/GNT# PIRQ
0.1U_0402_6.3VXX
Tolerance CARD BUS AD17 1 C
D D

Temperature Characteristics
Rated Voltage
Package Size
Value
PM TABLE
+5V_RUN
+3.3V_SRC +3.3V_RUN

Tantalum or Polymer Capacitors : power +5V_ALW


+15V_SUS
+5V_SUS
+3.3V_RUN_R
+1.8V_RUN
plane
+3.3V_ALW +3.3V_SUS +0.9V_DDR_VTT

10U_D2_10VX_R45 +1.8V_SUS +1.5V_RUN


+VCC_CORE
State
+1.05V_VCCP
C
Low ESR Mark : 45 m ohm +2.5V_RUN
C

Tolerance S0 ON ON ON

Rated Voltage S1 ON ON ON

Package Size S3 ON ON OFF

Value S5 S4/AC ON OFF OFF

S5 S4/AC don't exist OFF OFF OFF

Capacitor Spec Guide:


USB TABLE
Temperature Characteristics:
B
Symbol 0 1 2 3 4 5 6 7 USB PORT# DESTINATION USB HUB DESTINATION B

CODE Z5U Z5V Z5P Y5U Y5V Y5P X5R X7R

0 Mini 2(WLAN) 1 PC Card Bay


8 9 A B C D E F G

NPO COG X6S BJ CH CJ CK SH SJ


1 USB Hub (5018) 2 Mini 1(WWAN)
H I J K
2 D Moudle 3 Smart Card --> BIO
UJ UK SL X5S

3,4 SIDE 4 Blue tooth


Tolerance:
Symbol A B C D F G H J
5,6 REAR
CODE +-0.05PF +-0.1PF +-0.25PF +-0.5PF +-1PF +-2% +-3% +-5%

A K M N P Q V X Z 7 Docking A

+-10% +-20% +-30% +100,-0% +30,-10% +20,-10% +40,-20% +80,-20% NOTE1:


@XX : Depop component DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL Title
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, Index and Config.
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD Size Document Number Rev
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. 0.6
LA-2791
Date: Tuesday, February 07, 2006 Sheet 3 of 63
5 4 3 2 1
5 4 3 2 1

D D

ADAPTER
RUN_ON
+PWR_SRC FDS4435 +INV_PWR_SRC

BATTERY

ALWON
+5V_ALW
MAX8734 ALWON
ISL6260 ISL6227 MAX88550
C C

+3.3V_ALW

SUSPWROK_5V

RUN_ON
RUNPWROK
SUS_ON

SUS_ON

RUNPWROK

RUNPWROK
+5V_SUS +3.3V_SRC +VCC_CORE +1.5V_RUN +1.05V_VCCP +1.8V_SUS +0.9V_DDR_VTT
AUDIO_AVDD_ON
HDDC_EN#

ENAB_3VLAN
RUN_ON

RUN_ON

RUN_ON
B B

RUN_ON
(Option)

SI3456 SI3456 793475 PL8 SI4800 SI3456 SI4800 SI4800 SI3456


MODC_EN#

+VDDA +15V_SUS
+5V_SATA +5V_RUN +3.3V_RUN +3VLAN +3.3V_SUS +3.3V_RUN_R +1.8V_RUN

SI3456
L47
EMC4000
MOD
(+5VRUN)
A A

DELL CONFIDENTIAL/PROPRIETARY
+2.5V_RUN
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL Title
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, Power Rail
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD Size Document Number Rev
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. 0.6
LA-2791
Date: Tuesday, February 07, 2006 Sheet 4 of 63
5 4 3 2 1
5 4 3 2 1

+3.3V_SUS +3.3V_RUN

2.2K 2.2K 2.2K 2.2K

+3.3V_SUS
C22 ICH_SMBCLK CLK_SCLK 16
2N7002
D D

ICH7-M ICH_SMBDATA CLK GEN.


B22 CLK_SDATA 17
2N7002
32 30 C7 C8 32 30
SMBUS Address [D2]
+3.3V_ALW 5752M
WWAN WLAN 197
LOM
SMBUS Address [TBD] SMBUS Address [C8] SMBUS Address [TBD]
DIMM0
10K 10K
195
6 CLK_SMB 8 SMBUS Address [A0]

DAT_SMB +3.3V_ALW GUARDIAN 197


5 7 SMBUS Address [2F]
DIMM1
195
+3.3V_ALW
SMBUS Address [A2]
C C
8.2K 8.2K

10 DOCK_SMB_CLK 39

DOCK_SMB_DAT +3.3V_ALW DOCKING SMBUS Address [C4, 72, 70, 48]


9 40

SIO +3.3V_ALW
100
3
2'nd
4.7K 4.7K SMBUS Address [16]
4 BATTERY
SBAT_SMBCLK 100
112 6

Macallan IV SBAT_SMBDAT +3.3V_ALW INV Inverter


111 5
SMBUS Address [58]
B B

+3.3V_ALW

8.2K 8.2K

PBAT_SMBCLK 100
8 3
BATTERY
PBAT_SMBDAT +3.3V_ALW SMBUS Address [16]
7 4 CONN
100

9
10 CHARGER SMBUS Address [12]
A A

DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL Title
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, SMBUS TOPOLOGY
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD Size Document Number Rev
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. 0.6
LA-2791
Date: Tuesday, February 07, 2006 Sheet 5 of 63
5 4 3 2 1
5 4 3 2 1

+3.3V_RUN +CK_VDD_MAIN CLK_CPU_ITP 2 1


D R369 49.9_0402_1%~D
+3.3V_RUN +CK_VDD_MAIN CLK_CPU_ITP#
1 2 2 1

2.2K_0402_5%~D

2.2K_0402_5%~D
1 L40 1 1 1 1 1 1 R377 49.9_0402_1%~D

1
1 BLM21PG600SN1D_0805~D CLK_MCH_BCLK 2 1
G 2 3 S C326 C402 C384 C58 C64 C389 C70 R349 49.9_0402_1%~D

R270

R275
10U_0805_10V4Z~D 0.1U_0402_16V4Z~D 0.1U_0402_16V4Z~D 0.1U_0402_16V4Z~D 0.1U_0402_16V4Z~D 0.1U_0402_16V4Z~D CLK_MCH_BCLK# 2 1
0.1U_0402_16V4Z~D 2 2 2 2 2 2 R360 49.9_0402_1%~D
2 CLK_CPU_BCLK 2 1
2N7002

2
+CK_VDD_MAIN2 R322 49.9_0402_1%~D
ICH_SMBDATA CLK_SDATA CLK_CPU_BCLK# 2

S
23,28,34 ICH_SMBDATA 1 3 CLK_SDATA 16,17 1
R338 49.9_0402_1%~D
Q36 1 2 CLK_MCH_3GPLL 1 2
2N7002W-7-F_SOT323~D L32 1 1 1 R392 49.9_0402_1%~D

G
2
BLM21PG600SN1D_0805~D CLK_MCH_3GPLL# 1 2
D C308 C344 C330 R403 49.9_0402_1%~D D
+3.3V_RUN
10U_0805_10V4Z~D 0.1U_0402_16V4Z~D 0.1U_0402_16V4Z~D CLK_PCIE_SATA 1 2
2 2 2 R381 49.9_0402_1%~D

2
CLK_PCIE_SATA# 1

G
2
Place near each pin R385 49.9_0402_1%~D
ICH_SMBCLK 1 3 CLK_SCLK CLK_PCIE_ICH 1 2
23,28,34 ICH_SMBCLK CLK_SCLK 16,17 W>40 mil R365 49.9_0402_1%~D

S
Q38 R401 CLK_PCIE_ICH# 1 2

0.047U_0402_16V4Z~D
2N7002W-7-F_SOT323~D +CK_VDD_A +CK_VDD_48 +CK_VDD_REF 2.2_0603_5%~D R374 49.9_0402_1%~D

0.047U_0402_16V4Z~D
1 2 +CK_VDD_A CLK_PCIE_LOM 1 2
1 1 1 1 1
Place near CK410+

4.7U_0603_6.3V4Z~D

4.7U_0603_6.3V4Z~D

0.047U_0402_16V4Z~D
R393 49.9_0402_1%~D
CLK_PCIE_LOM# 1
FSC FSB FSA CPU SRC PCI 2

C68

C61

C50
R399 49.9_0402_1%~D
2 2 2 2 2
CLKSEL2 CLKSEL1 CLKSEL0 MHz MHz MHz DREFCLK 1 2

C51

C52
U16 R344 49.9_0402_1%~D
DREFCLK# 1 2
0 0 0 266 100 33.3 R355 49.9_0402_1%~D
1 7 DREF_SSCLK 1 2
VDDSRC VDDA R522 49.9_0402_1%~D
49 VDDSRC
0 0 1 133 100 33.3 54 8 DREF_SSCLK# 1 2
* 65
VDDSRC
VDDSRC
GNDA R523
CLK_PCIE_MINI2 1
49.9_0402_1%~D
2
0 1 0 200 100 33.3 NOTE: Place Decoupling as close as 25 H_STP_PCI# R544 49.9_0402_1%~D
PCI_SRC_STOP# H_STP_PCI# 23
30 CLK_PCIE_MINI2# 1 2
physically possilble to the VDD pins 36
VDDPCI
24 H_STP_CPU# R545 49.9_0402_1%~D
VDDPCI CPU_STOP# H_STP_CPU# 23
0 1 1 166 100 33.3 CLK_PCIE_MINI1 1 2
R274 12 R1641 49.9_0402_1%~D
C329 X2 1_0603_5%~D VDDCPU MCH_BCLK CLK_MCH_BCLK CLK_PCIE_MINI1# 1
CPUT1 11 1 2 CLK_MCH_BCLK 10 2
1 0 0 333 100 33.3 27P_0402_50V8J~D 14.31818MHz_20P_1BX14318CC1A~D 1 2 +CK_VDD_REF 18 R348 33_0402_5%~D R1642 49.9_0402_1%~D
VDDREF MCH_BCLK# CLK_MCH_BCLK#
2 1 CPUC1 10 1 2 CLK_MCH_BCLK# 10
1 2 +CK_VDD_48 40 R359 33_0402_5%~D
VDD48

1
1 0 1 100 100 33.3 R273
C 2.2_0603_5%~D CPU_BCLK CLK_CPU_BCLK C
CPUT0 14 1 2 CLK_CPU_BCLK 7
Place crystal within CLK_XTAL_IN 20 R321 33_0402_5%~D
C333 R32 X1 CPU_BCLK# 1 CLK_CPU_BCLK#
1 1 0 400 100 33.3 500 mils of CK410 13 2 CLK_CPU_BCLK# 7

2
27P_0402_50V8J~D 470_0402_5%~D CPUC0 R337 33_0402_5%~D
2 1 1 2 CLK_XTAL_OUT 19 X2 CPU_ITP CLK_CPU_ITP
1 1 1 Reserve CPUT_ITP/SRCT10 6 1 2 CLK_CPU_ITP 7
R368 33_0402_5%~D
CLK_ICH_48M 2 1 FSA 41 5 CPU_ITP# 1 2 CLK_CPU_ITP#
23 CLK_ICH_48M USB_48MHz/FSLA CPUC_ITP/SRCC10 CLK_CPU_ITP# 7
Table : ICS954305AK R298 12.1_0402_1%~D R376 33_0402_5%~D
CLK_SMC_48M 1 2 FSB 45
31 CLK_SMC_48M FSLB/TEST_MODE
R1589 12.1_0402_1%~D 3
FSC SRCT9
23 REF0/FSLC/TEST_SEL
CLK_PCI_5004 2 1 2
39 CLK_PCI_5004 SRCC9
CPU_BSEL CPU_BSEL2(FSC) CPU_BSEL1(FSB) R1619 12.1_0402_1%~D
CLK_PCI_5018 2 1 FCTSEL1 34 72
38 CLK_PCI_5018 PCICLK4/FCTSEL1 CLKREQ9#
R1438 12.1_0402_1%~D
CLK_PCI_LOM 2 1 PCI_LOM 33 70 PCIE_SATA 1 2 CLK_PCIE_SATA CLK_PCIE_SATA 22
28 CLK_PCI_LOM PCICLK3 SRCT8
133 0 0 R331 33_0402_5%~D R394 33_0402_5%~D
CLK_PCI_PCM 2 1 PCI_PCM 32 69 PCIE_SATA# 1 2 CLK_PCIE_SATA# CLK_PCIE_SATA# 22
30 CLK_PCI_PCM PCICLK2 SRCC8
R302 33_0402_5%~D R400 33_0402_5%~D
CLK_DOCKPCI_33M 2 1 DOCKPCI_33M 27 71 SATA_CLKREQ# 23
36 CLK_DOCKPCI_33M PCICLK1 CLKREQ8#
166 0 1 R294 33_0402_5%~D R292 1 2 10K_0402_5%~D +3.3V_RUN
SRCT7 66
CLK_ICH_14M 1 2 CLKREF 22
23 CLK_ICH_14M REF1
CLK_SIO_14M R266
1 2 12.1_0402_1%~D 67
38 CLK_SIO_14M SRCC7
R250 12.1_0402_1%~D
DREFCLK 1 2 DOT96 43 38
10 DREFCLK DOTT_96MHz/27MHz CLKREQ7#
R345 33_0402_5%~D
DREFCLK# 1 2 DOT96# 44 63 PCIE_ICH 1 2 CLK_PCIE_ICH
10 DREFCLK# DOTC_96MHz/27MHz(SS) SRCT6 CLK_PCIE_ICH 23
R356 33_0402_5%~D R366 33_0402_5%~D
R316 64 PCIE_ICH# 1 2 CLK_PCIE_ICH#
SRCC6 CLK_PCIE_ICH# 23
R1582 +3.3V_RUN 1 2 37 R375 33_0402_5%~D
B 33_0402_5%~D 10K_0402_5%~D ITP_EN/PCICLK_F0 B
CLKREQ6# 62 1 2 +3.3V_RUN
CLK_PCI_ICH 2 1 PCI_ICH @ R1761 10K_0402_5%~D
21 CLK_PCI_ICH
49 CLK_ENABLE# CLK_ENABLE# 39 60 MCH_3GPLL 1 2 CLK_MCH_3GPLL CLK_MCH_3GPLL 10
Vtt_PwrGd#/PD SRCT5 R397 33_0402_5%~D
61 MCH_3GPLL# 1 2 CLK_MCH_3GPLL# CLK_MCH_3GPLL# 10
SRCC5
1 2 CLKIREF 9 IREF
R402 33_0402_5%~D
R362 475_0402_1%~D 29 CLK_3GPLLREQ# 10
CLKREQ5# R299 1 2 10K_0402_5%~D +3.3V_RUN
58 PCIE_LOM 1 2 CLK_PCIE_LOM CLK_PCIE_LOM 28
CLK_SCLK SRCT4 R1435 33_0402_5%~D
16 SMBCLK
59 PCIE_LOM# 1 2 CLK_PCIE_LOM# CLK_PCIE_LOM# 28
R531 SRCC4 R1436 33_0402_5%~D
CLKREQ4# 57 LOM_CLKREQ# 28
8.2K_0402_5%~D CLK_SDATA 17 1 2 +3.3V_RUN
SMBDAT R1762 10K_0402_5%~D
SRCT3 55
FSC 2 1 1 2 FSB 1 2
MCH_CLKSEL2 10 MCH_CLKSEL1 10
4 GNDSRC SRCC3 56
R330 R354
8 CPU_BSEL2 0_0402_5%~D 8 CPU_BSEL1 0_0402_5%~D 15 28
GNDCPU CLKREQ3#
21 52 PCIE_MINI2 1 2 CLK_PCIE_MINI2
GNDREF SRCT2 CLK_PCIE_MINI2 34
FCTSEL1 R1393 33_0402_5%~D
+3.3V_RUN 31 53 PCIE_MINI2# 1 2 CLK_PCIE_MINI2#
GNDPCI SRCC2 CLK_PCIE_MINI2# 34
1

R1394 33_0402_5%~D
R291 35 26 MINI2CLK_REQ# 34
GNDPCI CLKREQ2#
2

FCTSEL1 PIN43 PIN44 PIN47 PIN48 10K_0402_5%~D R1395 1 2 10K_0402_5%~D +3.3V_RUN


R271 42 50 PCIE_MINI1 1 2 CLK_PCIE_MINI1
10K_0402_5%~D GND48 SRCT1 R1638 33_0402_5%~D CLK_PCIE_MINI1 34
2

0 DOT96T DOT96C 96/100M_T 96/100M_C 68 51 PCIE_MINI1# 1 2 CLK_PCIE_MINI1#


* GNDSRC SRCC1 R1639 33_0402_5%~D CLK_PCIE_MINI1# 34
1

FSA 46 MINI1CLK_REQ# 34
CLKREQ1#
1 27M_out 27M SSout SRCT0 SRCC0 73 THRM_PAD 1 2 +3.3V_RUN
1

A DOT96_SSC R1640 1 10K_0402_5%~D A


74 THRM_PAD LCD100/96/SRC0_T 47 2 DREF_SSCLK 10
@ R278 75 R524 33_0402_5%~D
THRM_PAD DOT96_SSC#
10K_0402_5%~D 76 THRM_PAD LCD100/96/SRC0_C 48 1 2 DREF_SSCLK# 10
R525 33_0402_5%~D

DELL CONFIDENTIAL/PROPRIETARY
2

Solder Thermal Pad to GND. Add min. 4 vias. SLG84450VTR_QFN72~D


Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL Title
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, Clock Generator
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD Size Document Number Rev
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. 0.6
LA-2791
Date: Tuesday, February 07, 2006 Sheet 6 of 63
5 4 3 2 1
5 4 3 2 1

10 H_A#[3..31] H_D#[0..63] 10
JCPUA
+1.05V_VCCP
H_A#3 J4 E22 H_D#0
H_A#4 L4
A3#
A4#
YONAH D0#
D1# F24 H_D#1

0.01U_0402_16V7K~D

0.01U_0402_16V7K~D
H_A#5 H_D#2

29
M3 A5# D2# E26
H_A#6 K5 H22 H_D#3 1 1 JITP +3.3V_SUS
H_A#7 A6# D3# H_D#4 R367
M1 F23

29
A7# D4#

C71

C72
H_A#8 N2 G25 H_D#5 28 150_0402_1%~D
H_A#9 A8# D5# H_D#6 VTT1 ITP_DBRESET#
J1 A9# D6# E25 27 VTT0 1 2
D H_A#10 H_D#7 2 @ 2 @ D
N3 A10# D7# E23 26 VTAP
H_A#11 P5 K24 H_D#8 ITP_DBRESET# 25
H_A#12 A11# D8# H_D#9 DBR# +1.05V_VCCP
P2 A12# D9# G24 24 DBA#
H_A#13 L1 J24 H_D#10 ITP_BPM#0 23 R415
H_A#14 A13# D10# H_D#11 BPM0# 51_0402_5%~D
P4 A14# D11# J23 22 GND5
H_A#15 P1 H26 H_D#12 ITP_BPM#1 21 1 2 ITP_TDO
H_A#16 A15# D12# H_D#13 BPM1# R416
R1 A16# D13# F26 20 GND4
H_A#17 Y2 K22 H_D#14 ITP_BPM#2 19 51_0402_5%~D
H_A#18 A17# D14# H_D#15 BPM2# H_RESET#
U5 A18# D15# H25 18 GND3 1 2
H_A#19 R3 N22 H_D#16 ITP_BPM#3 17 R33
H_A#20 A19# D16# H_D#17 BPM3# 54.9_0402_1%~D
W6 A20# D17# K25 16 GND2
H_A#21 U4 P26 H_D#18 ITP_BPM#4 15 1 2 ITP_BPM#5
H_A#22 A21# D18# H_D#19 R424 BPM4#
Y5 A22# D19# R23 14 GND1
H_A#23 U2 L25 H_D#20 22.6_0402_1%~D ITP_BPM#5 13
H_A#24 A23# D20# H_D#21 H_RESET# 1 BPM5#
R4 A24# D21# L22 2 12 RESET#
H_A#25 T5 ADDR GROUP DATA GROUP L23 H_D#22 ITP_TCK 11
H_A#26 A25# D22# H_D#23 FBO +1.05V_VCCP R387
T3 A26# D23# M23 10 GND0
H_A#27 W3 P25 H_D#24 R434 CLK_CPU_ITP 9 39.2_0402_1%~D
A27# D24# 6 CLK_CPU_ITP BCLKP
H_A#28 W5 P22 H_D#25 22.6_0402_1%~D CLK_CPU_ITP# 8 1 2 ITP_TMS
A28# D25# 6 CLK_CPU_ITP# BCLKN
H_A#29 Y4 P23 H_D#26 ITP_TDO 1 2 7 R417
H_A#30 A29# D26# H_D#27 TDO 150_0402_5%~D
W2 A30# D27# T24 6 NC2
H_A#31 Y1 R24 H_D#28 ITP_TCK 5 1 2 ITP_TDI
10 H_REQ#[0..4] A31# D28# H_D#29 TCK This shall place near CPU
D29# L26 4 NC1
H_REQ#0 K3 T25 H_D#30 ITP_TRST# 3 R391
H_REQ#1 REQ0# D30# H_D#31 ITP_TMS TRST# 680_0402_5%~D
H2 REQ1# D31# N24 2 TMS
H_REQ#2 K2 AA23 H_D#32 ITP_TDI 1 1 2 ITP_TRST#
H_REQ#3 REQ2# D32# H_D#33 TDI R436
J3 AB24

30
H_REQ#4 REQ3# D33# H_D#34 27.4_0402_1%~D
L5 REQ4# D34# V24
V26 H_D#35 @ MOLEX_52435-2891_28P~D 1 2 ITP_TCK

30
H_ADSTB#0 D35# H_D#36
10 H_ADSTB#0 L2 ADSTB0# D36# W25
H_ADSTB#1 V4 U23 H_D#37
10 H_ADSTB#1 ADSTB1# D37#
U25 H_D#38
C D38# H_D#39 C
D39# U22
AB25 H_D#40
D40# H_D#41
D41# W22
Y23 H_D#42
CLK_CPU_BCLK A22 D42# H_D#43
6 CLK_CPU_BCLK BCLK0 D43# AA26
CLK_CPU_BCLK# A21 HOST CLK Y26 H_D#44
6 CLK_CPU_BCLK# BCLK1 D44#
Y22 H_D#45
D45# H_D#46
D46# AC26
AA24 H_D#47
H_ADS# D47# H_D#48
10 H_ADS# H1 ADS# D48# AC22
H_BNR# E2 AC23 H_D#49
10 H_BNR# BNR# D49#
H_BPRI# G5 AB22 H_D#50
10 H_BPRI# BPRI# D50#
H_BR0# F1 AA21 H_D#51
10 H_BR0# BR0# D51#
H_DEFER# H5 AB21 H_D#52
10 H_DEFER# H_DRD Y# DEFER# D52# H_D#53
10 H_DRDY# F21 DRDY# D53# AC25
R422 H_HIT# G6 AD20 H_D#54
10 H_HIT# HIT# D54#
56_0402_5%~D H_HITM# E4 CONTROL AE22 H_D#55
10 H_HITM# HITM# D55#
1 2 H_IERR# D20 AF23 H_D#56
+1.05V_VCCP H_LOCK# IERR# D56# H_D#57
10 H_LOCK# H4 LOCK# D57# AD24
H_RESET# B1 AE21 H_D#58
10 H_RESET# RESET# D58#
AD21 H_D#59
D59# H_D#60
10 H_RS#[0..2] D60# AE25
H_RS#0 F3 AF25 H_D#61
H_RS#1 RS0# D61# H_D#62
F4 RS1# D62# AF22
H_RS#2 G3 AF26 H_D#63
H_TRDY# RS2# D63#
10 H_TRDY# G2 TRDY#

DINV0# J26 H_DINV#0 10


DINV1# M26 H_DINV#1 10
ITP_BPM#0 AD4 V23
BPM0# DINV2# H_DINV#2 10
ITP_BPM#1 AD3 AC20
BPM1# DINV3# H_DINV#3 10
ITP_BPM#2 AD1
B ITP_BPM#3 BPM2# B
AC4 BPM3# H_DSTBN#[0..3] 10
H23 H_DSTBN#0
ITP_DBRESET# DSTBN0# H_DSTBN#1
23,39 ITP_DBRESET# C20 DBR# DSTBN1# M24
H_DBSY# E1 W24 H_DSTBN#2
10 H_DBSY# DBSY# DSTBN2#
H_DPSLP# B5 AD23 H_DSTBN#3
22 H_DPSLP# DPSLP# DSTBN3# H_DSTBP#[0..3] 10
H_DPRSTP# E5 G22 H_DSTBP#0
22,49 H_DPRSTP# DPRSTP# DSTBP0#
H_DPWR# D24 N25 H_DSTBP#1
10 H_DPWR# ITP_BPM#4 DPWR# DSTBP1# H_DSTBP#2
AC2 PRDY# MISC DSTBP2# Y25
ITP_BPM#5 AC1 AE24 H_DSTBP#3
PREQ# DSTBP3#
38 CPU_PROCHOT# D21 PROCHOT#
Pop R1378 required by 22 H_PWRGOOD D6 PWRGOOD
H_CPUSLP# D7
Intel for B0 Yonah. 10,22 H_CPUSLP# SLP#
ITP_TCK AC5
R1387 @ ITP_TDI TCK H_A20M#
Backward compatible for AA6 TDI A20M# A6 H_A20M# 22
1K_0603_1%~D ITP_TDO AB3 A5 H_FERR#
A0 and A1 Yonah TDO FERR# H_FERR# 22
2 1 TEST1 C26 C4 H_IGNNE#
TEST1 IGNNE# H_IGNNE# 22
2 1 TEST2 D25 B3 H_INIT#
TEST2 INIT# H_INIT# 22
R1378 ITP_TMS AB5 C6 H_INTR
TMS LINT0 H_INTR 22
51_0603_1%~D ITP_TRST# AB6 B4 H_NMI
TRST# LINT1 H_NMI 22
LEGACY CPU
THERMAL
H_THERMDA A24 D5 H_STPCLK#
18 H_THERMDA H_THERMDC THERMDA DIODE STPCLK# H_SMI#
H_STPCLK# 22
18 H_THERMDC A25 THERMDC SMI# A3 H_SMI# 22
C7 THERMTRIP#
H_THERMTRIP#
18 H_THERMTRIP# TYCO_1-1674770-2_Yonah~D

H_THERMDA, H_THERMDC routing together.


Trace width / Spacing = 10 / 10 mil R398
A 56_0402_5%~D A

+1.05V_VCCP 1 2 H_THERMTRIP#

DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL Title
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, Yonah in mFCPGA479
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD Size Document Number Rev
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. 0.6
LA-2791
Date: Tuesday, February 07, 2006 Sheet 7 of 63
5 4 3 2 1
5 4 3 2 1

Length match within 25 mils


+VCC_CORE
JCPUB JCPUC

VCCSENSE AF7 AB26 AE18 K1


49 VCCSENSE VCCSENSE VSS VCC VSS
VSSSENSE AE7 AA25 AE17 J2
49 VSSSENSE VSSSENSE VSS VCC VSS
VSS AD25 AB15 VCC VSS M2
VSS AE26 AA15 VCC VSS N1
+1.5V_RUN B26 VCCA VSS AB23 AD15 VCC VSS T1
VSS AC24 AC15 VCC VSS R2
+1.05V_VCCP K6 VCCP VSS AF24 AF15 VCC VSS V2
D D
J6 VCCP VSS AE23 AE15 VCC VSS W1
M6 VCCP VSS AA22 AB14 VCC VSS A26
N6 AD22 AA13 D26
+1.05V_VCCP T6
VCCP
VCCP
YONAH VSS
VSS AC21 AD14
VCC
VCC
VSS
VSS C25
R6 VCCP VSS AF21 AC13 VCC VSS F25
R_A K21 VCCP VSS AB19 AF14 VCC VSS B24
1

0.01U_0402_16V7K~D

10U_0805_4VAM~D
J21 VCCP VSS AA19 AE13 VCC VSS A23
+VCC_CORE M21 AD19 AB12 D23
1 1 VCCP VSS VCC VSS
R140 R555 N21 AC19 AA12 E24
V_CPU_GTLREF VCCP VSS VCC YONAH VSS

C88

C87
1K_0402_1%~D 100_0402_1%~D T21 AF19 AD12 B21
VCCSENSE VCCP VSS VCC VSS
1 2 R21 AE19 AC12 C22
2

2 2 VCCP VSS VCC VSS


V21 VCCP VSS AB16 AF12 VCC VSS F22
R556 W21 AA16 AE12 E21

POWER, GROUNG, RESERVED SIGNALS AND NC


100_0402_1%~D VCCP VSS VCC VSS
R_B V6 VCCP VSS AD16 AB10 VCC VSS B19
1

1 2 VSSSENSE G21 AC16 AB9 A19


VCCP VSS VCC VSS
VSS AF16 AA10 VCC VSS D19
R147 AE16 AA9 C19
2K_0402_1%~D H_PSI# VSS VCC VSS
49 H_PSI# AE6 PSI# VSS AB13 AD10 VCC VSS F19
AA14 AD9 E19
2

VID0 VSS VCC VSS


49 VID0 AD6 VID0 VSS AD13 AC10 VCC VSS B16
VID1 AF5 AC14 AC9 A16
49 VID1 VID1 VSS VCC VSS
VID2 AE5 AF13 AF10 D16
49 VID2 VID2 VSS VCC VSS
VID3 AF4 AE14 AF9 C16
Layout close CPU PIN AD26 Layout close CPU 49 VID3
VID4 AE3
VID3 VSS
AB11 AE10
VCC
POWER, GROUND VSS
F16
49 VID4 VID4 VSS VCC VSS
VID5
0.5 inch (max) 49 VID5
VID6
AF2
AE2
VID5 VSS AA11
AD11
AE9
AB7
VCC VSS E16
B13
49 VID6 VID6 VSS VCC VSS
VSS AC11 AA7 VCC VSS A14
VSS AF11 AD7 VCC VSS D13
V_CPU_GTLREF AD26 GTLREF VSS AE11 AC7 VCC VSS C14
VSS AB8 B20 VCC VSS F13
10 CPU_BSEL0 CPU_BSEL0 B22 AA8 A20 E14
CPU_BSEL1 BSEL0 VSS VCC VSS
6 CPU_BSEL1 B23 BSEL1 VSS AD8 F20 VCC VSS B11
C CPU_BSEL2 C
6 CPU_BSEL2 C21 BSEL2 VSS AC8 E20 VCC VSS A11
VSS AF8 B18 VCC VSS D11
COMP0 R26 AE8 B17 C11
COMP1 COMP0 VSS VCC VSS
U26 COMP1 VSS AA5 A18 VCC VSS F11
COMP2 U1 AD5 A17 E11
COMP3 COMP2 VSS VCC VSS
V1 COMP3 VSS AC6 D18 VCC VSS B8
VSS AF6 D17 VCC VSS A8
VSS AB4 C18 VCC VSS D8
+VCC_CORE E7 VCC VSS AC3 C17 VCC VSS C8
AB20 VCC VSS AF3 F18 VCC VSS F8
Resistor placed within AA20 VCC VSS AE4 F17 VCC VSS E8
27.4_0402_1%~D

54.9_0402_1%~D

27.4_0402_1%~D

54.9_0402_1%~D
AF20 AB1 E18 G26
0.5" of CPU pin.Trace AE20
VCC VSS
AA2 E17
VCC VSS
K26
VCC VSS VCC VSS
should be at least 25 AB18 VCC VSS AD2 B15 VCC VSS J25
1

1
AB17 AE1 A15 M25
mils away from any AA18
VCC VSS
B6 D15
VCC VSS
N26
VCC VSS VCC VSS
R129

R124

R465

R457

other toggling signal. AA17 VCC VSS C5 C15 VCC VSS T26
AD18 VCC VSS F5 F15 VCC VSS R25
AD17 E6 E15 V25
2

VCC VSS VCC VSS


AC18 VCC VSS H6 B14 VCC VSS W26
AC17 VCC VSS J5 A13 VCC VSS H24
AF18 VCC VSS M5 D14 VCC VSS G23
AF17 VCC VSS L6 C13 VCC VSS K23
VSS P6 F14 VCC VSS L24
VSS R5 E13 VCC VSS P24
D2 RSVD VSS V5 B12 VCC VSS N23
F6 RSVD VSS U6 A12 VCC VSS T23
D3 RSVD VSS Y6 D12 VCC VSS U24
C1 RSVD VSS A4 C12 VCC VSS Y24
CPU_BSEL CPU_BSEL2 CPU_BSEL1 CPU_BSEL0 AF1 RSVD VSS D4 F12 VCC VSS W23
D22 RSVD VSS E3 E12 VCC VSS H21
C23 RSVD VSS H3 B10 VCC VSS J22
B B
C24 RSVD VSS G4 B9 VCC VSS M22
133 0 0 1 AA1 RSVD VSS K4 A10 VCC VSS L21
AA4 RSVD VSS L3 A9 VCC VSS P21
AB2 RSVD VSS P3 D10 VCC VSS R22
AA3 RSVD VSS N4 D9 VCC VSS V22
166 0 1 1 M4 RSVD VSS T4 C10 VCC VSS U21
N5 RSVD VSS U3 C9 VCC VSS Y21
T2 RSVD VSS Y3 F10 VCC
V3 RSVD VSS W4 F9 VCC
B2 RSVD VSS D1 E10 VCC
C3 RSVD VSS C2 E9 VCC
T22 RSVD VSS F2 B7 VCC
B25 RSVD VSS G1 A7 VCC
F7 VCC

TYCO_1-1674770-2_Yonah~D TYCO_1-1674770-2_Yonah~D

A A

DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL Title
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, Yonah in mFCPGA479
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD Size Document Number Rev
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. 0.6
LA-2791
Date: Tuesday, February 07, 2006 Sheet 8 of 63
5 4 3 2 1
5 4 3 2 1

+VCC_CORE

Place these inside 1 1 1 1 1 1 1 1 1 1


socket cavity on L8
(North side C100 C429 C98 C430 C99 C472 C473 C119 C142 C141
Secondary) 10U_0805_4VAM~D 10U_0805_4VAM~D 10U_0805_4VAM~D 10U_0805_4VAM~D 10U_0805_4VAM~D 10U_0805_4VAM~D 10U_0805_4VAM~D 10U_0805_4VAM~D 10U_0805_4VAM~D 10U_0805_4VAM~D
2 2 2 2 2 2 2 2 2 2
D D

+VCC_CORE

Place these inside 1 1 1 1 1 1 1 1 1 1


socket cavity on L8
(Sorth side C428 C138 C447 C470 C469 C467 C471 C97 C102 C433
Secondary) 10U_0805_4VAM~D 10U_0805_4VAM~D 10U_0805_4VAM~D 10U_0805_4VAM~D 10U_0805_4VAM~D 10U_0805_4VAM~D 10U_0805_4VAM~D 10U_0805_4VAM~D 10U_0805_4VAM~D 10U_0805_4VAM~D
2 2 2 2 2 2 2 2 2 2

+VCC_CORE

Place these inside 1 1 1 1 1 1


socket cavity on L8
(North side C468 C140 C139 C446 C466 C137
Primary) 10U_0805_4VAM~D 10U_0805_4VAM~D 10U_0805_4VAM~D 10U_0805_4VAM~D 10U_0805_4VAM~D 10U_0805_4VAM~D
2 2 2 2 2 2

+VCC_CORE

Place these inside 1 1 1 1 1 1 22uF 0805 X5R -> 85 degree C 10uF 0805 X5R -> 85 degree C
socket cavity on L8
(Sorth side C448 C432 C426 C427 C431 C120
Primary) 10U_0805_4VAM~D 10U_0805_4VAM~D 10U_0805_4VAM~D 10U_0805_4VAM~D 10U_0805_4VAM~D 10U_0805_4VAM~D
C 2 2 2 2 2 2 C

High Frequence Decoupling

Near VCORE regulator.

+VCC_CORE
The caps need change to ESR=6m ohms
330U_D_2.5VM_R6M~D

330U_D_2.5VM_R6M~D

330U_D_2.5VM_R6M~D

330U_D_2.5VM_R6M~D

330U_D_2.5VM_R6M~D

330U_D_2.5VM_R6M~D

South Side Secondary 1 1 1 1 1 1 North Side Secondary


ESR <= 1.5m ohm
C352

C496

C354

C497

C618

C365

+ + + + + +

2 2 2 2 2 2 Capacitor > 1980uF


@

B B

7mOhm 7mOhm 7mOhm 7mOhm 7mOhm 7mOhm


PS CAP PS CAP PS CAP PS CAP PS CAP PS CAP

+1.05V_VCCP
330U_D2E_2.5VM_R9~D

1
1 1 1 1 1 1
@ C372

+ Place these inside


C415 C439 C451 C416 C462 C414 socket cavity on L8
0.1U_0402_10V7K~D 0.1U_0402_10V7K~D 0.1U_0402_10V7K~D 0.1U_0402_10V7K~D 0.1U_0402_10V7K~D 0.1U_0402_10V7K~D (North side
2 2 2 2 2 2 2 Secondary)

A CRB was 270uF A

DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL Title
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, CPU Bypass
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD Size Document Number Rev
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. 0.6
LA-2791
Date: Tuesday, February 07, 2006 Sheet 9 of 63
5 4 3 2 1
5 4 3 2 1

Description at page12

Note :
CFG3:17 has
internal pullup,
CFG18:19 has
+1.05V_VCCP internal pulldown
U40B

221_0402_1%~D
1
D D
7 H_D#[0..63] U40A H_A#[3..31] 7

R85
DMI_MRX_ITX_N0 AE35 K16 CPU_BSEL0 CPU_BSEL0 8
23 DMI_MRX_ITX_N0 DMIRXN0 CFG0
H_D#0 F1 H9 H_A#3 DMI_MRX_ITX_N1 AF39 K18 MCH_CLKSEL1
HD0# HA3# 23 DMI_MRX_ITX_N1 DMIRXN1 CFG1 MCH_CLKSEL1 6
H_D#1 J1 C9 H_A#4 DMI_MRX_ITX_N2 AG35 J18 MCH_CLKSEL2
HD1# HA4# 23 DMI_MRX_ITX_N2 DMIRXN2 CFG2 MCH_CLKSEL2 6
H_D#2 H1 E11 H_A#5 DMI_MRX_ITX_N3 AH39 F18 CFG3 PAD~D T34
23 DMI_MRX_ITX_N3

2
H_D#3 HD2# HA5# H_A#6 H_SWNG1 DMIRXN3 CFG3 CFG4
J6 HD3# HA6# G11 CFG4 E15 PAD~D T35
H_D#4 H3 F11 H_A#7 F15 CFG5 CFG5 12
HD4# HA7# CFG5

0.1U_0402_16V4Z~D
H_D#5 K2 G12 H_A#8 DMI_MRX_ITX_P0 AC35 E18 CFG6 CFG6 12
HD5# HA8# 23 DMI_MRX_ITX_P0 DMIRXP0 CFG6

1
100_0402_1%~D
H_D#6 G1 F9 H_A#9 DMI_MRX_ITX_P1 AE39 D19 CFG7 CFG7 12
HD6# HA9# 23 DMI_MRX_ITX_P1 DMIRXP1 CFG7

R86
H_D#7 G2 H11 H_A#10 1 DMI_MRX_ITX_P2 AF35 D16 CFG8 PAD~D T41
HD7# HA10# 23 DMI_MRX_ITX_P2 DMIRXP2 CFG8

DMI
H_D#8 K9 J12 H_A#11 DMI_MRX_ITX_P3 AG39 G16 CFG9 CFG9 12
HD8# HA11# 23 DMI_MRX_ITX_P3 DMIRXP3 CFG9
H_D#9 K1 G14 H_A#12 E16 CFG10 PAD~D T42
HD9# HA12# CFG10

C65
H_D#10 K7 D9 H_A#13 D15 CFG11 CFG11 12

2
H_D#11 HD10# HA13# H_A#14 2 DMI_MTX_IRX_N0 CFG11 CFG12
J8 HD11# HA14# J14 23 DMI_MTX_IRX_N0 AE37 DMITXN0 CFG12 G15 CFG12 12
H_D#12 H4 H13 H_A#15 DMI_MTX_IRX_N1 AF41 K15 CFG13 CFG13 12
HD12# HA15# 23 DMI_MTX_IRX_N1 DMITXN1 CFG13
H_D#13 J3 J15 H_A#16 DMI_MTX_IRX_N2 AG37 C15 CFG14

CFG
HD13# HA16# 23 DMI_MTX_IRX_N2 DMITXN2 CFG14 PAD~D T43
H_D#14 K11 F14 H_A#17 DMI_MTX_IRX_N3 AH41 H16 CFG15 PAD~D T44
HD14# HA17# 23 DMI_MTX_IRX_N3 DMITXN3 CFG15
H_D#15 G4 D12 H_A#18 G18 CFG16 CFG16 12
H_D#16 HD15# HA18# H_A#19 CFG16 CFG17
T10 HD16# HA19# A11 CFG17 H15 PAD~D T45
H_D#17 W11 C11 H_A#20 DMI_MTX_IRX_P0 AC37 J25 CFG18 CFG18 12
HD17# HA20# +1.05V_VCCP 23 DMI_MTX_IRX_P0 DMITXP0 CFG18
H_D#18 T3 A12 H_A#21 DMI_MTX_IRX_P1 AE41 K27 CFG19 CFG19 12
HD18# HA21# 23 DMI_MTX_IRX_P1 DMITXP1 CFG19
H_D#19 U7 A13 H_A#22 DMI_MTX_IRX_P2 AF37 J26 CFG20 CFG20 12
HD19# HA22# 23 DMI_MTX_IRX_P2 DMITXP2 CFG20
H_D#20 U9 E13 H_A#23 DMI_MTX_IRX_P3 AG41
HD20# HA23# 23 DMI_MTX_IRX_P3 DMITXP3

221_0402_1%~D
H_D#21 U11 G13 H_A#24
HD21# HA24#

1
H_D#22 T11 F12 H_A#25 AG33 CLK_MCH_3GPLL 6
HD22# HA25# G_CLKP

R64
H_D#23 W9 B12 H_A#26 M_CLK_DDR0 AY35 AF33 CLK_MCH_3GPLL# 6
HD23# HA26# 16 M_CLK_DDR0 SM_CK0 G_CLKN
H_D#24 T1 B14 H_A#27 M_CLK_DDR1 AR1
HD24# HA27# 16 M_CLK_DDR1 SM_CK1
H_D#25 T8 C12 H_A#28 M_CLK_DDR2 AW7 A27

CLK
HD25# HA28# 17 M_CLK_DDR2 SM_CK2 D_REF_CLKN DREFCLK# 6
H_D#26 T4 A14 H_A#29 M_CLK_DDR3 AW40 A26 DREFCLK 6
17 M_CLK_DDR3

2
H_D#27 HD26# HA29# H_A#30 H_SWNG0 SM_CK3 D_REF_CLKP
W7 HD27# HA30# C14
H_D#28 U5 D14 H_A#31 M_CLK_DDR#0 AW35 C40
HD28# HA31# 16 M_CLK_DDR#0 SM_CK0# D_REF_SSCLKN DREF_SSCLK# 6

0.1U_0402_16V4Z~D
H_D#29 T9 M_CLK_DDR#1 AT1 D41
HD29# 16 M_CLK_DDR#1 SM_CK1# D_REF_SSCLKP DREF_SSCLK 6

1
100_0402_1%~D
C H_D#30 M_CLK_DDR#2 C
W6 HD30# 1 17 M_CLK_DDR#2 AY7 SM_CK2#

R65
H_D#31 T5 M_CLK_DDR#3 AY40 H32 CLK_3GPLLREQ# 6
HOST

HD31# H_REQ#[0..4] 7 17 M_CLK_DDR#3 SM_CK3# CLK_REQ#


H_D#32 AB7 D8 H_REQ#0
HD32# HREQ#0

C48
H_D#33 AA9 G8 H_REQ#1 DDR_CKE0_DIMMA AU20
HD33# HREQ#1 2 16 DDR_CKE0_DIMMA SM_CKE0

DDR MUXING
H_D#34 W4 B8 H_REQ#2 DDR_CKE1_DIMMA AT20
16 DDR_CKE1_DIMMA

2
H_D#35 HD34# HREQ#2 H_REQ#3 DDR_CKE2_DIMMB SM_CKE1
W3 HD35# HREQ#3 F8 17 DDR_CKE2_DIMMB BA29 SM_CKE2 NC0 A3
H_D#36 Y3 A8 H_REQ#4 DDR_CKE3_DIMMB AY29 A39
HD36# HREQ#4 17 DDR_CKE3_DIMMB SM_CKE3 NC1
H_D#37 Y7 A4
H_D#38 HD37# DDR_CS0_DIMMA# AW13 NC2
W5 HD38# 16 DDR_CS0_DIMMA# SM_CS0# NC3 A40
H_D#39 Y10 B9 H_ADSTB#0 DDR_CS1_DIMMA# AW12 AW1
HD39# HADSTB#0 H_ADSTB#0 7 16 DDR_CS1_DIMMA# SM_CS1# NC4
H_D#40 AB8 C13 H_ADSTB#1 DDR_CS2_DIMMB# AY21 AW41
HD40# HADSTB#1 H_ADSTB#1 7 17 DDR_CS2_DIMMB# SM_CS2# NC5
H_D#41 W2 DDR_CS3_DIMMB# AW21 AY1
HD41# 17 DDR_CS3_DIMMB# SM_CS3# NC6
H_D#42 AA4 AG1 BA1

NC
HD42# HCLKN CLK_MCH_BCLK# 6 NC7
H_D#43 AA7 AG2 M_OCDOCMP0 AL20 BA2
HD43# HCLKP CLK_MCH_BCLK 6 SM_OCDCOMP0 NC8
H_D#44 AA2 M_OCDOCMP1 AF10 BA3
HD44# H_DSTBN#[0..3] 7 +1.05V_VCCP SM_OCDCOMP1 NC9
H_D#45 AA6 K4 H_DSTBN#0 BA39
H_D#46 HD45# HDSTBN#0 H_DSTBN#1 M_ODT0 NC10
AA10 HD46# HDSTBN#1 T7 16 M_ODT0 BA13 SM_ODT0 NC11 BA40

100_0402_1%~D
H_D#47 Y8 Y5 H_DSTBN#2 +1.8V_SUS M_ODT1 BA12 BA41
HD47# HDSTBN#2 16 M_ODT1 SM_ODT1 NC12

1
H_D#48 AA1 AC4 H_DSTBN#3 M_ODT2 AY20 C1
HD48# HDSTBN#3 H_DSTBP#[0..3] 7 17 M_ODT2 SM_ODT2 NC13

R326
H_D#49 AB4 K3 H_DSTBP#0 M_ODT3 AU21 AY41
HD49# HDSTBP#0 17 M_ODT3 SM_ODT3 NC14
H_D#50 AC9 T6 H_DSTBP#1 B2
H_D#51 HD50# HDSTBP#1 H_DSTBP#2 R142 1 NC15
AB11 HD51# HDSTBP#2 AA5 2 80.6_0402_1%~D SMRCOMPN AV9 SM_RCOMPN NC16 B41
H_D#52 AC11 AC5 H_DSTBP#3 1 2 SMRCOMPP AT9 C41

2
H_D#53 HD52# HDSTBP#3 H_VREF R141 80.6_0402_1%~D SM_RCOMPP NC17
AB3 HD53# NC18 D1
+1.05V_VCCP H_D#54 AC2 AK1
HD54# SM_VREF0

0.1U_0402_16V4Z~D
H_D#55 AD1 J7 V_DDR_MCH_REF AK41
HD55# HDINV#0 H_DINV#0 7 SM_VREF1

200_0402_1%~D
H_D#56 AD9 W8 1 T32
HD56# HDINV#1 H_DINV#1 7 RESERVED1

R325

C363
H_D#57 AC1 U3 R32
HD57# HDINV#2 H_DINV#2 7 RESERVED2
H_D#58 AD7 AB10 23 PM_BMBUSY# G28 F3
HD58# HDINV#3 H_DINV#3 7 PM_BMBUSY# RESERVED3
1

1
54.9_0402_1%~D

54.9_0402_1%~D

H_D#59 AC6 16 PM_EXTTS#0 PM_EXTTS#0 F25 F7


HD59# 2 PM_EXTTS0# RESERVED4

PM
H_D#60 AB5 23 PM_EXTTS#1 PM_EXTTS#1 H26 AG11

RESERVED
2
HD60# PM_EXTTS1# RESERVED5
R80

R52

H_D#61 AD10 B7 H_RESET# 18 THERMTRIP_MCH# G6 AF11


B HD61# HCPURST# H_RESET# 7 PM_THERMTRIP# RESERVED6 B
H_D#62 AD4 E8 H_ADS# ICH_PWRGD AH33 H7
HD62# HADS# H_ADS# 7 23,42 ICH_PWRGD PWROK RESERVED7
H_D#63 AC8 E7 H_TRDY# 21,23,28,34,52 PLTRST# 2 1 PLTRST_R# AH34 J19
H_TRDY# 7
2

HD63# HTRDY# 100_0402_1%~D R441 RSTIN# RESERVED8


HDPWR# J9 H_DPWR# 7 RESERVED9 A41
H8 H_DRD Y# 21 MCH_ICH_SYNC# K28 A34
HDRDY# H_DRDY# 7 ICH_SYNC# RESERVED10
J13 C3 H_DEFER# D28
HVREF0 HDEFER# H_DEFER# 7 RESERVED11
H_VREF K13 D4 H_HITM# D27
HVREF1 HHITM# H_HITM# 7 RESERVED12
H_XRCOMP E1 D3 H_HIT# A35
HXRCOMP HHIT# H_HIT# 7 RESERVED13
H_XSCOMP E2 B3 H_LOCK#
HXSCOMP HLOCK# H_LOCK# 7
H_YRCOMP Y1 C7 H_BR0# CALISTOGA A0_FCBGA1466~D
HYRCOMP HBREQ0# H_BR0# 7
H_YSCOMP U1 C6 H_BNR# +3.3V_RUN_R
HYSCOMP HBNR# H_BNR# 7
H_SWNG0 E4 F6 H_BPRI#
HXSWING HBPRI# H_BPRI# 7
H_SWNG1 W1 A7 H_DBSY#
HYSWING HDBSY# H_DBSY# 7
E3 H_CPUSLP# Layout Note:
HCPUSLP# H_CPUSLP# 7,22
24.9_0402_1%~D

24.9_0402_1%~D

Route as short
1

R336
B4 H_RS#0 as possible 10K_0402_5%~D
HRS0#
R57

R90

E6 H_RS#1 PM_EXTTS#0 2 1
HRS1# H_RS#2 V_DDR_MCH_REF
HRS2# D6 16,17,48 V_DDR_MCH_REF

0.1U_0402_16V4Z~D
@ R253
2

H_RS#[0..2] 7 10K_0402_5%~D
CALISTOGA A0_FCBGA1466~D 1 PM_EXTTS#1 2 1
M_OCDOCMP0

C425
M_OCDOCMP1
2

40.2_0402_1%~D

40.2_0402_1%~D
@

1
R335
75_0402_5%~D

@ R435

@ R437
THERMTRIP_MCH# 1 2 +1.05V_VCCP

2
A A

Stuff R435 & R437 for A1 Calistoga


Layout Note:
H_XRCOMP & H_YRCOMP trace width
DELL CONFIDENTIAL/PROPRIETARY
and spacing is 10/20
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL Title
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, Calistoga(1 of 6)
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD Size Document Number Rev
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. 0.6
LA-2791
Date: Tuesday, February 07, 2006 Sheet 10 of 63
5 4 3 2 1
5 4 3 2 1

D D
D
E
U40D U40E

DDR_A_D[0..63] 16 DDR_B_D[0..63] 17
DDR_A_BS0 AU12 AJ35 DDR_A_D0 DDR_B_BS0 AT24 AK39 DDR_B_D0
16 DDR_A_BS0 SA_BS0 SA_DQ0 17 DDR_B_BS0 SB_BS0 SB_DQ0
DDR_A_BS1 AV14 AJ34 DDR_A_D1 DDR_B_BS1 AV23 AJ37 DDR_B_D1
16 DDR_A_BS1 SA_BS1 SA_DQ1 17 DDR_B_BS1 SB_BS1 SB_DQ1
DDR_A_BS2 BA20 AM31 DDR_A_D2 DDR_B_BS2 AY28 AP39 DDR_B_D2
16 DDR_A_BS2 SA_BS2 SA_DQ2 17 DDR_B_BS2 SB_BS2 SB_DQ2
AM33 DDR_A_D3 AR41 DDR_B_D3
SA_DQ3 DDR_A_D4 SB_DQ3 DDR_B_D4
SA_DQ4 AJ36 SB_DQ4 AJ38
AK35 DDR_A_D5 AK38 DDR_B_D5
16 DDR_A_DM[0..7] SA_DQ5 17 DDR_B_DM[0..7] SB_DQ5
DDR_A_DM0 AJ33 AJ32 DDR_A_D6 DDR_B_DM0 AK36 AN41 DDR_B_D6
DDR_A_DM1 SA_DM0 SA_DQ6 DDR_A_D7 DDR_B_DM1 SB_DM0 SB_DQ6 DDR_B_D7
AM35 SA_DM1 SA_DQ7 AH31 AR38 SB_DM1 SB_DQ7 AP41
DDR_A_DM2 AL26 AN35 DDR_A_D8 DDR_B_DM2 AT36 AT40 DDR_B_D8
DDR_A_DM3 SA_DM2 SA_DQ8 DDR_A_D9 DDR_B_DM3 SB_DM2 SB_DQ8 DDR_B_D9
AN22 SA_DM3 SA_DQ9 AP33 BA31 SB_DM3 SB_DQ9 AV41
DDR_A_DM4 AM14 AR31 DDR_A_D10 DDR_B_DM4 AL17 AU38 DDR_B_D10
DDR_A_DM5 SA_DM4 SA_DQ10 DDR_A_D11 DDR_B_DM5 SB_DM4 SB_DQ10 DDR_B_D11
AL9 SA_DM5 SA_DQ11 AP31 AH8 SB_DM5 SB_DQ11 AV38
DDR_A_DM6 AR3 AN38 DDR_A_D12 DDR_B_DM6 BA5 AP38 DDR_B_D12
DDR_A_DM7 SA_DM6 SA_DQ12 DDR_A_D13 DDR_B_DM7 SB_DM6 SB_DQ12 DDR_B_D13
AH4 SA_DM7 SA_DQ13 AM36 AN4 SB_DM7 SB_DQ13 AR40
AM34 DDR_A_D14 AW38 DDR_B_D14
SA_DQ14 DDR_A_D15 SB_DQ14 DDR_B_D15
SA_DQ15 AN33 SB_DQ15 AY38
AK26 DDR_A_D16 BA38 DDR_B_D16
SA_DQ16 DDR_A_D17 SB_DQ16 DDR_B_D17
16 DDR_A_DQS[0..7] SA_DQ17 AL27 17 DDR_B_DQS[0..7] SB_DQ17 AV36
DDR_A_DQS0 AK33 AM26 DDR_A_D18 DDR_B_DQS0 AM39 AR36 DDR_B_D18
DDR_A_DQS1 SA_DQS0 SA_DQ18 DDR_A_D19 DDR_B_DQS1 SB_DQS0 SB_DQ18 DDR_B_D19
AT33 SA_DQS1 SA_DQ19 AN24 AT39 SB_DQS1 SB_DQ19 AP36
DDR_A_DQS2 AN28 AK28 DDR_A_D20 DDR_B_DQS2 AU35 BA36 DDR_B_D20

DDR SYS MEMORY A

DDR SYS MEMORY B


DDR_A_DQS3 SA_DQS2 SA_DQ20 DDR_A_D21 DDR_B_DQS3 SB_DQS2 SB_DQ20 DDR_B_D21
AM22 SA_DQS3 SA_DQ21 AL28 AR29 SB_DQS3 SB_DQ21 AU36
DDR_A_DQS4 AN12 AM24 DDR_A_D22 DDR_B_DQS4 AR16 AP35 DDR_B_D22
DDR_A_DQS5 SA_DQS4 SA_DQ22 DDR_A_D23 DDR_B_DQS5 SB_DQS4 SB_DQ22 DDR_B_D23
AN8 SA_DQS5 SA_DQ23 AP26 AR10 SB_DQS5 SB_DQ23 AP34
DDR_A_DQS6 AP3 AP23 DDR_A_D24 DDR_B_DQS6 AR7 AY33 DDR_B_D24
DDR_A_DQS7 SA_DQS6 SA_DQ24 DDR_A_D25 DDR_B_DQS7 SB_DQS6 SB_DQ24 DDR_B_D25
AG5 SA_DQS7 SA_DQ25 AL22 AN5 SB_DQS7 SB_DQ25 BA33
C DDR_A_D26 DDR_B_D26 C
SA_DQ26 AP21 SB_DQ26 AT31
AN20 DDR_A_D27 AU29 DDR_B_D27
16 DDR_A_DQS#[0..7] SA_DQ27 17 DDR_B_DQS#[0..7] SB_DQ27
DDR_A_DQS#0 AK32 AL23 DDR_A_D28 DDR_B_DQS#0 AM40 AU31 DDR_B_D28
DDR_A_DQS#1 AU33 SA_DQS0# SA_DQ28 DDR_A_D29 DDR_B_DQS#1 SB_DQS0# SB_DQ28 DDR_B_D29
SA_DQS1# SA_DQ29 AP24 AU39 SB_DQS1# SB_DQ29 AW31
DDR_A_DQS#2 AN27 AP20 DDR_A_D30 DDR_B_DQS#2 AT35 AV29 DDR_B_D30
DDR_A_DQS#3 AM21 SA_DQS2# SA_DQ30 DDR_A_D31 DDR_B_DQS#3 SB_DQS2# SB_DQ30 DDR_B_D31
SA_DQS3# SA_DQ31 AT21 AP29 SB_DQS3# SB_DQ31 AW29
DDR_A_DQS#4 AM12 AR12 DDR_A_D32 DDR_B_DQS#4 AP16 AM19 DDR_B_D32
DDR_A_DQS#5 AL8 SA_DQS4# SA_DQ32 DDR_A_D33 DDR_B_DQS#5 SB_DQS4# SB_DQ32 DDR_B_D33
SA_DQS5# SA_DQ33 AR14 AT10 SB_DQS5# SB_DQ33 AL19
DDR_A_DQS#6 AN3 AP13 DDR_A_D34 DDR_B_DQS#6 AT7 AP14 DDR_B_D34
DDR_A_DQS#7 AH5 SA_DQS6# SA_DQ34 DDR_A_D35 DDR_B_DQS#7 SB_DQS6# SB_DQ34 DDR_B_D35
SA_DQS7# SA_DQ35 AP12 AP5 SB_DQS7# SB_DQ35 AN14
AT13 DDR_A_D36 AN17 DDR_B_D36
SA_DQ36 DDR_A_D37 SB_DQ36 DDR_B_D37
SA_DQ37 AT12 SB_DQ37 AM16
AL14 DDR_A_D38 AP15 DDR_B_D38
16 DDR_A_MA[0..13] SA_DQ38 17 DDR_B_MA[0..13] SB_DQ38
DDR_A_MA0 AY16 AL12 DDR_A_D39 DDR_B_MA0 AY23 AL15 DDR_B_D39
DDR_A_MA1 SA_MA0 SA_DQ39 DDR_A_D40 DDR_B_MA1 SB_MA0 SB_DQ39 DDR_B_D40
AU14 SA_MA1 SA_DQ40 AK9 AW24 SB_MA1 SB_DQ40 AJ11
DDR_A_MA2 AW16 AN7 DDR_A_D41 DDR_B_MA2 AY24 AH10 DDR_B_D41
DDR_A_MA3 SA_MA2 SA_DQ41 DDR_A_D42 DDR_B_MA3 SB_MA2 SB_DQ41 DDR_B_D42
BA16 SA_MA3 SA_DQ42 AK8 AR28 SB_MA3 SB_DQ42 AJ9
DDR_A_MA4 BA17 AK7 DDR_A_D43 DDR_B_MA4 AT27 AN10 DDR_B_D43
DDR_A_MA5 SA_MA4 SA_DQ43 DDR_A_D44 DDR_B_MA5 SB_MA4 SB_DQ43 DDR_B_D44
AU16 SA_MA5 SA_DQ44 AP9 AT28 SB_MA5 SB_DQ44 AK13
DDR_A_MA6 AV17 AN9 DDR_A_D45 DDR_B_MA6 AU27 AH11 DDR_B_D45
DDR_A_MA7 SA_MA6 SA_DQ45 DDR_A_D46 DDR_B_MA7 SB_MA6 SB_DQ45 DDR_B_D46
AU17 SA_MA7 SA_DQ46 AT5 AV28 SB_MA7 SB_DQ46 AK10
DDR_A_MA8 AW17 AL5 DDR_A_D47 DDR_B_MA8 AV27 AJ8 DDR_B_D47
DDR_A_MA9 SA_MA8 SA_DQ47 DDR_A_D48 DDR_B_MA9 SB_MA8 SB_DQ47 DDR_B_D48
AT16 SA_MA9 SA_DQ48 AY2 AW27 SB_MA9 SB_DQ48 BA10
DDR_A_MA10 AU13 AW2 DDR_A_D49 DDR_B_MA10 AV24 AW10 DDR_B_D49
DDR_A_MA11 SA_MA10 SA_DQ49 DDR_A_D50 DDR_B_MA11 SB_MA10 SB_DQ49 DDR_B_D50
AT17 SA_MA11 SA_DQ50 AP1 BA27 SB_MA11 SB_DQ50 BA4
DDR_A_MA12 AV20 AN2 DDR_A_D51 DDR_B_MA12 AY27 AW4 DDR_B_D51
DDR_A_MA13 SA_MA12 SA_DQ51 DDR_A_D52 DDR_B_MA13 SB_MA12 SB_DQ51 DDR_B_D52
AV12 SA_MA13 SA_DQ52 AV2 AR23 SB_MA13 SB_DQ52 AY10
AT3 DDR_A_D53 AY9 DDR_B_D53
SA_DQ53 DDR_A_D54 SB_DQ53 DDR_B_D54
SA_DQ54 AN1 SB_DQ54 AW5
AL2 DDR_A_D55 AY5 DDR_B_D55
DDR_A_CAS# AY13 SA_DQ55 DDR_A_D56 DDR_B_CAS# SB_DQ55 DDR_B_D56
16 DDR_A_CAS# SA_CAS# SA_DQ56 AG7 17 DDR_B_CAS# AR24 SB_CAS# SB_DQ56 AV4
DDR_A_RAS# AW14 AF9 DDR_A_D57 DDR_B_RAS# AU23 AR5 DDR_B_D57
B 16 DDR_A_RAS# SA_RAS# SA_DQ57 17 DDR_B_RAS# SB_RAS# SB_DQ57 B
DDR_A_WE# AY14 AG4 DDR_A_D58 DDR_B_WE# AR27 AK4 DDR_B_D58
16 DDR_A_WE# SA_WE# SA_DQ58 17 DDR_B_WE# SB_WE# SB_DQ58
SA_RCVENIN# AK23 AF6 DDR_A_D59 SB_RCVENIN# AK16 AK3 DDR_B_D59
T2022 PAD~D SA_RCVENOUT# AK24 SA_RCVENIN# SA_DQ59 DDR_A_D60 T2023 PAD~D SB_RCVENOUT# SB_RCVENIN# SB_DQ59 DDR_B_D60
SA_RCVENOUT# SA_DQ60 AG9 AK18 SB_RCVENOUT# SB_DQ60 AT4
T2024 PAD~D AH6 DDR_A_D61 T2025 PAD~D AK5 DDR_B_D61
SA_DQ61 DDR_A_D62 SB_DQ61 DDR_B_D62
SA_DQ62 AF4 SB_DQ62 AJ5
AF8 DDR_A_D63 AJ3 DDR_B_D63
SA_DQ63 SB_DQ63

CALISTOGA A0_FCBGA1466~D CALISTOGA A0_FCBGA1466~D

A A

DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL Title
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, Calistogo(2 of 6)
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD Size Document Number Rev
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. 0.6
LA-2791
Date: Tuesday, February 07, 2006 Sheet 11 of 63
5 4 3 2 1
5 4 3 2 1

LOW = Moby Dick

C +1.5VRUN_PCIE
R1493
U40C 24.9_0402_1%~D
SDVO_CTRLDATA H27 D40 PEGCOMP 1 2
52 SDVO_CTRLDATA SDVOCTRL_DATA EXP_COMPI
SDVO_CTRLCLK H28 D38
52 SDVO_CTRLCLK SDVOCTRL_CLK EXP_COMPO

EXP_RXN0 F34 Strap Pin Table


D 19 LCD_A0+ B37 LA_DATA0 EXP_RXN1 G38 SDVOB_INT- 52 Low = DMI x 2 D
19 LCD_A1+ B34 LA_DATA1 EXP_RXN2 H34 CFG5
19 LCD_A2+ A36 LA_DATA2 EXP_RXN3 J38 High = DMI x 4 *
L34 R307 1 2 @ 2.2K_0402_5%~D
EXP_RXN4 10 CFG5
19 LCD_A0- C37 LA_DATA#0 EXP_RXN5 M38 LOW = Moby Dick
B35 N34 CFG6 R67 1 2 @ 2.2K_0402_5%~D
19 LCD_A1- LA_DATA#1 EXP_RXN6 10 CFG6
19 LCD_A2- A37 LA_DATA#2 EXP_RXN7 P38 HIGH = Calistoga *
R34 R281 1 2 @ 2.2K_0402_5%~D
EXP_RXN8 10 CFG7
19 LCD_B0+ F30 LB_DATA0 EXP_RXN9 T38 Low = DT/Transportable CPU
CFG7 R282 @ 2.2K_0402_5%~D

LVDS
19 LCD_B1+ D29 LB_DATA1 EXP_RXN10 V34 10 CFG9 1 2
19 LCD_B2+ F28 LB_DATA2 EXP_RXN11 W38 High = Mobile CPU *
Y34 R357 1 2 @ 2.2K_0402_5%~D
EXP_RXN12 10 CFG11
19 LCD_B0- G30 LB_DATA#0 EXP_RXN13 AA38 Low = Reverse Lane
D30 AB34 CFG9 R288 1 2 @ 2.2K_0402_5%~D
19 LCD_B1- LB_DATA#1 EXP_RXN14 10 CFG12
19 LCD_B2- F29 LB_DATA#2 EXP_RXN15 AC38 High = Normal Operation * R323 1 2 @ 2.2K_0402_5%~D
10 CFG13
19 LCD_ACLK+ A32 LA_CLK EXP_RXP0 D34
A33 F38 R346 1 2 @ 2.2K_0402_5%~D
19 LCD_ACLK- LA_CLK# EXP_RXP1 SDVOB_INT+ 52 10 CFG16
19 LCD_BCLK+ E26 LB_CLK EXP_RXP2 G34 CFG11
19 LCD_BCLK- E27 LB_CLK# EXP_RXP3 H38
J34 CFG[3:17] have internal pullup

PCI-EXPRESS GRAPHICS
BIA_PWM_R EXP_RXP4
D32 LBKLT_CTL EXP_RXP5 L38 00 = Reserved
PANEL_BKEN J30 M34 01 = XOR Mode Enabled
19 PANEL_BKEN LBKLT_EN EXP_RXP6
LCTLA_CLK H30 N38 CFG[13:12] 10 = All Z Mode Enabled
LCTLB_DATA LCTLA_CLK EXP_RXP7 +3.3V_RUN_R
H29 LCTLB_DATA EXP_RXP8 P34 11 = Normal Operation *
LDDC_CLK G26 R38 (Default)
19 LDDC_CLK LDDC_CLK EXP_RXP9
LDDC_DATA G25 T34
19 LDDC_DATA LDDC_DATA EXP_RXP10
F32 V38 @
19 ENVDD LVDD_EN EXP_RXP11
2 1 L_IBG B38 W34 CFG16 Low = Disabled R308 1 2 1K_0402_5%~D
LIBG EXP_RXP12 10 CFG18
R251 C35 Y38 1 2
LVBG EXP_RXP13 10 CFG19
1.5K_0402_1%~D (FSB Dynamic ODT) High = Enabled R306 @1K_0402_5%~D
LVREF for Alviso N.C
C33
C32
LVREFH EXP_RXP14 AA34
AB38
* 1 2
LVREFL EXP_RXP15 10 CFG20
R310 @1K_0402_5%~D
C for Calistoga to GND C
EXP_TXN0 F36 DVO_RED#_C C1346 1 2 0.1U_0402_16V4Z~D
SDVOB_RED- 52 CFG18 Low = 1.05V (Default) *
36 TV_CVBS A16 TVDAC_A EXP_TXN1 G40 DVO_GREEN#_CC1347 1 2 0.1U_0402_16V4Z~D
SDVOB_GREEN- 52
36 TV_Y C18 TVDAC_B EXP_TXN2 H36 DVO_BLUE#_C C1348 1 2 0.1U_0402_16V4Z~D
SDVOB_BLUE- 52 (VCC Select) High = 1.5V CFG[18:20] have internal pulldown
36 TV_C A19 TVDAC_C EXP_TXN3 J40 DVO_CLK#_C C1349 1 2 0.1U_0402_16V4Z~D
SDVOB_CLK- 52
150_0402_1%~D

150_0402_1%~D

150_0402_1%~D

TV

EXP_TXN4 L36 Low = Normal *


1

TVIREF J20 M40


TV_IREF EXP_TXN5 Operation (Default):
1

4.99K_0402_1%~D

EXP_TXN6 N36 CFG19


R25

R24

R23

B16 TV_IRTNA EXP_TXN7 P40 Lane number in Order


R314

B18 TV_IRTNB EXP_TXN8 R36 (DMI Lane Reversal)


B19 T40 High = Reverse Lane
2

TV_IRTNC EXP_TXN9
V36
2

EXP_TXN10
J29 TV_DCONSEL1 EXP_TXN11 W40
K30 TV_DCONSEL0 EXP_TXN12 Y36 Low = No SDVO Device Present
EXP_TXN13 AA40 SDVO_CTRLDATA (Default)*
Close to U40.J20 EXP_TXN14 AB36 High = SDVO Device Present
EXP_TXN15 AC40
G_CLK_DDC2 C26 DDCCLK
CRT

G_DAT_DDC2 C25 D36 DVO_RED_C C1350 1 2 0.1U_0402_16V4Z~D Low = Only PCIE or SDVO is
DDCDATA EXP_TXP0 SDVOB_RED+ 52
F40 DVO_GREEN_CC1360 1 2 0.1U_0402_16V4Z~D CFG20
EXP_TXP1 SDVOB_GREEN+ 52 operational. (Default)
DVO_BLUE_C C1372 1 0.1U_0402_16V4Z~D
20 VGA_VSYNC H23 VSYNC EXP_TXP2 G36
DVO_CLK_C C1359 1
2
0.1U_0402_16V4Z~D
SDVOB_BLUE+ 52 *
20 VGA_HSYNC G23 HSYNC EXP_TXP3 H40 2 SDVOB_CLK+ 52 (PCIE/SDVO select)
20,36 VGA_BLU E23 BLUE EXP_TXP4 J36 High = PCIE/SDVO are operating
D23 L40
C22
BLUE# EXP_TXP5
M36 simu.
20,36 VGA_GRN GREEN EXP_TXP6
B22 GREEN# EXP_TXP7 N40
20,36 VGA_RED A21 RED EXP_TXP8 P36
B21 RED# EXP_TXP9 R40
EXP_TXP10 T36
EXP_TXP11 V40
2 1 J22 CRT_IREF EXP_TXP12 W36
Close to U40.J22 EXP_TXP13 Y40
R150 AA36
B 255_0402_1%~D EXP_TXP14 B
EXP_TXP15 AB40
+3.3V_RUN_R

CALISTOGA A0_FCBGA1466~D VGA_RED 1 2


R261 150_0402_1%~D

2.2K_0402_5%~D

2.2K_0402_5%~D
VGA_GRN 1 2

1
R260 150_0402_1%~D

R229

R232
VGA_BLU 1 2
R295 150_0402_1%~D

D
G_CLK_DDC2 3 1 CLK_DDC2
CLK_DDC2 20,36
Q31
BSS138W-7-F_SOT323~D

G
2
+3.3V_RUN_R +3.3V_RUN_R

2
G
+3.3V_RUN_R
1 2 LCTLA_CLK G_DAT_DDC2 3 1 DAT_DDC2
DAT_DDC2 20,36
R283 10K_0402_5%~D

D
Q27
5

1 2 LCTLB_DATA BSS138W-7-F_SOT323~D
R279 10K_0402_5%~D 1
P

IN1 BIA_PWM_R
19,39 BIA_PWM 4 O
IN2 2
G

U8
3

74AHC1G08GW_SOT353-5~D

A A

1 2 PANEL_BKEN
R300 100K_0402_5%~D

DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL Title
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, Calistoga(3 of 6)
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD Size Document Number Rev
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. 0.6
LA-2791
Date: Tuesday, February 07, 2006 Sheet 12 of 63
5 4 3 2 1
5 4 3 2 1

U40H +2.5V_RUN
+1.05V_VCCP H22 C465 1
VCC_SYNC 0.1U_0402_16V4Z~D
AC14
AB14
VTT0
VTT1 VCCTX_LVDS0 B30 +2.5V_RUN 2
Should be placed on top
+2.5V_RUN
+3V_TVDAC
W14 C30 +3VRUN_TVDACA +3V_TVDAC L9
VTT2 VCCTX_LVDS1 +1.5VRUN_PCIE BLM18PG181SN1_0603~D
V14 A30
T14
VTT3
VTT4
VCCTX_LVDS2 W=30 mils BLM21PG600SN1D_0805~D
1
1 2 2 1 +3.3V_RUN_R

10U_0805_4VAM~D
R14 AB41 2 1 +1.5V_RUN C345
VTT5 VCC3G0

22n_0805_25V

0.1U_0402_16V4Z~D
220U_V_4VM_R45~D

10U_0805_4VAM~D

10U_0805_4VAM~D
P14 AJ41 0.1U_0402_16V4Z~D 1
VTT6 VCC3G1 2 3

C599
N14 L41 1 L35 1
VTT7 VCC3G2

C35

C22
CRB 270uF M14 VTT8 VCC3G3 N41 1 1

C49

C53

C59
L14 R41 +
VTT9 VCC3G4 2
AD13 VTT10 VCC3G5 V41
2
AC13 VTT11 VCC3G6 Y41
2 2 2 Route +2.5VRUN from GMCH pinG41 to
220U_V_4VM_R45~D

AB13 VTT12
D 1 AA13 VTT13 VCCA_3GPLL AC33 +1.5VRUN_3GPLL decoupling cap (C345)<200mil to the edge. D
Y13 G41
VTT14 VCCA_3GBG +2.5V_RUN
C411

+ W13 H41
VTT15 VSSA_3GBG
V13 VTT16
U13 L37 BLM18PG181SN1_0603~D +3VRUN_TVDACB
2 VTT17 +2.5V_CRTDAC
T13 VTT18 VCCA_CRTDAC0 E21 1 2 +2.5V_RUN

0.1U_0402_16V4Z~D
0.022U_0402_16V7K~D
R13 VTT19 VCCA_CRTDAC1 F21 1 2

0.1U_0402_16V4Z~D
N13 VTT20 VSSA_CRTDAC2 G21 1 1

C357

22n_0805_25V
M13 VTT21 3

C364
L13 +2.5V_RUN 1
VTT22

C306
AB12 VTT23 VCCA_DPLLA B26 +1.5VRUN_DPLLA 2 2 CRTDAC: Route caps within

C299
AA12 VTT24 VCCA_DPLLB C39 +1.5VRUN_DPLLB

2
Y12 VTT25 VCCA_HPLL AF1 +1.5VRUN_HPLL 250mil of Alviso. Route FB
2

0.1U_0402_16V4Z~D

0.01U_0402_16V7K~D
W12 R92
VTT26 within 3" of Calistoga
V12 VTT27 0_0603_5%~D
U12 VTT28 VCCA_LVDS A38 +2.5V_RUN 1 1

C323
T12 B39

1
+3VRUN_ATV
VTT29 VSSA_LVDS

C318
R12 VTT30
P12 VTT31 2 2 +3VRUN_ATVBG
N12 AF2
M12
VTT32
VTT33
P O W E R VCCA_MPLL +1.5VRUN_MPLL
+3VRUN_ATVBG Route VSSACRTDAC gnd from GMCH to +3VRUN_TVDACC
4.7U_0603_6.3V4Z~D

2.2U_0603_6.3V6K~D

L12 VTT34 VCCA_TVBG H20


R11 VTT35 VSSA_TVBG G20 VSSA_TVBG decoupling cap ground lead and then 1 2
1 1 P11 VTT36 connect to the gnd plane. 1 2

C36
C391

C390

0.1U_0402_16V4Z~D

4.7U_0603_6.3V4Z~D

0.1U_0402_16V4Z~D
N11 VTT37 3

22n_0805_25V
M11 VTT38 VCCA_TVDACA0 E19 +3VRUN_TVDACA 1
3

@ C598

22n_0805_25V
2 2
R10 VTT39 VCCA_TVDACA1 F19 Route VSSA_TVBG GND from GMCH to close pin A38 1 1

C305
P10 VTT40 VCCA_TVDACB0 C20 +3VRUN_TVDACB
decoupling cap ground lead and then

C23
C298
N10 VTT41 VCCA_TVDACB1 D20
2 C35, C305, C306 replace by 0
M10 VTT42 VCCA_TVDACC0 E20 +3VRUN_TVDACC connect to the GND plane.
P9 VTT43 VCCA_TVDACC1 F20 2 2 ohm 0805 resistor
N9 VTT44
M9 VTT45
R8 AH1 +1.5V_RUN VSSA_TVBG
VTT46 VCCD_HMPLL0
C
P8 VTT47 VCCD_HMPLL1 AH2 C
N8 +1.5V_RUN
VTT48
M8 VTT49
P7 A28 +2.5V_RUN
VTT50 VCCD_LVDS0
N7 VTT51 VCCD_LVDS1 B28

0.01U_0402_16V7K~D
M7 VTT52 VCCD_LVDS2 C28

10U_0805_4VAM~D

4.7U_0603_6.3V4Z~D

0.1U_0402_16V4Z~D
R6 VTT53
P6 VTT54 VCCD_TVDAC D21 +1.5V_RUN_TVDAC 1 1

C310
0.47U_0402_16V4Z~D

M6 VTT55 VCCDQ_TVDAC H19 +1.5VRUN_QTVDAC 1 1

C325

C314

C324
U40_A6 A6 VTT56
R5 VTT57 VCCHV0 A23 +3.3V_RUN_R 2 2 +1.5VRUN_QTVDAC +1.5V_RUN +1.5V_RUN_TVDAC
0.1U_0402_16V4Z~D

P5 B23 L11
VTT58 VCCHV1 2 2 +1.5V_RUN
10U_0805_4VAM~D

1 N5 B25 BLM18PG181SN1_0603~D
VTT59 VCCHV2
C316

M5 VTT60 1 1 2 1
C336

C385

P4 VTT61 VCCAUX0 AK31

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D
0.022U_0402_16V7K~D

0.022U_0402_16V7K~D
N4 VTT62 VCCAUX1 AF31
2 M4 AE31
VTT63 VCCAUX2 2 2 1 1 1 1
R3 VTT64 VCCAUX3 AC31 close pin B30/C30/A30

C37

C24

C304

C297
P3 VTT65 VCCAUX4 AL30
N3 VTT66 VCCAUX5 AK30
2 2 2 2
M3 VTT67 VCCAUX6 AJ30
+1.5V_RUN
0.22U_0402_10V4Z~D

R2 VTT68 VCCAUX7 AH30


P2 VTT69 VCCAUX8 AG30
1 M2 VTT70 VCCAUX9 AF30
C118

U40_D2 D2 AE30
VTT71 VCCAUX10
AB1 VTT72 VCCAUX11 AD30 1
0.22U_0402_10V4Z~D

0.1U_0402_16V4Z~D

R1 VTT73 VCCAUX12 AC30


2
C437
U40_AB1

1 P1 VTT74 VCCAUX13 AG29


C164

N1 VTT75 VCCAUX14 AF29


2
M1 VTT76 VCCAUX15 AE29
0.47U_0402_16V4Z~D

VCCAUX16 AD29
2 AC29
1 VCCAUX17
C435

VCCAUX18 AG28
AF28 +1.5VRUN_HPLL +1.5VRUN_MPLL
VCCAUX19 L39 L38
VCCAUX20 AE28
2
B
VCCAUX21 AH22 45mA Max. 2 1 +1.5V_RUN 45mA Max. 2 1 +1.5V_RUN B
AJ21 BLM18AG121SN1D_0603~D BLM18AG121SN1D_0603~D
VCCAUX22

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D
AG14 VCCAUX32 VCCAUX23 AH21
AF14 VCCAUX33 VCCAUX24 AJ20
AE14 VCCAUX34 VCCAUX25 AH20 1 1 1 1

C413

C418
Y14 VCCAUX35 VCCAUX26 AH19
AF13 P19 Should be placed in cavity C94 C419
VCCAUX36 VCCAUX27 22U_0805_6.3VAM~D 22U_0805_6.3VAM~D
AE13 VCCAUX37 VCCAUX28 P16
+1.5V_RUN 2 2 2 2
AF12 VCCAUX38 VCCAUX29 AH15
AE12 P15 +1.5V_RUN
VCCAUX39 VCCAUX30 +1.5VRUN_3GPLL R267 L34
AD12 VCCAUX40 VCCAUX31 AH14
0.5_0805_1%~D BLM18PG181SN1_0603~D
1 2+3GPLL_R 2 1
0.1U_0402_16V4Z~D

10U_0805_4VAM~D

0.1U_0402_16V4Z~D

CALISTOGA A0_FCBGA1466~D

1 1 1
+1.5VRUN_DPLLA +1.5VRUN_DPLLB
C332
C404

C311

L28 L33
10U_MLZ2012E100PTAIN_60mA_25%_0805~D 10U_MLZ2012E100PTAIN_60mA_25%_0805~D
2 2 2
40mA Max. 2 1 +1.5V_RUN 40mA Max. 2 1 +1.5V_RUN
0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D
470U_D2_2.5VM~D
1 1

470U_D2_2.5VM~D
1 1
C294

C331

C335
+ +
C322

2 2 2 2

+1.5V_RUN
+1.05V_VCCP

2 +3.3V_RUN_R
2 +2.5V_RUN

A
1 1 2 A
1 1 2 R12
R320 3 10_0402_5%~D
3 10_0402_5%~D
D8
D14 MMBD4148_SOT23~D
MMBD4148_SOT23~D DELL CONFIDENTIAL/PROPRIETARY
CRT DAC Voltge Follower Circuit - 700mV TV DAC Voltge Follower Circuit - 700mV
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL Title
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, Calistoga(4 of 6)
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD Size Document Number Re v
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. 0.6
LA-2791
Date: Tuesday, February 07, 2006 Sheet 13 of 63
5 4 3 2 1
5 4 3 2 1

+1.05V_VCCP U40G +1.8V_SUS

AA33 VCC0 VCC_SM0 AU41


+1.5V_RUN W33 AT41 VCCSM_LF4
VCC1 VCC_SM1 VCCSM_LF5
P33 VCC2 VCC_SM2 AM41
+1.05V_VCCP N33 AU40
U40F VCC3 VCC_SM3

0.47U_0402_16V4Z~D

0.47U_0402_16V4Z~D
L33 VCC4 VCC_SM4 BA34
J33 VCC5 VCC_SM5 AY34
AD27 VCC_NCTF0 VCCAUX_NCTF0 AG27 AA32 VCC6 VCC_SM6 AW34 1 1

C615
AC27 VCC_NCTF1 VCCAUX_NCTF1 AF27 Y32 VCC7 VCC_SM7 AV34

C612
D D
AB27 VCC_NCTF2 VCCAUX_NCTF2 AG26 W32 VCC8 VCC_SM8 AU34
AA27 VCC_NCTF3 VCCAUX_NCTF3 AF26 V32 VCC9 VCC_SM9 AT34
2 2
Y27 VCC_NCTF4 VCCAUX_NCTF4 AG25 P32 VCC10 VCC_SM10 AR34
W27 VCC_NCTF5 VCCAUX_NCTF5 AF25 N32 VCC11 VCC_SM11 BA30
V27 VCC_NCTF6 VCCAUX_NCTF6 AG24 M32 VCC12 VCC_SM12 AY30
U27 VCC_NCTF7 VCCAUX_NCTF7 AF24 L32 VCC13 VCC_SM13 AW30
T27 VCC_NCTF8 VCCAUX_NCTF8 AG23 J32 VCC14 VCC_SM14 AV30
0.22U_0402_10V4Z~D

0.22U_0402_10V4Z~D

0.22U_0402_10V4Z~D

R27 VCC_NCTF9 VCCAUX_NCTF9 AF23 AA31 VCC15 VCC_SM15 AU30


AD26 VCC_NCTF10 VCCAUX_NCTF10 AG22 W31 VCC16 VCC_SM16 AT30
1 1 1 AC26 VCC_NCTF11 VCCAUX_NCTF11 AF22 V31 VCC17 VCC_SM17 AR30 Place near U40.AT41 & AM41
C379

C358

C383

AB26 VCC_NCTF12 VCCAUX_NCTF12 AG21 T31 VCC18 VCC_SM18 AP30


AA26 VCC_NCTF13 VCCAUX_NCTF13 AF21 R31 VCC19 VCC_SM19 AN30
Y26 VCC_NCTF14 VCCAUX_NCTF14 AG20 P31 VCC20 VCC_SM20 AM30
2 2 2
W26 VCC_NCTF15 VCCAUX_NCTF15 AF20 N31 VCC21 VCC_SM21 AM29
V26 VCC_NCTF16 VCCAUX_NCTF16 AG19 M31 VCC22 VCC_SM22 AL29
U26 VCC_NCTF17 VCCAUX_NCTF17 AF19 AA30 VCC23 VCC_SM23 AK29
T26 VCC_NCTF18 VCCAUX_NCTF18 R19 Y30 VCC24 VCC_SM24 AJ29
R26 VCC_NCTF19 VCCAUX_NCTF19 AG18 W30 VCC25 VCC_SM25 AH29

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D
AD25 VCC_NCTF20 VCCAUX_NCTF20 AF18 V30 VCC26 VCC_SM26 AJ28
AC25 VCC_NCTF21 VCCAUX_NCTF21 R18 U30 VCC27 VCC_SM27 AH28
AB25 VCC_NCTF22 VCCAUX_NCTF22 AG17 T30 VCC28 VCC_SM28 AJ27 1 1 1 1

C438

C441

C444

C452
AA25 VCC_NCTF23 VCCAUX_NCTF23 AF17 R30 VCC29 VCC_SM29 AH27
Y25 VCC_NCTF24 VCCAUX_NCTF24 AE17 P30 VCC30 VCC_SM30 BA26
W25 VCC_NCTF25 VCCAUX_NCTF25 AD17 N30 VCC31 VCC_SM31 AY26
2 2 2 2
V25 AB17 M30 AW26
U25
VCC_NCTF26
VCC_NCTF27
VCCAUX_NCTF26
VCCAUX_NCTF27 AA17 L30
VCC32
VCC33
P O W E R VCC_SM32
VCC_SM33 AV26
1U_0603_10V4Z~D
10U_0805_4VAM~D

10U_0805_4VAM~D

T25 W17 AA29 AU26


P O W E R
VCC_NCTF28 VCCAUX_NCTF28 VCC34 VCC_SM34
R25 VCC_NCTF29 VCCAUX_NCTF29 V17 Y29 VCC35 VCC_SM35 AT26
1 1 1 AD24 VCC_NCTF30 VCCAUX_NCTF30 T17 W29 VCC36 VCC_SM36 AR26
C366

C367

C368

AC24 VCC_NCTF31 VCCAUX_NCTF31 R17 V29 VCC37 VCC_SM37 AJ26


AB24 VCC_NCTF32 VCCAUX_NCTF32 AG16 U29 VCC38 VCC_SM38 AH26
AA24 VCC_NCTF33 VCCAUX_NCTF33 AF16 R29 VCC39 VCC_SM39 AJ25
C 2 2 2 C
Y24 VCC_NCTF34 VCCAUX_NCTF34 AE16 P29 VCC40 VCC_SM40 AH25
W24 VCC_NCTF35 VCCAUX_NCTF35 AD16 M29 VCC41 VCC_SM41 AJ24
V24 VCC_NCTF36 VCCAUX_NCTF36 AC16 L29 VCC42 VCC_SM42 AH24
U24 VCC_NCTF37 VCCAUX_NCTF37 AB16 AB28 VCC43 VCC_SM43 BA23
T24 VCC_NCTF38 VCCAUX_NCTF38 AA16 AA28 VCC44 VCC_SM44 AJ23

0.47U_0402_16V4Z~D
R24 VCC_NCTF39 VCCAUX_NCTF39 Y16 Y28 VCC45 VCC_SM45 BA22
AD23 VCC_NCTF40 VCCAUX_NCTF40 W16 V28 VCC46 VCC_SM46 AY22
V23 VCC_NCTF41 VCCAUX_NCTF41 V16 U28 VCC47 VCC_SM47 AW22 1
U23 VCC_NCTF42 VCCAUX_NCTF42 U16 T28 VCC48 VCC_SM48 AV22

C616
T23 VCC_NCTF43 VCCAUX_NCTF43 T16 R28 VCC49 VCC_SM49 AU22
R23 VCC_NCTF44 VCCAUX_NCTF44 R16 P28 VCC50 VCC_SM50 AT22
2
AD22 VCC_NCTF45 VCCAUX_NCTF45 AG15 N28 VCC51 VCC_SM51 AR22
220U_V_4VM_R45~D

V22 VCC_NCTF46 VCCAUX_NCTF46 AF15 M28 VCC52 VCC_SM52 AP22


1 U22 VCC_NCTF47 VCCAUX_NCTF47 AE15 L28 VCC53 VCC_SM53 AK22
T22 VCC_NCTF48 VCCAUX_NCTF48 AD15 P27 VCC54 VCC_SM54 AJ22
C423

+ R22 AC15 N27 AK21


VCC_NCTF49 VCCAUX_NCTF49 VCC55 VCC_SM55
AD21 VCC_NCTF50 VCCAUX_NCTF50 AB15 M27 VCC56 VCC_SM56 AK20 Place near U40.BA23
V21 VCC_NCTF51 VCCAUX_NCTF51 AA15 L27 VCC57 VCC_SM57 BA19
2
U21 VCC_NCTF52 VCCAUX_NCTF52 Y15 P26 VCC58 VCC_SM58 AY19

330U_D2E_2.5VM_R9~D
10U_0805_4VAM~D

10U_0805_4VAM~D
T21 VCC_NCTF53 VCCAUX_NCTF53 W15 N26 VCC59 VCC_SM59 AW19
R21 VCC_NCTF54 VCCAUX_NCTF54 V15 L26 VCC60 VCC_SM60 AV19 1
AD20 VCC_NCTF55 VCCAUX_NCTF55 U15 N25 VCC61 VCC_SM61 AU19 1 1
V20 T15 M25 AT19 +
VCC_NCTF56 VCCAUX_NCTF56 VCC62 VCC_SM62

C160

C158

@ C165
CRB 270uF U20
T20
VCC_NCTF57 VCCAUX_NCTF57 R15 L25
P24
VCC63 VCC_SM63 AR19
AP19
VCC_NCTF58 VCC64 VCC_SM64 2 2 2
R20 VCC_NCTF59 N24 VCC65 VCC_SM65 AK19
AD19 VCC_NCTF60 VSS_NCTF0 AE27 M24 VCC66 VCC_SM66 AJ19
V19 VCC_NCTF61 VSS_NCTF1 AE26 AB23 VCC67 VCC_SM67 AJ18
U19 VCC_NCTF62 VSS_NCTF2 AE25 AA23 VCC68 VCC_SM68 AJ17
220U_V_4VM_R45~D

T19 VCC_NCTF63 VSS_NCTF3 AE24 Y23 VCC69 VCC_SM69 AH17


1 AD18 VCC_NCTF64 VSS_NCTF4 AE23 P23 VCC70 VCC_SM70 AJ16
AC18 VCC_NCTF65 VSS_NCTF5 AE22 N23 VCC71 VCC_SM71 AH16
C620

B + AB18 AE21 M23 BA15 B


VCC_NCTF66 VSS_NCTF6 VCC72 VCC_SM72
AA18 VCC_NCTF67 VSS_NCTF7 AE20 L23 VCC73 VCC_SM73 AY15

0.47U_0402_16V4Z~D
Y18 VCC_NCTF68 VSS_NCTF8 AE19 AC22 VCC74 VCC_SM74 AW15
2
W18 VCC_NCTF69 VSS_NCTF9 AE18 AB22 VCC75 VCC_SM75 AV15
V18 VCC_NCTF70 VSS_NCTF10 AC17 Y22 VCC76 VCC_SM76 AU15 1
U18 VCC_NCTF71 VSS_NCTF11 Y17 W22 VCC77 VCC_SM77 AT15

C617
T18 VCC_NCTF72 VSS_NCTF12 U17 P22 VCC78 VCC_SM78 AR15
N22 VCC79 VCC_SM79 AJ15
+1.05V_VCCP 2
M22 VCC80 VCC_SM80 AJ14
M19 +1.8V_SUS L22 AJ13
VCC100 VCC81 VCC_SM81
L19 VCC101 VCC_SM100 AR6 AC21 VCC82 VCC_SM82 AH13
N18 VCC102 VCC_SM101 AP6 AA21 VCC83 VCC_SM83 AK12
M18 VCC103 VCC_SM102 AN6 W21 VCC84 VCC_SM84 AJ12
L18 VCC104 VCC_SM103 AL6 N21 VCC85 VCC_SM85 AH12
P17 VCC105 VCC_SM104 AK6 M21 VCC86 VCC_SM86 AG12
N17 VCC106 VCC_SM105 AJ6 L21 VCC87 VCC_SM87 AK11
M17 VCC107 VCC_SM106 AV1 VCCSM_LF2 AC20 VCC88 VCC_SM88 BA8 Place near U40.BA15
N16 VCC108 VCC_SM107 AJ1 VCCSM_LF1 AB20 VCC89 VCC_SM89 AY8
M16 VCC109 Y20 VCC90 VCC_SM90 AW8
0.47U_0402_16V4Z~D

0.47U_0402_16V4Z~D

L16 VCC110 W20 VCC91 VCC_SM91 AV8


P20 VCC92 VCC_SM92 AT8
1 1 N20 VCC93 VCC_SM93 AR8
CALISTOGA A0_FCBGA1466~D M20 AP8
VCC94 VCC_SM94
C613

C614

L20 VCC95 VCC_SM95 BA6


AB19 VCC96 VCC_SM96 AY6
2 2
AA19 VCC97 VCC_SM97 AW6
Y19 VCC98 VCC_SM98 AV6
N19 VCC99 VCC_SM99 AT6

CALISTOGA A0_FCBGA1466~D

A
Place near U40.AV1 & AJ1 A

DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL Title
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, Calistoga(5 of 6)
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD Size Document Number Rev
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. 0.6
LA-2791
Date: Tuesday, February 07, 2006 Sheet 14 of 63
5 4 3 2 1
5 4 3 2 1

U40I
U40J
AC41 VSS0 VSS100 AE34
AA41 VSS1 VSS101 AC34 AN21 VSS200 VSS280 AG10
W41 VSS2 VSS102 C34 AL21 VSS201 VSS281 AC10
T41 VSS3 VSS103 AW33 AB21 VSS202 VSS282 W10
P41 VSS4 VSS104 AV33 Y21 VSS203 VSS283 U10
D D
M41 VSS5 VSS105 AR33 P21 VSS204 VSS284 BA9
J41 VSS6 VSS106 AE33 K21 VSS205 VSS285 AW9
F41 VSS7 VSS107 AB33 J21 VSS206 VSS286 AR9
AV40 VSS8 VSS108 Y33 H21 VSS207 VSS287 AH9
AP40 VSS9 VSS109 V33 C21 VSS208 VSS288 AB9
AN40 VSS10 VSS110 T33 AW20 VSS209 VSS289 Y9
AK40 VSS11 VSS111 R33 AR20 VSS210 VSS290 R9
AJ40 VSS12 VSS112 M33 AM20 VSS211 VSS292 G9
AH40 VSS13 VSS113 H33 AA20 VSS212 VSS291 E9
AG40 VSS14 VSS114 G33 K20 VSS213 VSS293 A9
AF40 VSS15 VSS115 F33 B20 VSS214 VSS294 AG8
AE40 VSS16 VSS116 D33 A20 VSS215 VSS295 AD8
B40 VSS17 VSS117 B33 AN19 VSS216 VSS296 AA8
AY39 VSS18 VSS118 AH32 AC19 VSS217 VSS297 U8
AW39 VSS19 VSS119 AG32 W19 VSS218 VSS298 K8
AV39 VSS20 VSS120 AF32 K19 VSS219 VSS299 C8
AR39 VSS21 VSS121 AE32 G19 VSS220 VSS300 BA7
AN39 VSS22 VSS122 AC32 C19 VSS221 VSS301 AV7
AJ39 VSS23 VSS123 AB32 AH18 VSS222 VSS302 AP7
AC39 VSS24 VSS124 G32 P18 VSS223 VSS303 AL7
AB39 VSS25 VSS125 B32 H18 VSS224 VSS304 AJ7
AA39 VSS26 VSS126 AY31 D18 VSS225 VSS305 AH7
Y39 VSS27 VSS127 AV31 A18 VSS226 VSS306 AF7
W39 VSS28 VSS128 AN31 AY17 VSS227 VSS307 AC7
V39 VSS29 VSS129 AJ31 AR17 VSS228 VSS308 R7
T39 AG31 AP17 G7
R39
VSS30
VSS31
VSS130
VSS131 AB31 AM17
VSS229
VSS230
P O W E R VSS309
VSS310 D7
P39 VSS32 VSS132 Y31 AK17 VSS231 VSS311 AG6
N39 VSS33 VSS133 AB30 AV16 VSS232 VSS312 AD6
M39 E30 AN16 AB6
L39
VSS34
VSS35
P O W E R VSS134
VSS135 AT29 AL16
VSS233
VSS234
VSS313
VSS314 Y6
J39 VSS36 VSS136 AN29 J16 VSS235 VSS315 U6
C C
H39 VSS37 VSS137 AB29 F16 VSS236 VSS316 N6
G39 VSS38 VSS138 T29 C16 VSS237 VSS317 K6
F39 VSS39 VSS139 N29 AN15 VSS238 VSS318 H6
D39 VSS40 VSS140 K29 AM15 VSS239 VSS319 B6
AT38 VSS41 VSS141 G29 AK15 VSS240 VSS320 AV5
AM38 VSS42 VSS142 E29 N15 VSS241 VSS321 AF5
AH38 VSS43 VSS143 C29 M15 VSS242 VSS322 AD5
AG38 VSS44 VSS144 B29 L15 VSS243 VSS323 AY4
AF38 VSS45 VSS145 A29 B15 VSS244 VSS324 AR4
AE38 VSS46 VSS146 BA28 A15 VSS245 VSS325 AP4
C38 VSS47 VSS147 AW28 BA14 VSS246 VSS326 AL4
AK37 VSS48 VSS148 AU28 AT14 VSS247 VSS327 AJ4
AH37 VSS49 VSS149 AP28 AK14 VSS248 VSS328 Y4
AB37 VSS50 VSS150 AM28 AD14 VSS249 VSS329 U4
AA37 VSS51 VSS151 AD28 AA14 VSS250 VSS330 R4
Y37 VSS52 VSS152 AC28 U14 VSS251 VSS331 J4
W37 VSS53 VSS153 W28 K14 VSS252 VSS332 F4
V37 VSS54 VSS154 J28 H14 VSS253 VSS333 C4
T37 VSS55 VSS155 E28 E14 VSS254 VSS334 AY3
R37 VSS56 VSS156 AP27 AV13 VSS255 VSS335 AW3
P37 VSS57 VSS157 AM27 AR13 VSS256 VSS336 AV3
N37 VSS58 VSS158 AK27 AN13 VSS257 VSS337 AL3
M37 VSS59 VSS159 J27 AM13 VSS258 VSS338 AH3
L37 VSS60 VSS160 G27 AL13 VSS259 VSS339 AG3
J37 VSS61 VSS161 F27 AG13 VSS260 VSS340 AF3
H37 VSS62 VSS162 C27 P13 VSS261 VSS341 AD3
G37 VSS63 VSS163 B27 F13 VSS262 VSS342 AC3
F37 VSS64 VSS164 AN26 D13 VSS265 VSS343 AA3
D37 VSS65 VSS165 M26 B13 VSS264 VSS344 G3
AY36 VSS66 VSS166 K26 AY12 VSS263 VSS345 AT2
AW36 VSS67 VSS167 F26 AC12 VSS266 VSS346 AR2
AN36 VSS68 VSS168 D26 K12 VSS267 VSS347 AP2
B B
AH36 VSS69 VSS169 AK25 H12 VSS268 VSS348 AK2
AG36 VSS70 VSS170 P25 E12 VSS269 VSS349 AJ2
AF36 VSS71 VSS171 K25 AD11 VSS270 VSS350 AD2
AE36 VSS72 VSS172 H25 AA11 VSS271 VSS351 AB2
AC36 VSS73 VSS173 E25 Y11 VSS272 VSS352 Y2
C36 VSS74 VSS174 D25 J11 VSS273 VSS353 U2
B36 VSS75 VSS175 A25 D11 VSS274 VSS354 T2
BA35 VSS76 VSS176 BA24 B11 VSS275 VSS355 N2
AV35 VSS77 VSS177 AU24 AV10 VSS276 VSS356 J2
AR35 VSS78 VSS178 AL24 AP10 VSS277 VSS357 H2
AH35 VSS79 VSS179 AW23 AL10 VSS278 VSS358 F2
AB35 VSS80 VSS180 AT23 AJ10 VSS279 VSS359 C2
AA35 VSS81 VSS181 AN23 VSS360 AL1
Y35 VSS82 VSS182 AM23
W35 AH23 CALISTOGA A0_FCBGA1466~D
VSS83 VSS183
V35 VSS84 VSS184 AC23
T35 VSS85 VSS185 W23
R35 VSS86 VSS186 K23
P35 VSS87 VSS187 J23
N35 VSS88 VSS188 F23
M35 VSS89 VSS189 C23
L35 VSS90 VSS190 AA22
J35 VSS91 VSS191 K22
H35 VSS92 VSS192 G22
G35 VSS93 VSS193 F22
F35 VSS94 VSS194 E22
D35 VSS95 VSS195 D22
AN34 VSS96 VSS196 A22
AK34 VSS97 VSS197 BA21
AG34 VSS98 VSS198 AV21
AF34 VSS99 VSS199 AR21
A CALISTOGA A0_FCBGA1466~D A

DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL Title
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, Calistoga(6 of 6)
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD Size Document Number Rev
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. 0.6
LA-2791
Date: Tuesday, February 07, 2006 Sheet 15 of 63
5 4 3 2 1
5 4 3 2 1

+1.8V_SUS +1.8V_SUS
11 DDR_A_DQS#[0..7] ON TOP SIDE V_DDR_MCH_REF
V_DDR_MCH_REF 10,17,48
11 DDR_A_D[0..63]

2.2U_0603_6.3V6K~D

0.1U_0402_16V4Z~D
JDIM2
11 DDR_A_DM[0..7] 1 VREF VSS 2

1
3 4 DDR_A_D7 1 1
DDR_A_D0 VSS DQ4 DDR_A_D4 R51
11 DDR_A_DQS[0..7] Layout Note: 5 DQ0 DQ5 6

C226

C224
DDR_A_D1 7 8 100K_0402_5%~D
Place near JDIM1 9
DQ1 VSS
10 DDR_A_DM0
11 DDR_A_MA[0..13] VSS DM0 2 2
DDR_A_DQS#0 11 12

2
DDR_A_DQS0 DQS0# VSS DDR_A_D6
13 DQS0 DQ6 14
15 16 DDR_A_D5
DDR_A_D3 VSS DQ7
17 DQ2 VSS 18
D DDR_A_D2 DDR_A_D13 D
19 DQ3 DQ12 20
21 22 DDR_A_D12
DDR_A_D14 VSS DQ13
23 DQ8 VSS 24
+1.8V_SUS DDR_A_D8 25 26 DDR_A_DM1
DQ9 DM1
27 VSS VSS 28
DDR_A_DQS#1 29 30 M_CLK_DDR0
DQS1# CK0 M_CLK_DDR0 10
DDR_A_DQS1 31 32 M_CLK_DDR#0
DQS1 CK0# M_CLK_DDR#0 10
2.2U_0603_6.3V6K~D

2.2U_0603_6.3V6K~D

2.2U_0603_6.3V6K~D

2.2U_0603_6.3V6K~D

2.2U_0603_6.3V6K~D
33 VSS VSS 34
1 1 1 1 1 DDR_A_D11 35 36 DDR_A_D15
DQ10 DQ14
C213

C214

C222

C225

C229
DDR_A_D10 37 38 DDR_A_D9
DQ11 DQ15
39 VSS VSS 40
2 2 2 2 2
41 VSS VSS 42
DDR_A_D20 43 44 DDR_A_D16
DDR_A_D17 DQ16 DQ20 DDR_A_D21
45 DQ17 DQ21 46 PM_EXTTS#0_R 17
47 VSS VSS 48
DDR_A_DQS#2 49 50 PM_EXTTS#0_R 1 2 PM_EXTTS#0 10
DDR_A_DQS2 DQS2# NC DDR_A_DM2 R177
51 DQS2 DM2 52
0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D

53 54 0_0402_5%~D
DDR_A_D22 VSS VSS DDR_A_D18
1 1 1 1 55 DQ18 DQ22 56
C212

C215

C223

C227
DDR_A_D23 57 58 DDR_A_D19
DQ19 DQ23
59 VSS VSS 60
DDR_A_D24 61 62 DDR_A_D28
2 2 2 2 DDR_A_D29 DQ24 DQ28 DDR_A_D25
63 DQ25 DQ29 64
65 VSS VSS 66
DDR_A_DM3 67 68 DDR_A_DQS#3
DM3 DQS3# DDR_A_DQS3
69 NC DQS3 70
71 VSS VSS 72
DDR_A_D31 73 74 DDR_A_D26
DDR_A_D27 DQ26 DQ30 DDR_A_D30
75 DQ27 DQ31 76
77 VSS VSS 78
C DDR_CKE0_DIMMA DDR_CKE1_DIMMA C
10 DDR_CKE0_DIMMA 79 CKE0 NC/CKE1 80 DDR_CKE1_DIMMA 10
81 VDD VDD 82
83 NC NC/A15 84
DDR_A_BS2 85 86
11 DDR_A_BS2 BA2 NC/A14
87 VDD VDD 88
DDR_A_MA12 89 90 DDR_A_MA11
DDR_A_MA9 A12 A11 DDR_A_MA7
Layout Note: 91 A9 A7 92
DDR_A_MA8 93 94 DDR_A_MA6
Place one cap close to every 2 pullup 95
A8 A6
96
DDR_A_MA5 VDD VDD DDR_A_MA4
resistors terminated to +0.9V_DDR_VTT 97 A5 A4 98
DDR_A_MA3 99 100 DDR_A_MA2
DDR_A_MA1 A3 A2 DDR_A_MA0
101 A1 A0 102
103 VDD VDD 104
DDR_A_MA10 105 106 DDR_A_BS1 DDR_A_BS1 11
DDR_A_BS0 A10/AP BA1 DDR_A_RAS#
11 DDR_A_BS0 107 BA0 RAS# 108 DDR_A_RAS# 11
DDR_A_WE# 109 110 DDR_CS0_DIMMA#
11 DDR_A_WE# WE# S0# DDR_CS0_DIMMA# 10
111 VDD VDD 112
DDR_A_CAS# 113 114 M_ODT0
11 DDR_A_CAS# CAS# ODT0 M_ODT0 10
+0.9V_DDR_VTT DDR_CS1_DIMMA# 115 116 DDR_A_MA13
10 DDR_CS1_DIMMA# NC/S1# NC/A13
117 VDD VDD 118
M_ODT1 119 120
10 M_ODT1 NC/ODT1 NC
121 VSS VSS 122
DDR_A_D35 123 124 DDR_A_D36
DDR_A_D32 DQ32 DQ36 DDR_A_D37
125 DQ33 DQ37 126
0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D

127 VSS VSS 128


DDR_A_DQS#4 129 130 DDR_A_DM4
DDR_A_DQS4 DQS4# DM4
1 1 1 1 1 1 1 1 1 1 1 1 1 131 DQS4 VSS 132
133 134 DDR_A_D39
DDR_A_D34 VSS DQ38 DDR_A_D38
135 DQ34 DQ39 136
DDR_A_D33 137 138
2 2 2 2 2 2 2 2 2 2 2 2 2 DQ35 VSS DDR_A_D44
139 VSS DQ44 140
C221

C220

C219

C218

C217

C216

C231

C232

C233

C235

C237

C236

C234

DDR_A_D43 141 142 DDR_A_D40


B DDR_A_D45 DQ40 DQ45 B
143 DQ41 VSS 144
145 146 DDR_A_DQS#5
DDR_A_DM5 VSS DQS5# DDR_A_DQS5
147 DM5 DQS5 148
149 VSS VSS 150
DDR_A_D46 151 152 DDR_A_D41
DDR_A_D47 DQ42 DQ46 DDR_A_D42
153 DQ43 DQ47 154
155 VSS VSS 156
DDR_A_D48 157 158 DDR_A_D49
DDR_A_D52 DQ48 DQ52 DDR_A_D53
159 DQ49 DQ53 160
161 VSS VSS 162
163 164 M_CLK_DDR1
NC,TEST CK1 M_CLK_DDR1 10
+0.9V_DDR_VTT 165 166 M_CLK_DDR#1
VSS CK1# M_CLK_DDR#1 10
DDR_A_DQS#6 167 168
DDR_A_DQS6 DQS6# VSS DDR_A_DM6
RN25 RN27 169 170
DDR_A_MA1 DQS6 DM6
1 4 4 1 DDR_A_MA9 171 VSS VSS 172
DDR_A_MA3 2 3 3 2 DDR_A_MA12 DDR_A_D55 173 174 DDR_A_D50
56_0404_4P2R_5%~D 56_0404_4P2R_5%~D DDR_A_D51 DQ50 DQ54 DDR_A_D54
175 DQ51 DQ55 176
RN24 RN19 Layout Note: 177 VSS VSS 178
DDR_A_BS0 1 4 4 1 DDR_A_MA7 Place these resistor DDR_A_D60 179 180 DDR_A_D57
DDR_A_MA10 DQ56 DQ60
2 3 3 2 DDR_A_MA6 closely DIMM0,all DDR_A_D61 181 DQ57 DQ61 182 DDR_A_D56
56_0404_4P2R_5%~D 56_0404_4P2R_5%~D 183 184
RN16 RN26 trace length<750 mil DDR_A_DM7 VSS VSS DDR_A_DQS#7
185 DM7 DQS7# 186
DDR_A_RAS# 1 4 4 1 DDR_A_MA5 187 188 DDR_A_DQS7
DDR_CS0_DIMMA# 2 VSS DQS7
3 3 2 DDR_A_MA8 DDR_A_D58 189 DQ58 VSS 190
56_0404_4P2R_5%~D 56_0404_4P2R_5%~D DDR_A_D59 191 192 DDR_A_D62
RN18 DQ59 DQ62 DDR_A_D63
RN23 193 194
DDR_A_CAS# VSS DQ63
1 4 4 1 DDR_A_MA4 6,17 CLK_SDATA
CLK_SDATA 195 SDA VSS 196
DDR_A_WE# 2 3 3 2 DDR_A_MA2 CLK_SCLK 197 198 R175 1 2 100K_0402_5%~D
6,17 CLK_SCLK SCL SAO
56_0404_4P2R_5%~D 56_0404_4P2R_5%~D +3.3V_RUN 199 200 R176 1 2 100K_0402_5%~D
RN17 VDDSPD SA1
RN22
0.1U_0402_16V4Z~D

M_ODT1 2.2U_0603_6.3V6K~D
1 4 4 1 DDR_A_MA0 201 GND GND 202
DDR_CS1_DIMMA# 2 3 3 2 DDR_A_BS1 1 1
C228

C230
A 56_0404_4P2R_5%~D 56_0404_4P2R_5%~D TYCO_1470815-2~D A
RN15
4 1 M_ODT0
2 2
DIMMA
3 2 DDR_A_MA13
56_0404_4P2R_5%~D RESERVE
RN20
DELL CONFIDENTIAL/PROPRIETARY
RN21 Layout Note:
DDR_CKE0_DIMMA 2 1 DDR_CKE1_DIMMA
DDR_A_BS2 1
3
4
4
3 2 DDR_A_MA11
Place these resistor
closely DIMM0,all
Compal Electronics, Inc.
56_0404_4P2R_5%~D 56_0404_4P2R_5%~D PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL Title
trace length TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
Max=1.3" BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, DDRII-SODIMM SLOT1
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD Size Document Number Rev
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. 0.6
LA-2791
Date: Tuesday, February 07, 2006 Sheet 16 of 63
5 4 3 2 1
5 4 3 2 1

+1.8V_SUS +1.8V_SUS
11 DDR_B_DQS#[0..7]
V_DDR_MCH_REF
11 DDR_B_D[0..63]
ON BOTTOM SIDE V_DDR_MCH_REF 10,16,48

2.2U_0603_6.3V6K~D

0.1U_0402_16V4Z~D
JDIM1
11 DDR_B_DM[0..7] Layout Note: 1 VREF VSS 2
3 4 DDR_B_D5 1 1
Place near JDIM2 DDR_B_D1 5
VSS DQ4
6 DDR_B_D4
11 DDR_B_DQS[0..7] DQ0 DQ5

C253

C252
DDR_B_D0 7 8
DQ1 VSS DDR_B_DM0
11 DDR_B_MA[0..13] 9 VSS DM0 10
DDR_B_DQS#0 2 2
11 DQS0# VSS 12
DDR_B_DQS0 13 14 DDR_B_D2
DQS0 DQ6 DDR_B_D3
15 VSS DQ7 16
DDR_B_D6 17 18
DDR_B_D7 DQ2 VSS DDR_B_D12
19 DQ3 DQ12 20
D +1.8V_SUS 21 22 DDR_B_D13 D
DDR_B_D8 VSS DQ13
23 DQ8 VSS 24
DDR_B_D9 25 26 DDR_B_DM1
DQ9 DM1
27 VSS VSS 28
2.2U_0603_6.3V6K~D

2.2U_0603_6.3V6K~D

2.2U_0603_6.3V6K~D

2.2U_0603_6.3V6K~D

2.2U_0603_6.3V6K~D
DDR_B_DQS#1 29 30 M_CLK_DDR3
DQS1# CK0 M_CLK_DDR3 10
1 1 1 1 1 DDR_B_DQS1 31 32 M_CLK_DDR#3
DQS1 CK0# M_CLK_DDR#3 10
C249

C254

C261

C242

C241
33 VSS VSS 34
DDR_B_D14 35 36 DDR_B_D10
DDR_B_D15 DQ10 DQ14 DDR_B_D11
37 DQ11 DQ15 38
2 2 2 2 2
39 VSS VSS 40

41 VSS VSS 42
DDR_B_D16 43 44 DDR_B_D17
DDR_B_D21 DQ16 DQ20 DDR_B_D20
45 DQ17 DQ21 46
47 VSS VSS 48
0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D
DDR_B_DQS#2 49 50 PM_EXTTS#0_R PM_EXTTS#0_R 16
DDR_B_DQS2 DQS2# NC DDR_B_DM2
1 1 1 1 51 DQS2 DM2 52
C240

C239

C251

C255
53 VSS VSS 54
DDR_B_D19 55 56 DDR_B_D22
DDR_B_D18 DQ18 DQ22 DDR_B_D23
57 DQ19 DQ23 58
2 2 2 2
59 VSS VSS 60
DDR_B_D26 61 62 DDR_B_D24
DDR_B_D28 DQ24 DQ28 DDR_B_D25
63 DQ25 DQ29 64
65 VSS VSS 66
DDR_B_DM3 67 68 DDR_B_DQS#3
DM3 DQS3# DDR_B_DQS3
69 NC DQS3 70
71 VSS VSS 72
DDR_B_D29 73 74 DDR_B_D30
DDR_B_D27 DQ26 DQ30 DDR_B_D31
75 DQ27 DQ31 76
77 VSS VSS 78
DDR_CKE2_DIMMB 79 80 DDR_CKE3_DIMMB
C 10 DDR_CKE2_DIMMB CKE0 NC/CKE1 DDR_CKE3_DIMMB 10 C
81 VDD VDD 82
83 NC NC/A15 84
Layout Note: DDR_B_BS2 85 86
11 DDR_B_BS2 BA2 NC/A14
87 88
Place one cap close to every 2 pullup DDR_B_MA12 89
VDD VDD
90 DDR_B_MA11
DDR_B_MA9 A12 A11 DDR_B_MA7
resistors terminated to +0.9V_DDR_VTT 91 A9 A7 92
DDR_B_MA8 93 94 DDR_B_MA6
A8 A6
95 VDD VDD 96
DDR_B_MA5 97 98 DDR_B_MA4
DDR_B_MA3 A5 A4 DDR_B_MA2
99 A3 A2 100
DDR_B_MA1 101 102 DDR_B_MA0
A1 A0
103 VDD VDD 104
DDR_B_MA10 105 106 DDR_B_BS1 DDR_B_BS1 11
DDR_B_BS0 A10/AP BA1 DDR_B_RAS#
11 DDR_B_BS0 107 BA0 RAS# 108 DDR_B_RAS# 11
+0.9V_DDR_VTT DDR_B_WE# 109 110 DDR_CS2_DIMMB#
11 DDR_B_WE# WE# S0# DDR_CS2_DIMMB# 10
111 VDD VDD 112
DDR_B_CAS# 113 114 M_ODT2
11 DDR_B_CAS# CAS# ODT0 M_ODT2 10
DDR_CS3_DIMMB# 115 116 DDR_B_MA13
10 DDR_CS3_DIMMB# NC/S1# NC/A13
117 VDD VDD 118
0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D

M_ODT3 119 120


10 M_ODT3 NC/ODT1 NC
121 VSS VSS 122
1 1 1 1 1 1 1 1 1 1 1 1 1 DDR_B_D33 123 124 DDR_B_D36
DDR_B_D32 DQ32 DQ36 DDR_B_D37
125 DQ33 DQ37 126
127 VSS VSS 128
DDR_B_DQS#4 129 130 DDR_B_DM4
2 2 2 2 2 2 2 2 2 2 2 2 2 DDR_B_DQS4 DQS4# DM4
131 DQS4 VSS 132
C248

C247

C246

C245

C244

C243

C269

C268

C267

C266

C265

C264

C263

133 134 DDR_B_D38


DDR_B_D35 VSS DQ38 DDR_B_D39
135 DQ34 DQ39 136
DDR_B_D34 137 138
DQ35 VSS DDR_B_D44
139 VSS DQ44 140
DDR_B_D41 141 142 DDR_B_D45
DDR_B_D40 DQ40 DQ45
143 DQ41 VSS 144
B DDR_B_DQS#5 B
145 VSS DQS5# 146
DDR_B_DM5 147 148 DDR_B_DQS5
DM5 DQS5
149 VSS VSS 150
DDR_B_D43 151 152 DDR_B_D42
DDR_B_D46 DQ42 DQ46 DDR_B_D47
153 DQ43 DQ47 154
155 VSS VSS 156
DDR_B_D49 157 158 DDR_B_D52
DDR_B_D48 DQ48 DQ52 DDR_B_D53
159 DQ49 DQ53 160
161 VSS VSS 162
163 164 M_CLK_DDR2
NC,TEST CK1 M_CLK_DDR2 10
+0.9V_DDR_VTT 165 166 M_CLK_DDR#2
VSS CK1# M_CLK_DDR#2 10
DDR_B_DQS#6 167 168
RN13 DDR_B_DQS6 DQS6# VSS DDR_B_DM6
RN11 169 170
DDR_B_MA1 DDR_B_MA9 DQS6 DM6
1 4 4 1 171 VSS VSS 172
DDR_B_MA3 2 3 3 2 DDR_B_MA12 DDR_B_D55 173 174 DDR_B_D54
56_0404_4P2R_5%~D 56_0404_4P2R_5%~D DDR_B_D50 DQ50 DQ54 DDR_B_D51
175 DQ51 DQ55 176
RN10 RN7 177 178
DDR_B_BS0 DDR_CKE3_DIMMB DDR_B_D61 VSS VSS DDR_B_D60
1 4 4 1 179 DQ56 DQ60 180
DDR_B_MA10 2 3 3 2 DDR_B_MA11 DDR_B_D56 181 182 DDR_B_D57
56_0404_4P2R_5%~D 56_0404_4P2R_5%~D DQ57 DQ61
Layout Note: 183 VSS VSS 184
RN4 RN12 Place these resistor DDR_B_DM7 185 186 DDR_B_DQS#7
DDR_B_MA0 DDR_B_MA5 DM7 DQS7# DDR_B_DQS7
1 4 4 1 closely DIMM0,all 187 VSS DQS7 188
DDR_B_BS1 2 3 3 2 DDR_B_MA8 DDR_B_D58 189 190
56_0404_4P2R_5%~D 56_0404_4P2R_5%~D trace length<750 mil DDR_B_D59 DQ58 VSS DDR_B_D62
191 DQ59 DQ62 192
RN3 RN6 193 194 DDR_B_D63 +3.3V_RUN
DDR_B_RAS# DDR_B_MA7 CLK_SDATA VSS DQ63
1 4 4 1 6,16 CLK_SDATA 195 SDA VSS 196
DDR_CS2_DIMMB# 2 3 3 2 DDR_B_MA6 CLK_SCLK 197 198
6,16 CLK_SCLK SCL SAO
56_0404_4P2R_5%~D 56_0404_4P2R_5%~D +3.3V_RUN 199 200 2 1
VDDSPD SA1

100K_0402_5%~D
RN9 RN5
0.1U_0402_16V4Z~D

2.2U_0603_6.3V6K~D

DDR_B_CAS# 1 4 4 1 DDR_B_MA4 201 202 R174


GND GND

1
DDR_B_WE# 2 3 3 2 DDR_B_MA2 10K_0402_5%~D

R173
56_0404_4P2R_5%~D 56_0404_4P2R_5%~D 1 1 TYCO_1565917-4~D
C549

C548

A RN2 A
4 1 M_ODT2 DIMMB
3 2 DDR_B_MA13
STANDARD

2
56_0404_4P2R_5%~D 2 2

RN14
DELL CONFIDENTIAL/PROPRIETARY
RN8 Layout Note:
DDR_CS3_DIMMB# 2 DDR_B_BS2
M_ODT3 1
3
4
4
3
1
2 DDR_CKE2_DIMMB
Place these resistor
closely DIMM0,all
Compal Electronics, Inc.
56_0404_4P2R_5%~D PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL Title
56_0404_4P2R_5%~D trace length TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
Max=1.3" BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, DDRII-SODIMM SLOT2
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD Size Document Number Rev
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. 0.6
LA-2791
Date: Tuesday, February 07, 2006 Sheet 17 of 63
5 4 3 2 1
5 4 3 2 1

FAN1 Control and Tachometer


Place near the bottom SODIMM
+3.3V_RUN

+5V_SUS +5V_SUS

1
R479

1
1 2
D R413 R481 R480 D