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EE 598

Digital Design using Verilog


Lecture 9/10: Behavior Model
Prof. Bo Yuan
Electrical Engineering, CCNY
Slides adapted from Mingjie Lin, Arvind, Krste Asanovic, Emil Petriu, Wikipedia,
Hakim Weatherspoon, Peter M. Nyasulu, David Harris, Sarah Harris
Behavior Model
 Represents circuits at functional and
algorithmic level.
 Use procedural statements similar in concept
to procedural programming languages (e.g. C,
Java),
 Behavioral modeling is mostly used to
represent sequential circuits.
Styles for Behavior Modeling
• Boolean-equation-based behavioral Models
-- Continuous-assignment (assign)

• Cyclic Behavioral Models


-- Dataflow/RTL (always)

• Algorithm-based Models
-- Highest abstraction
Styles for Behavior Modeling
• Boolean-equation-based behavioral Models
-- Continuous-assignment (assign)

• Cyclic Behavioral Models


-- Dataflow/RTL (always)

• Algorithm-based Models
-- Highest abstraction
Continuous Assignment
• Continuous assignment is used to assign a
value onto a wire in a module.
-- It is the normal assignment outside of
always or initial blocks.
• Continuous assignment statements are
concurrent and are continuously executed
during simulation.
-- Order of assign statements does not
matter.
-- Any change in any of the RHS inputs will
immediately change a LHS output.
Example
Simple Circuit Boolean
Expression
HDL Levels
Example
Styles for Behavior Modeling
• Boolean-equation-based behavioral Models
-- Continuous-assignment (assign)

• Cyclic Behavioral Models


-- Dataflow/RTL (always)

• Algorithm-based Models
-- Highest abstraction
Always Block
 The primary construct in RTL modeling.
-- Concurrent statement
-- All always blocks in a module execute simultaneously.

 Used to imply latches, flip-flops or combinational logic.


-- If the statements in the always block are enclosed
within begin ... end, the statements are executed
sequentially.
-- If enclosed within the fork ... join, they are executed
concurrently (simulation only).

 Triggered by the level, positive/negative edge of signals


-- The single edge-triggers are specified by posedge and
negedge keywords.
Syntax and Example
always @(event_1 or event_2 or ...)
begin
... statements ...
end
Type of Variable in Always
• Target variables are of type reg
Reg ? Registers?
Data Type (ctd.)
 Wire
-- A wire represents a physical wire in a circuit and is
used to connect gates or modules.
-- The value of a wire can be read, but not assigned to,
in a function or block.
-- A wire does not store its value but must be driven
by a continuous assignment statement or by connecting
it to the output of a gate or module
Data Type (ctd.)
 A reg (register) is a data object that holds its
value from one procedural assignment to the
next.
-- They are used only in functions and procedural
blocks.
-- A reg is a Verilog variable type and does not
necessarily imply a physical register.
-- In multi-bit registers, data is stored as unsigned
numbers and no sign extension is done
Styles for Behavior Modeling
• Boolean-equation-based behavioral Models
-- Continuous-assignment (assign)

• Cyclic Behavioral Models


-- Dataflow/RTL (always)

• Algorithm-based Models
-- Highest abstraction
Pros and Cons
• The circuit’s input-output algorithm is more
abstract than RTL description.
-- Abstract: Eliminate the need for an a
priori architecture.
-- Readable & Understandable
-- Challenge for EDA tools to synthesize
Styles for Behavior Modeling
Example for Three Styles
• 2-bit Comparator
-- 2 inputs of 2-bit (A, B)
-- 3 outputs of 1-bit (A_lt_B, A_gt_B, A_eq_B)
Dataflow-based Model
Algorithm-based Model
Example: 4-input Multiplexer
• Gate Level
Example: 4-input Multiplexer
• Continuous Assignment
Example: 4-input Multiplexer
• Another type of implementation
Example: 4-input Multiplexer
• Behavioral model
Example: 4-input Multiplexer
• Another type of implementation
If else
 only one if block and one else block.
-- can have many else if statements as required
 else if and else statements are optional.
-- if all possibilities are not s covered, latches will be
synthesized
if (expression)
begin
... statements ...
end
else if (expression)
begin
... statements ...
end
... more else if blocks ...
else
begin
... statements ...
end
Case
 Statements in the default block executes when
none of the case choice are true.
-- If no default, latches may be produced.
 Case choices may be a simple constant or
expression, or a comma-separated list of same.
case (expression)
case_choice1:
begin
... statements ...
end
case_choice2:
begin
... statements ...
end
... more case choices blocks ...
default:
begin
... statements ...
end
endcase
D-FF with Syn Set/Reset
D-Latch
Shift Register
Encoder
Encoder
Encoder
4-Bit Ripple Adder
LFSR-Linear-Feedback Shift
Register (LFSR)
Data-Flow Model of LFSR
Repetitive Logic Modeling
Parameterized Models
SR with Parallel Loads
Barrel SR

Layout of LDPC decoder for IEEE 802.11n

Cited from C. Studer. “Configurable High-Throughput Decoder Architecture for Quasi-Cyclic LDPC
Codes”
Barrel SR
Universal RF
Bi-Directional Bus
Bi-Directional Bus
Sync. Data Swapping

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