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# EE 598

## Digital Design using Verilog

Prof. Bo Yuan
Electrical Engineering, CCNY
Slides adapted from Mingjie Lin, Arvind, Krste Asanovic, Emil Petriu, Wikipedia,
Hakim Weatherspoon, Peter M. Nyasulu, David Harris, Sarah Harris, J. Rabaey,
Soha Hassoun

## • T = O(N) worst case delay

• Goal: Make the fastest possible carry path
Fast Carry Chain Design
 The key to fast addition is a low latency carry
network
 What matters is whether in a given position a
carry is

##  Giving a carry recurrence of

Carry-Bypass (carry-skip)
Optimal Block Size and Time
Variable Block Sizes
A carry that is generated in, or absorbed by,
one of the inner blocks travels a shorter
distance through the skip blocks, so can have
bigger blocks for the inner carries without
increasing the overall delay
Multiple Levels of Skip Logic
Comparisons
 Precompute the carry
out of each block for
both carry_in = 0 and
carry_in = 1 (can be
done for all blocks in
parallel) and then select
the correct one
Path
Bit 0–3 Bit 4–7 Bit 8–11 Bit 12–15
Setup Setup Setup Setup

## Multiplexer Multiplexer Multiplexer Multiplexer

Ci,0 Co,3 Co,7 Co,11 Co,15

## Sum Generation Sum Generation Sum Generation Sum Generation

S0–3 S4–7 S8–11 S12–15
Linear Carry Select
Bit 0-3 Bit 4-7 Bit 8-11 Bit 12-15

(1)

"0" "0" "0" "0"
(1)

## "1" Carry "1" Carry "1" Carry "1" Carry

"1" "1" "1" "1"
(5) (5) (5) (5) (5)
(6) (7) (8)
Multiplexer Multiplexer Multiplexer Multiplexer
Ci,0
(9)

## S0-3 S 4-7 S8-11 S 12-15 (10)

Square Root Carry Select
Bit 0-1 Bit 2-4 Bit 5-8 Bit 9-13 Bit 14-19

(1)

"0" "0" "0" "0"
(1)

## "1" Carry "1" Carry "1" Carry "1" Carry

"1" "1" "1" "1"
(3) (3) (4) (5) (6) (7)
(4) (5) (6) (7)
Multiplexer Multiplexer Multiplexer Multiplexer Mux
Ci,0
(8)
Sum Generation Sum Generation Sum Generation Sum Generation Sum

## S0-1 S2-4 S5-8 S9-13 S14-19 (9)

Comparison
50

tp (in unit delays)

30

Linear select
20

10
Square root select

0
0 20 40 60
N
Verilog Example
Using Generate Statements
CLA

A0 F

A1 A2 A3 A4 A5 A6 A7

A0
tp N
A1

A2
A3
F
A4
A5
A6 tp log2(N)
A7
• Can continue building the tree hierarchically
Co  0 = G0 + P0 Ci  0
C o 1 = G1 + P1 G 0 + P1 P0 Ci 0
C o 2 = G2 + P2 G 1 + P2 P1 G0 + P2 P1 P0 C i 0
=  G 2 + P2 G1 +  P2 P1   G 0 + P0 Ci  0  = G 2:1 + P2:1 C o 0

Comparison

## Cited from N. Weste et.al. “CMOS VLSI Design”

Sequential Implementation
A Basic Array Multiplier
A Basic Unsigned Array
Multiplier
An Unsigned CSA Array
Multiplier
A Signed Array Multiplier
A Signed Array Multiplier
An Unsigned Non-restoring
Division Algorithm
An Unsigned Nonrestoring
Division Example
A Sequential Unsigned Non-
restoring Division
An Unsigned Array Non-
restoring Divider