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EE 598

Digital Design using Verilog


Lecture 3/4: Sequential Logic

Prof. Bo Yuan
Electrical Engineering, CCNY
Slides adapted from Mingjie Lin, Arvind, Krste Asanovic, Emil Petriu,
Wikipedia, Hakim Weatherspoon
Review on Comb. Logic
Until now is combinatorial logic
-- output is computed when inputs are present
-- no internal state for systems
-- nothing computed in the present depends
on what happened in the past
Need of Stateful Components
& Circuits
 Need a way to record data
-- Data storage component

 Need a way to build stateful circuits


-- Sequential logic circuits
Need of Stateful Components
& Circuits
 Need a way to record data
-- Data storage component

 Need a way to build stateful circuits


-- Sequential logic circuits
A Simple Idea
Set-Reset (SR) Latch
Takeaway
 Basic unclocked Set Reset (SR) latch can store
one bit and we can change the value of the
stored bit. But, SR Latch has a forbidden state.
Adding Enable Signal
Data Latch (D-latch)
Takeaway
 Basic unclocked Set Reset (SR) latch can store
one bit and we can change the value of the
stored bit. But, SR Latch has a forbidden state.
 (Unclocked) D Latch can store and change a
bit like an SR Latch while avoiding the
forbidden state.
Clock
 Clock helps coordinate state changes
-- Usually generated by an oscillating crystal
-- Fixed period; frequency = 1/period
Edge triggering
 Circuits can be designed to change on the
rising or falling edge
 Trigger on rising edge = positive
edge triggered
 Trigger on falling edge = negative
edge triggered
 Inputs must be stable just before the triggering
edge
Clock Disciplines
 Level sensitive
-- State changes when clock is high (or low)
 Edge triggered
-- State changes at clock edge

 Positive edge triggered

 Negative edge triggered


D Flip-Flops
Takeaway
 Basic unclocked Set Reset (SR) latch can store
one bit and we can change the value of the
stored bit. But, SR Latch has a forbidden state.
 (Unclocked) D Latch can store and change a
bit like an SR Latch while avoiding the
forbidden state.
 An Edge Triggered D Flip Flip (aka
Master Slave D Flip Flip) stores one bit. The
bit can be changed in a synchronized fashion
on the edge of a clock signal.
Transmission Gate
Transmission Gate-based D-FF
Other types of FF
Registers
 Register
-- Store multiple bits
-- D flip flops in parallel
-- Shared clock
-- extra clocked inputs: write_enable, reset, …
Takeaway
 Basic unclocked Set Reset (SR) latch can store
one bit and we can change the value of the
stored bit. But, SR Latch has a forbidden state.
 (Unclocked) D Latch can store and change a bit
like an SR Latch while avoiding the forbidden
state.
 An Edge Triggered D Flip Flip (aka Master Slave
D Flip Flip) stores one bit. The bit can be changed
in a synchronized fashion on the edge of a clock
signal.
 An N bit register stores N bits. It is be created
with N D Flip Flops in parallel along with a
shared clock.
Practical Example
Need of Stateful Components
& Circuits
 Need a way to record data
-- Data storage component

 Need a way to build stateful circuits


-- Sequential logic circuits
Finite State Machines
 An electronic machine which has
-- external inputs
-- externally visible outputs
-- internal state
 Output and next state depend on
-- inputs
-- current state
Abstract Model of FSM
 Machine is
M = ( S, I, O, T )
S: Finite set of states
I: Finite set of inputs
O: Finite set of outputs
T : State transition function

 Next state depends on present input and


present state
Automata Model
 inputs from external world
 outputs to external world
 internal state
 combinational logic
Mealy Machine
 Outputs and next state depend on both
current state and input
Mealy FSM Example
Moore Machine
 Outputs depend only on current state
Moore FSM Example
Design Example: Counter
State Table
K-Map
Circuits
Example: Digital Door Lock

 Inputs:
-- keycodes from keypad
-- clock
 Outputs:
-- “unlock” signal
-- display how many keys pressed so far
Door Lock: Inputs
 Assumptions:
-- signals are synchronized to clock
-- Password is B A B
Door Lock: Outputs
 Assumptions:
-- High pulse on U unlocks door
State Diagram
Simplified State Diagram
State Table
Stable Table Encoding
Big Picture
Summary
 FSM design strategy:
(1) Draw a state diagram (Moore or Mealy)
(2) Write output and next state tables
(3) Encode states, inputs, and outputs as bits
(4) Determine logic equations for next state
and outputs
 Pros and Cons:
-- Universal for any design
-- Not practical for large-scale design
-- HDL is a more practical choice