LETTERS

International Journal of Recent Trends in Engineering, Vol 2, No. 6, November 2009

FPGA Implementation of Discrete Wavelet

Transform (DWT) for JPEG 2000
M. Jeyaprakash1,
1
KARUNYA UNIVERSITY/Electronics and Communication Department, Coimbatore, India
Email: vlsijp@gmail.com

Abstract—This paper presents an approach towards

FPGA implementation of Discrete Wavelet Transform
(DWT) for image compression. The design follows the
JPEG2000 standard and can be used for both lossy and
lossless compression. Lifting scheme is used for filtering
process. This is more efficient than conventional approach
using convolution. Also, integer arithmetic is used .This
design can be used for image compression in a robotic
system.

Index Terms— Discrete wavelet transform (DWT), image

compression, thresholding, VLSI design, JPEG 2000.

I. INTRODUCTION
With the use of more and more digital still and moving Figure1. View of JPEG2000 Encoding process
images, huge amount of disk space is required for storage
and manipulation purpose. For example, a standard 35- II. LIFTING SCHEME FOR WAVELET TRANSFORM
mm photograph digitized at 12µm per pixel requires
about 18Mbytes of storage and one second of NTSC- Lifting scheme is new method on spatial to construct
quality color video requires 23 Mbytes of storage. That is wavelets which consist of three steps: split, predict and
why image compression is very important in order to update. Lifting wavelet is called the second generation
reduce storage need. Digital images can be compressed wavelet. The basic principle of which is to break up the
by eliminating redundant information present in the polyphase matrices for wavelet filters into sequence of
image, such as spatial redundancy, spectral redundancy upper and lower triangular matrices and convert the filter
and temporal redundancy. The removal of spatial and implementation into banded matrix multiplications. The
spectral redundancy is often accomplished by transform DWT and IDWT lifting scheme is shown in figure.2,3
coding, which uses some reversible linear transform to
decorrelate the image data. JPEG is the most commonly
used image compression standard in today’s world. But
researchers have found that JPEG has many limitations.
In order to overcome all those limitations and to add on
new improved features, researchers has come up with
new image compression standard, which is JPEG2000.
The JPEG2000 is intended to provide a new image
coding/decoding system using state of the art
compression techniques, based on the use of wavelet
technology. Its wide range of usage includes from
portable digital cameras through pre-press, medical Figure2. DWT using lifting
imaging. Right now, JPEG2000 is composed of 6 main
parts. The two important parts in the coding/decoding
processes of JPEG2000 are Wavelet Transform and
Arithmetic Coding. Since the later is widely
implemented, this paper focuses on the hardware
implementation of discrete wavelet transform (both
FDWT and IDWT), which will provide the transform
coefficients for later stage and is one key part of
JPEG2000 implementation. The Fig.1 shows the basic
building blocks of JPEG2000 encoding process.
Figure3. IDWT using lifting

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LETTERS
International Journal of Recent Trends in Engineering, Vol 2, No. 6, November 2009
Let p (z) represents the polyphase matrices for the
analysis filters then p (z) is factorized by lifting scheme
as follows.
in which k is constant , t(z) and s(z) are denoted as
primary lifting and dual lifting polynomial respectively,
and m represents the total lifting steps required.
III. LIFTING OF WAVELET FILTERS FOR JPEG2000
The core coding system of JPEG 2000 standard
recommended two wavelet filters. The (5, 3) filter bank is
recommended for lossless compression. Whereas (9, 7) is
recommended for lossy compression.
The polyphase matrix of this filter bank is
If samples are numbered from 0, the even terms of the
output terms form the low pass subband and odd terms
form the high pass subband.
The lifting based DWT has many advantages over the
convolution based approach. Lifting based DWT
typically requires less computation compared to
convolution based approach. During the lifting
implementation no extra memory buffer is required
because of in-place computation feature of lifting. This is
particularly suitable for hardware implementation with
on-chip memory.
IV. GENERALIZED ARCHITECTURE
The processor architecture consists of adders, multipliers
and shifters that are interconnected in a manner that
support the computational structure of specific filter.
Figure.6 shows processor architecture for the (5, 3) filter
and the (9, 7) filter. While the (5, 3) filter consists of two
adders and a shifter, the (9, 7) filter architecture consists
of two adders and multiplier. In this delays are used.
Delays are used for to overcome the data dependency
problem during computation. And also two processor is
used. Figure.4 shows the processor assignment for (5, 3).
Figure4. Processor assignment for (5, 3) filter
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For example adder1 of p1 adds the elements (x0,x2) in
second clock cycle and stores the sum on register R1. The
shifter reads this sum in the next cycle carries out the
required number of shifts and stores the result in register
RS.The second adders reads the value of Rs and subtract
the elements x1 to generate y1 in the next cycle.
To process N=9 data, the processor takes four clock
cycle, adder 1 in P2 processor starts computation in the
sixth cycle.
A1-adder1 M-multiplier
A2-adder2 Sh-shifter
R-register
Figure5. Processor architecture for the (5, 3) and (9, 7).
V. TWO DIMENSIONAL DWT ARCHITECTURE
The basic idea of lifting based approach for DWT
implementation is to replace the parallel low pass and
high pass filtering by sequence of alternating smaller
filters. The computations in each filter can be partitioned
into prediction and update stages as shown in Figure 6.
Here the row module reads the data from MEM1,
performs the DWT along the rows (H and L) and writes
the data into MEM2. The prediction filter of the column
module reads the data from MEM2, performs column
wise DWT along alternate rows (HH and LH) and writes
the data into MEM2. The update filter of the column
module reads the data from MEM2, performs column
wise DWT along the remaining rows, and writes the LL
data into MEM1 for higher octave computations and HL
data to external memory.
Figure6. Overview of lifting based 2D DWT architecture.
LETTERS
International Journal of Recent Trends in Engineering, Vol 2, No. 6, November 2009
The architecture can compute a large set of filters for
both the 2D forward and inverse transforms. It supports
two classes of architectures based on whether lifting is
implemented by one or two lifting steps. The one step
architecture corresponds to implementation using one
lifting step or two factorization matrices.
RP1, RP2-row processors
CP1, CP2- column processor
MEM1, MEM2- memory
Figure7. One step lifting based architecture.
The block diagram shows one step lifting architecture is
shown in Fig.7. It consists of the row and column
computation modules and two memory units, MEM1 and
MEM2. The row module consists of two processors RP1
and RP2, along with a resister file REG1, and column
module consists of two processors CP1 and CP2 along
with register file REG2. All the four processor RP1, RP2,
CP1, CP2 contain 2 adders, 1 multiplier and 1shifter. RP1
and CP1 are predicting filters and RP2 and CP2 are
update filters.
VI. CONCLUSION
Figure8. RTL view of design
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Synthesis is performed to transform the VHDL code into
logic gate level using Synplify 7.0 by Synplicity. The
physical hardware layout is generated using synthesis
tools. It is a great design approach to take the VHDL
code as a basis and translate it automatically into a netlist.
After synthesis, 3 RTL views and 106 Technology views
have been achieved. One sample Technology view is
given in figure 8. The achieved system frequency is 10.8
MHz In this design 64 bit registers have been used.
The architecture for the 2D discrete wavelet transform
has been proposed, which is based on lifting scheme of
wavelet transform. The proposed architecture can reduce
the internal memory size, the number of accessing storage
and will improve the throughput. This lifting scheme has
been implemented and tested in MATLAB. After this, it
can be implemented in VHDL and then it can be
implemented in a single chip for many image processing
applications.
REFERENCES
[1] T. Acharya and P. S. Tsai. JPEG2000 Standard for Image
Compression: Concepts, Algorithms and VLSI
Architectures. John Wiley & Sons, Hoboken, New Jersey,
2004.
[2] Chengi Xiong, Jinwen Tian and Jian Liu “A fast VLSI
architecture for two dimensional discrete wave let
transform based on lifting scheme “IEEE Trans. pp.1661-
1664, 2004.
[3] Jong woog Kim and Jong wha chong “A fast parallel VLSI
architecture for lifting based 2D discrete wavelet
transform” IEEE Trans page 1258-1261, 2004
[4] Abdullah Al Muhit, Md Shabiul Islam and Masuri Othman
“ VLSI implementation of discrete wavelet transform for
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autonomous robots and agents ,page 391-395,2004.
[5] JPEG official website, www.jpeg.org/jpeg2000.html
[6] Wavelets and Filter Banks by Gilbert Strang and Truong
Nguyen, Wellesley-Cambridge Press, 1997
[7] “Image Compression Using The Haar Wavelet
Transform” by Colm Mulcahy, Spelman College
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22-31