UNIT II

INTRODUCTION TO CMOS CIRCUITS

CONTENTS
1. INTRODUCTION
2. CMOS FABRICATION
2.1 n-well CMOS process
2.2 p-well CMOS process
2.3 Twin -Tub Process

3. LOGIC GATES
CMOS Inverter
NAND Gate
NOR Gate

4. STICK DIAGRAM AND LAYOUT REPRESENTATION

Components in CMOS technology
CMOS Joining Rules
Inverter stick diagrams
NAND gate stick diagrams
NOR gate stick diagram

5. LAYOUT DESIGN RULES

6. SCALING OF CMOS CIRCUITS

7. OTHER CMOS LOGIC

Pseudo nMOS Logic
Clocked Cmos Logic( C2 MOS Logic)
Dynamic CMOS Logic
CMOS Domino Logic
n-p CMOS LOGIC
1. INTRODUCTION

One of the most popular MOSFET technologies available today is the

Complementary MOS or CMOS technology. CMOS technology is the dominant
semiconductor technology for microprocessors, memories and application specific integrated
circuits (ASICs).
The main advantage of CMOS over NMOS and BIPOLAR technology is the
much smaller power dissipation. Unlike NMOS or BIPOLAR circuits, a CMOS circuit has
almost no static power dissipation. Power is only dissipated in case the circuit actually
switches. This allows to integrate many more CMOS gates on an IC than in NMOS or
bipolar technology, resulting in much better performance.

In CMOS technology, both N-type and P-type transistors are used to realize
logic functions. The same signal which turns on a transistor of one type is used to turn off a
transistor of the other type. This allows the design of logic devices using only simple
switches, without the need for a pull-up resistor.

In CMOS logic gates a collection of n-type MOSFETs is arranged in a pull-

down network between the output and the lower voltage power supply rail (Vss or quite often
ground). Instead of the load resistor of NMOS logic gates, CMOS logic gates have a
collection of p-type MOSFETs in a pull-up network between the output and the higher-
voltage rail (often named Vdd). Thus, if both a p-type and n-type transistor have their gates
connected to the same input, the p-type MOSFET will be on when the n-type MOSFET is
off, and vice-versa.

2. CMOS FABRICATION

There are a number of approaches to CMOS fabrication, including the p-well,

the n-well, the twin tub and the silicon - on – insulator processors.

2.1 n-well CMOS process

Step 1: Si Substrate

The n-well CMOS process starts with a moderately doped (with impurity
concentration around 2 ×1021 impurities/m3) p-type silicon substrate.

p substrate

Step 2: Oxidation

This step deposits a thin layer of SiO2 over the complete wafer by exposing it
to high-purity oxygen and hydrogen at approx. 1000oC
 SiO2

p substrate

Step 3: Photoresist Coating

Photoresist is a light sensitive polymer evenly applied to a thickness of 1µm

by spinning the wafer. This photoresist cross link when exposed to light, making the affected
regions insoluble

Photoresist
SiO2

p substrate

Step 4: Masking

The first lithographic mask defining the n-well region is brought in close
proximity to the wafer. The mask is opaque in the regions we want to process and transparent
in the other regions The combination of mask and wafer is now exposed to Ultraviolet rays.
Where the mass is transparent, the photoresist becomes insoluble.

Uv rays

n-type
mask

Photoresist
SiO 2

p substrate

Step 5: Removal of Photoresist

The soluble photoresist are removed by treating the wafer with acidic or basic
solution. Then the wafer is soft baked at low temperature to harden the the remaining
photoresist
 Photoresist
SiO2

p substrate

Step 6: Acid Etching

SiO2 is selectively removed from areas of wafer that are not covered by
photoresist by using hydrofluoric acid.

Photoresist
SiO2

p substrate

Step 7: Removal of Photoresist

Strip off the remaining photoresist

SiO2

p substrate

Step 8: Formation of n-well

n-well is formed by diffusion or ion implantation.

DIFFUSION

In diffusion, the wafers are placed in a quartz tube embedded in a heated

furnace. A gas containing the dopant is introduced in the tube. The high temperatures of the
furnace (900 to 1000oC) cause the dopants to diffuse into the exposed surface both vertically
and horizontally

ION IMPLANTATION

Dopants are introduced as ions into the material. The ion implantation system
directs and sweeps a beam of purified ions over the semiconductor surface. The acceleration
of ions determines how deep they will penetrate the material, while the beam current and the
exposure time determine the dosage.
 SiO2

n well

Steps 2 to 8 constitutes the photolithographic process.

Step 9: Removal of SiO2

Strip off the remaining oxide using HF and we have bare wafer with n-well

n well
p substrate

Step 10: Polysilicon deposition

Deposit very thin layer of gate oxide and then using chemical vapor
deposition process a layer of polysilicon is deposited. In this process silane gas flows over
the heated wafer coated with SiO2 at a temperature of approx. 650oC.The resulting reaction
produces a noncrystaline or amorphous material called polysilicon.

Polysilicon
Thin gate oxide

n well
p substrate

Use same lithography process to pattern polysilicon

Polysilicon
Thin gate oxide

n well
p substrate

Step 11: N- diffusion

Carry on photolithographic process to diffuse n- type material. N-diffusion

forms nMOS source, drain, and n-well contact.

Oxidation
 n well
p substrate

Uv rays

n+ Diffusion

n well
p substrate

Masking

n well
p substrate

Etching

n+ n+ n+
n well
p substrate

Diffusion or Ion implantation

n+ n+ n+
n well
p substrate

Removal of SiO2

Step 12: P- diffusion

 Step 11 repeated with p diffusion mask produces pMOS source ,drain and
substrate contact.

p+ n+ n+ p+ p+ n+
n well
p substrate

Step 13: Contact cuts

Now we need to wire the devices. Cover chip with thick field oxide. Etch
oxide where contact cuts are needed

Thick field oxide

p+ n+ n+ p+ p+ n+
n well
p substrate

Step 14: Metallization

Aluminum interconnect layers are deployed using a process known as

Sputtering. Aluminum is evaporated in vacuum with heat for evaporation delivered by
electron-beam or ion-beam bombarding. Other metal interconnects such as copper require
different deposition techniques.

Metal
Thick field oxide
p+ n+ n+ p+ p+ n+
n well
p substrate

2.2 p-well CMOS process

The fabrication of p-well cmos process is similar to n-well process except that
p-wells acts as substrate for the n-devices within the parent n-substrate

Advantages of n-well process

n-well CMOS are superior to p-well because of

™ lower substrate bias effects on transistor threshold voltage
™ lower parasitic capacitances associated with source and drain region
™ Latch-up problems can be considerably reduced by using a low
resistivity epitaxial p-type substrate
However n-well process degrades the performance of poorly performing p-type transistor

2.3 Twin -Tub Process

A combination of p-well and n-well process is the Twin-Tub process.
Here we start with a substrate of high resistivity n-type material and then
create both n-well and p-well regions.
It is possible to preserve the performance of n-type transistors without
compromising the p-type transistors
In general, the Twin-tub process allows separate optimization of the n and p
transistors

3. LOGIC GATES

3.1 CMOS INVERTER

The circuit below is the simplest CMOS logic gate.

Cmos inverter

• When a low voltage (0 V) is applied at the input, the top transitor (P-type) is
conducting (switch closed) while the bottom transitor behaves like an open circuit.
 • Therefore, the supply voltage (5 V) appears at the output.
• Conversely, when a high voltage (5 V) is applied at the input, the bottom transitor
(N-type) is conducting (switch closed) while the top transitor behaves like an open
circuit.
• Hence, the ouput voltage is low (0 V).
• The function of this gate can be summarized by the following table:

Input Output
High(1) Low(0)
Low(0) High(1)

• The output is the opposite of the input – this gate inverts the input.
• Notice that always one of the transistor will be an open circuit and no current flows
from the supply voltage to ground.

3.2 NAND Gate

NAND Circuit and Standard Symbol

• The circuit has two inputs and one output.

• Whenever at least one of the inputs is low, the corresponding P-type transistor will be
conducting while the N-type transistor will be closed.
• Consequently, the ouput voltage will be high.
• Conversely, if both inputs are high, then both P-type transistors at the top will be
open circuits and both N-type transistors will be conducting.
• Hence, the output voltage is low.
 • The function of this gate can be summarized by the following table:

V1 V2 Output
Low Low High
Low High High
High Low High
High High Low

• If logical 1’s are associated with high voltages then the function of this gate is called
NAND for negated AND.
• Again, there is never a conducting path from the supply voltage to ground.

3.3 NOR Gate

NOR Circuit and Standard Symbol

• The circuit has two inputs and one output.

• Whenever at least one of the inputs is high, the corresponding N-type transistor will
be closed while the P-type transistor will be open.
• Consequently, the ouput voltage will be low.
• Conversely, if both inputs are low, then both P-type transistors at the top will be
closed circuits and the N-type transistors will be open.
 • Hence, the output voltage is high.
• The function of this gate can be summarized by the following table:

V1 V2 Output
Low Low High
Low High Low
High Low Low
High High Low

• If logical 1's are associated with high voltages then the function of this gate is called
NOR for negated OR.
• Again, there is never a conducting path from the supply voltage to ground.

4. STICK DIAGRAM AND LAYOUT REPRESENTATION

Stick diagrams and layout representation are used to convey layer information
through the use of a color code.

The Stick diagrams and layout representation for CMOS are a logical
extension of the nMOS style. The exception is yellow is used to identify p-type transistors
and wires as depletion mode devices are not used.

4.1 Components in CMOS technology

Component Colour Use

power and
metal 1
signal wires
metal 2 power wires
signal wires and
polysilicon
transistor gates
n-type signal wires, source
diffusion and drain of transistors
p-type signal wires, source
diffusion and drain of transistors
signal
contact
connection
connection between
via
metal layers
insulator none -
Metal

Two types of metal are used to represent the supply rails

metal1 ( ) or metal2 ( )

Polysilicon

Polysilicon ( ) is used to represent the gate.

n-type diffusion

n-type diffusion ( ) is used to represent the source and drain n-transistors.

p-type diffusion

p-type diffusion ( ) is used to represent the source

and drain p-transistors.

Contacts

Contacts ( ) are used to represent electrical connections.

Via

Cuts called vias are used to make contact between two metal layers

4.2 CMOS Joining Rules

n-type p-type
poly metal1 metal2
diffusion diffusion
n-type
diffusion
p-type
diffusion
poly
metal1
metal2

symbol key
allowed - connection formed
 prohibited
transistor formed
contact needed if connection required,
otherwise no connection is made
via needed if connection required,
otherwise no connection is made

• wherever red cross green an n-transistors is formed and p-transistor is formed

wherever red cross yellow

• When wires of the same type are crossed connection is made even if you don't use
contact or via.
• Diffusions of the opposite types cannot cross and contact

• poly (red) cannot contact n-diff (green) and p-diff (yellow).

• when you want to connect poly (red) to n-diff (green) or p-diff (yellow), you must
first connect poly (red) to metal1 (blue) and then metal1 (blue) to n-diff (green) or p-
diff (yellow).
 • Metal1 (blue) can contact ndiff (green), pdiff (yellow) and poly (red), but remember
contact is needed, otherwise no connection is made, even if the layers are crossed

• Metal1 (blue) can contact metal2 (purple), but remember, via is needed, otherwise no
connection is made even if the layers are crossed.

4.3 Inverter Stick Diagram

Starting from the circuit diagram of inverter, we can design the stick layout step by step.

1. Two horizontal wires are used for connection with VSS and VDD. This is done in metal2,
but you can decide to use metal1 instead.
2. Two vertical wires (p-diff and n-diff) are used to represent the p-transistor (yellow) and n-
transistor (green).

3. Then the gates of the transistors are joined with a polysilicon wire, and connected to the
input.

4. The drains of two transistors are then connected with metal1 and joined to the output.
There cannot be direct connection from n-transistor to p-transistors.
5. The sources of the transistors are next connected to VSS and VDD with metal1. Notice
that vias are used, not contacts.

4.4 NAND Gate Stick Diagram

4.5 NOR Gate Stick Diagram

5. LAYOUT DESIGN RULES

The physical mask layout of any circuit to be manufactured using a particular

process must conform to a set of geometric constraints or rules, which are generally called
layout design rules. These rules usually specify the minimum allowable line widths for
physical objects on-chip such as metal and polysilicon interconnects or diffusion areas,
minimum feature dimensions, and minimum allowable separations between two such
features. If a metal line width is made too small, for example, it is possible for the line to
break during the fabrication process or afterwards, resulting in an open circuit. If two lines
are placed too close to each other in the layout, they may form an unwanted short circuit by
merging during or after the fabrication process. The main objective of design rules is to
achieve a high overall yield and reliability while using the smallest possible silicon area, for
any circuit to be manufactured with a particular process.

Note that there is usually a trade-off between higher yield which is obtained
through conservative geometries, and better area efficiency, which is obtained through
aggressive, high- density placement of various features on the chip. The layout design rules
which are specified for a particular fabrication process normally represent a reasonable
optimum point in terms of yield and density. It must be emphasized, however, that the design
rules do not represent strict boundaries which separate "correct" designs from "incorrect"
ones. A layout which violates some of the specified design rules may still result in an
operational circuit with reasonable yield, whereas another layout observing all specified
design rules may result in a circuit which is not functional and/or has very low yield. To
summarize, we can say, in general, that observing the layout design rules significantly
increases the probability of fabricating a successful product with high yield.

The design rules are usually described in two ways :

• Micron rules, in which the layout constraints such as minimum feature sizes and
minimum allowable feature separations, are stated in terms of absolute dimensions in
micrometers.
• Lambda rules, which specify the layout constraints in terms of a single parameter (λ)
and, thus, allow linear, proportional scaling of all geometrical constraints.
 Lambda-based layout design rules were originally devised to simplify the
industry- standard micron-based design rules and to allow scaling capability for various
processes. It must be emphasized, however, that most of the submicron CMOS process
design rules do not lend themselves to straightforward linear scaling. The use of lambda-
based design rules must therefore be handled with caution in sub-micron geometries. In the
following, we present a sample set of the lambda-based layout design rules devised for the
MOSIS CMOS process and illustrate the implications of these rules on a section a simple
layout which includes two transistors

MOSIS portable cmos design rules

Rule number Description L-Rule

R1 Minimum active area width 3 L

R2 Minimum active area spacing 3 L

R3 Minimum poly width 2 L

R4 Minimum poly spacing 2 L

R5 Minimum gate extension of poly over active 2 L

R6 Minimum poly-active edge spacing 1 L
(poly outside active area)
R7 Minimum poly-active edge spacing 3 L
(poly inside active area)

R8 Minimum metal width 3 L

R9 Minimum metal spacing 3 L

R10 Poly contact size 2 L

R11 Minimum poly contact spacing 2 L
R12 Minimum poly contact to poly edge spacing 1 L
R13 Minimum poly contact to metal edge spacing 1 L
R14 Minimum poly contact to active edge spacing 3 L

R15 Active contact size 2 L

R16 Minimum active contact spacing 2 L
(on the same active region)
R17 Minimum active contact to active edge spacing 1 L
R18 Minimum active contact to metal edge spacing 1 L
R19 Minimum active contact to poly edge spacing 3 L
R20 Minimum active contact spacing 6 L
(on different active regions)

SCALING

The size of the circuits in IC’s continues to increase. Proper scaling allows to shrink a design.

Technology scaling rate is approximately 13% / year, halving every 5 years.

Besides increasing the number of devices, scaling has had a profound impact on both speed
and power.

Full Scaling (Constant Electrical Field Scaling)

In the ideal model, all the dimensions of the MOS devices, e.g., the voltage supply level and
depletion widths are scaled by the same factor S.
Keeping the electric field patterns constant avoids breakdown and other secondary effects.
This leads to greater device density, higher speed and reduced power consumption.
Ron remains constant -- performance is improved because of the reduced capacitance.
Circuit speed increases linearly while the power scales down quadratically!
Both clearly indicate the benefits of scaling.

Dimensions are scaled by S while voltages are scaled by U.

Fixed Voltage Scaling

Full scaling is not a feasible option.
For example, to keep new chips compatible with existing chips, voltages cannot be
scaled arbitrarily.
Providing multiple voltage supplies is expensive.
5V was used up through the early 90s.
Voltages of 3.3 and 2.5 used since the introduction of 0.5 µm.
The change from a fixed-voltage scaling model to the general scaling model used today
can be justified by reviewing the rightmost column.
In velocity saturated device, keeping the voltage constant while scaling the device
dimensions:
Does not provide a performance advantage over full scaling model (1/S vs. 1/S)
But has a major power penalty associated with it (1/S2 vs 1).

Note the gain of increased current level is offset by the higher voltage swing, which only
hurts power dissipation.
Also note that this is very different from the situation when transistors were operating in the
long-channel mode.
Here, current was a quadratic function of the voltage.
In this scenario, keeping voltage constant gave a performance advantage (net reduction
in "on resistance"
Other reasons for scaling the supply voltage include hot-carrier effect and oxide breakdown.
These latter reasons played a significant role in the trend we see today.
Bear in mind that this is a first order analysis -- in reality, there is a (small) performance
benefit with fixed voltage due to, e.g., channel length modulation.

Supply voltage is now being scaled, but at a slower rate than feature size.
For example, from 0.5 μm to 0.1 μm, supply voltage reduced from 5 V to 1.5V.
Then why not stick with full scaling model if there is no benefit to keeping the supply
voltage
higher.
Some device voltages, e.g., silicon bandgap and built-in junction potential, are material
parameters and cannot be scaled.
VT scaling is limited since making it too low makes it difficult to turn off the devices
completely.
This is aggravated by large process variations.
A more general scaling model is needed, where dimensions and voltages are scaled
independently
using S and U respectively.
Under fixed voltage scaling, U = 1 as shown in the last column of the table.

General Scaling
Under general scaling model, performance scenario is identical (1/S) to other models but
power dissipation lies between the two models, S > U > 1.
Recent CMOS technologies and projections of the future.

OTHER CMOS LOGIC

Pseudo nMOS Logic

Using a PMOS transistor simply as a pull-up device for an n-block is called

pseudo-NMOS logic. In this type of logic the transistor widths must be chosen properly, i.e.,
The pull-up transistor must be chosen wide enough to conduct a multiple of the n-block's
leakage and narrow enough so that the n-block can still pull down the output safely.
 The advantage of pseudo-NMOS logic are its high speed (especially, in large-
fan-in NOR gates) and low transistor count. On the negative side is the static power
consumption of the pull-up transistor as well as the reduced output voltage swing and gain,
which makes the gate more susceptible to noise. Furthermore, when the gate of the pull-up
transistor is connected to a appropriate control signal it can be turned off, i.e., pseudo-NMOS
supports a power-down mode at no extra cost.

Clocked Cmos Logic( C2 MOS Logic)

The logic is implemented in both n- and p- transistors in the form of a pull up

p- block and a complementary n-block pull down structure. However the logic in this case is
evaluated only during the on period of the clock

Dynamic CMOS Logic

 The basic structure of dynamic CMOS logic is shown below

When the clock is low, the NMOS device is cutoff while the PMOS is turned
ON. This has the effect of disconnecting the output node from ground while simultaneously
connecting the node to VDD. Since the input to the next stage is charged up through the
PMOS transistor when the clock is low, this phase of the clock is known as the ‘precharge’
phase.

When the clock is high however, the PMOS is cutoff and the bottom NMOS is
turned ON, thereby disconnecting the output node from VDD and providing a possible pull-
down path to ground through the bottom NMOS transistor. This part of the clock cycle is
known as the ‘evaluation’ phase, and so the bottom NMOS is called the ‘evaluation NMOS.’
When the clock is in the evaluation phase, the output node will either be maintained at its
previous logic level or discharged to GND. In other words, the output node may be
selectively discharged through the NMOS logic structure depending upon whether or not a
path to GND is formed due to inputs of the NMOS logic block. If a path to ground is not
formed during the evaluation phase, the output node will maintain its previous voltage level
since no path exists from the output to VDD or GND for the charge to flow away.

There are many advantages to using dynamic CMOS logic over static CMOS
logic or Pseudo NMOS logic.

• The elimination of the complimentary PMOS transistors significantly reduces the

surface area needed to implement the various logic functions not only because the
physical number of transistors is nearly cut in half, but because the physical size
of the PMOS transistors tend to be much larger than the size of an NMOS
transistor.
• The switching speeds are also increased using the dynamic logic configuration
since the speed bottleneck caused by the lengthier time the PMOS requires to
pull-up the output node is eliminated. Since this node is already precharged high
through the PMOS during the precharge phase, the output node needs only to be
selectively discharged during the evaluation phase. Discharging the output node
 through the NMOS devices is significantly faster than the time needed to charge
up the output node through the PMOS device.

There are several potential problems with the implimentation of this design
that need to be considered.

• Since the basic dynamic CMOS logic configuration causes the output node to be
disconnected from VDD during the evaluation phase, even if the output is also
disconnected from GND, the charge of the output node will begin to diminish due
to the non-ideal effects of the system. Parasitic capacitances, for example, may
leak the charge away from the output node and eventually cause a logic error.
Since there is, however, a finite time needed for the charge to erroneously escape,
the use of faster the clock speeds will eliminate this kind of error. This implies
however, that there is a minimum clock speed at which dynamic CMOS logic
structures may be operated. It also eliminates the possibility to idle the basic
dynamic CMOS logic circuit.

CMOS Domino Logic

CMOS domino gates are formed by cascading dynamic gates. This kind of
design is referred to as Domino Logic since the pull-down of one stage can conditionally
cause the pull-down of succeeding stages and so on like falling dominoes. The number of
Domino Logic stages that may be cascaded is limited only by the sum of the total pull-down
times in all cascaded logic blocks which must be contained within the evaluation clock
phase.

The dynamic gate works or operates in two phases: Precharge phase and
evaluation. During the precharge phase, the clock input is low, turning off the NMOS device
and switching on the PMOS device, this pulls the output high, as there is no path from the
output to the ground.
 During evaluation the clock input is high, turning the PMOS transistor off and
switching on the NMOS transistor. In this case the output of the device depends on the
inputs. According to the precharge rule there should be no active path from the output to the
ground during the precharge cycle, otherwise there will be a dissension between the PMOS
precharge transistor and the NMOS transistors pulling to ground, consuming excess power
and leaving the output at indeterminate value.

Drawbacks to this design are

• The addition of two additional components to each dynamic block.

• Extra design consideration must also be observed when using dynamic CMOS
logic blocks in conjunction with static CMOS logic blocks.
• Only non inverting logic functions can be realized

n-p CMOS LOGIC

An alternative to Domino Logic is n-p cmos logic or Domino-Zipper Logic. n-

p logic is characterized by alternating the MOSFETs in the logic block from PMOS to
NMOS logic gates and so on.

The function of the clocked n- and p- fets in the PMOS logic stage are
reversed compared to the NMOS logic stage.

• Although this structure eliminates the cascading problem, the excess use of
PMOS in forming the logic gates reduces the maximum clocking speed and
increases the surface area of the system.
• Another significant drawback to this configuration is the use of the two-phase
clock The signals of both clock phases must be delivered at nearly the same
instant for the circuit to operate correctly.