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General Description
This application note describes how the NCP3063 can be This switching regulator is based on a very flexible ”gated
configured as a buck controller to drive an external PFET oscillator or bust mode” architecture that can be used to
transistor to produce a cost effective, high efficiency 3 A create step-down (buck), step-up (boost) and buck-boost
switching regulator. The NCP3063 has a wide input voltage voltage regulators. The NCP3063 contains an internal
range up to 40 V which makes it attractive for industrial and switch capable of up to 1.5 A but in applications requiring
consumer applications such as LCD-TVs. The design higher current, this device can be configured as a controller
example illustrates a buck converter delivering 3 A at 5 or driving an external MOSFET.
3.3 V from a 12 V supply.
The block diagram of the NCP3063 controller is shown in
Figure1.
NCP3063
8 1
NC TSD Switch Collector
SET Dominant
R
Q
S
7 Comparator
Ipk Sense - 2
+ R
Switch Emitter
Q SET Dominant
S
-
+ 0.2 V Oscillator
3
6 CT Timing Capacitor
+VCC
Comparator 1.25 V
+ Reference
- Regulator
5 4
Inverting Input GND
Typical operating waveforms, including the timing ramp CT, are illustrated in Figure 2.
1
Feedback Comparator Output
0
1
IPK Comparator Output
0
Timing Capacitor, CT
On
Output Switch
Off
Output Voltage
Startup Operation
For detailed information regarding controller operation between the charge current and the discharge current is set
refer to the NCP3063 data sheet. The essentials of the within the controller to be 1:6. This ratio creates a fixed duty
control method can be observed in the waveforms of cycle DMAX of 6/7 or 0.86. The ramp circuit is modified
Figure2. The output voltage is fed back to the inverting (also illustrated in Figure 3) by adding of an external current
input 5 of the comparator (Figure 1) via a resistor divider. If source IFF to ICHARGE at the CT pin. This current source, in
the output is below the set point, the comparator “gates” a the simplest case, is created by adding a feedforward resistor
series of clock cycles through the power switch. Control of between VIN and CT. (Additional information is available in
the output voltage is achieved by varying the average the application note AND8284.)
number of “on cycles” to the number of “off cycles” in a ICC
given time interval.
The transfer function (or gain) VOUT/VIN for a
conventional buck converter, neglecting circuit losses, is ICHARGE
given by the following equation:
BuckTransferFunction + D (eq. 1) IFF
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D MOD + T ONńT S (eq. 6) The table also shows the change in normalized oscillator
frequency. Once an optimum duty cycle has been identified
F S + 1ńT S (eq. 7)
and IFF selected, the value of CT can be ratio metrically
Table 1 shows the corresponding reduction in duty cycle increased to reset the design frequency. This done, the
DMOD as a normalized function of the charging and converter's design frequency remains constant over a wide
discharging currents flowing into the timing capacitor CT. range of operating conditions.
Variation of duty cycle DMOD and frequency FMOD as a function of normalized external current, charging the timing capacitor CT.
Practical Example
Figure 4 is a schematic of the buck converter. The input is NCP3063 is used as the imbedded controller driving an
a nominal 12 V while the output is regulated to 5 V. The external PFET switch.
NTMS5P02R2 L1
VIN = 12 V Q1 VOUT = 5 V
R1 22 mH
0.05 R2
R4 1k D3 C2 C12
3.76 k Q2 MBRD320 10 mF / 6V3 220 mF / 6V3
MMBT3904TT1G
D1 MMSD914T1G
U1
C1 NCP3063 MMSZ5V6T1
D2
C11 NC SWC 1
10 mF / 8
ISENS SWE 2
220 mF / 25 V 25 V 7
VCC CT 3
6
CMPINV GND
5 4
R6 15 k
R5 C3
1.24 k C4
RTN 2.2 mF / 25 V 3.9 nF
RTN
The selection of the timing capacitor CT (C4) and - charging current is 260 mA @ 5 V VCC / 25°C and
feedforward resistor R6 is discussed next. 280ĂmA @ 40 V VCC / 25°C.
Assuming no circuit losses, the transfer function or gain - discharging current is 1550 mA @ 5V VCC / 25°C and
of this application is 0.42 and is also 0.42. Referring to 1700 mA @ 40 V VCC / 25°C.
Table1, a 3:1 ratio for the external charging current to Assume we chose to operate at a switching frequency of
internal charging current would generate a modified duty approximately 200 kHz. Then TS is 5 mS and TON is 2.5 mS
DMOD of 0.5. This is a good starting point. giving the required modified duty cycle DMOD of 0.5.
The nominal charge and discharge currents for the Rearranging Equation 3, a value for the timing capacitor CT
NCP3063 are listed below: is obtained:
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With the values selected the observed ramp was captured continuous conduction mode, the maximum switch current
in Figure 5. The measured values are given below. and voltage ratings of the MOSFET must be considered. A
TON = 2.10 mS TS = 4.88 mS FS = 205 kHz 20 V, 5 A, 26 mW PFET such as the NTMS5P02 meets our
criteria with margin for de-rating. For a smaller package
ΔVRAMP = 0.54 V ΔVAVG = 0.94 V
footprint, the NTHS5441T1G PFET could also be an option,
DMOD = 2.1 / 4.88 = 0.43. depending on output current and thermal considerations.
The experimental duty cycle is close to our actual design The RDS(on) and total gate charge Qg curves for
requirement of DMOD = 0.42. ONSemiconductor's NTMS5P02R2 P channel MOSFET
are shown in Figures 6 and 7.
Selection of External Transistor Q1
Given the design requirements for a 12 V input and 3 A
output buck converter running with low ripple current in
RDS(on), DRAIN-TO-SOURCE RESISTANCE (W)
0.05 5 20
QT
TJ = 25°C VGS = -2.5 V
4 -VGS 16
0.04 -VDS
VGS = -2.7 V 3 12
Q1 Q2
0.03
2 8
VGS = -4.5 V
0.02
1 ID = -5.4 A 4
TJ = 25°C
0.01 0 0
2 4 6 8 10 12 0 4 8 12 16 20 24
-ID, DRAIN CURRENT (A) Qg, TOTAL GATE CHARGE (nC)
Figure 6. RDS(on) vs. Drain Current ID NTMS5P02R2 Figure 7. Qg vs. VGS NTMS5P02R2
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The conduction loss PQ1 is given by Equation 9. and R2, illustrated in the schematic (Figure 4) provides a fast
P Q1 + ńI OUT @ R DS(on) @ D MOD
2
(eq. 9)
turn off for the PFET Q1.
The turn on/off behavior of the external PFET Q1 is
PQ1 = 32* 26 mW * 0.43 = 101 mW determined as follows. When the internal switch within the
A 5.6 V zener diode D2 (Figure 4) is used to drop the gate NCP3063 turns “on”, the gate charge for Q1 is provided by
drive voltage VGS below VIN current flowing from VIN via D1 and D2 to ground return.
The positive voltage across D1 creates a reverse bias
The gate power PG required to switch the FET channel on
condition across Q2's base emitter junction. Q2 remains in the
and off is given by:
off state until the internal switch in the NCP3063 is itself
PG + QG @ VG @ FS (eq. 10) turned “off”. At this time, current flowing through resistor R2
For VGS = 4.5 V, the gate charge QG (from Figure 6) is 20nC is diverted to provide Q2 base current. Q2 conducts until Q1's
gate charge is neutralized.
PG = 20 nC * 4.5 V * 200 kHz = 180 mW
The gate drive waveform is captured in Figure 8. The
network consisting of a small signal NPN transistor Q2, D1
Figure 8. High Side Gate Drive for PFET Q1 with Clock Ramp
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able to selecting a lower value for L1 reduces the winding Small value MLCC capacitors in 805 and 1206 SMD
resistance RW, improving converter efficiency. packages can be an alternative to electrolytic or tantalum
capacitors. These MLCCs have extremely low ESR (2mW)
Selection of Freewheel Diode D1 and ESL (100 nH) parasitic values and so individually or in
Figure 9 shows the forward drop of the MBRD320 series parallel combinations can form the “perfect” lossless
of SWITCHMODEt power rectifiers in a DPAK surface capacitor when used for filtering at mid to high switching
mount package. frequencies.
For example if C1 = C2 = 10 mF, ΔIL1 = 0.6 A and DMOD
= 0.43, the peak to peak voltage ripple ΔVC across the input
10
and output of the converter are 130 mV and 171 mV
respectively. However as the NCP3063 controls the output
IF, INSTANTANEOUS FORWARD CURRENT (A)
Current Limit
75°C The NCP3063 has a peak current limit sense circuit, set by
1 connecting a sense resistor R1 (Figure 4) between pins 7 and
8 of the controller. The reference voltage for the current limit
function is nominally 200 mV so selecting a 50 milliohm
resistor for R1 allows the converter to operate above 3A
before current limit protection is activated. The power loss
in the sense resistor is 32 * R1 or Ps = 450 mW.
Bias Current
The maximum bias current to power the NCP3063 is
0.1 7mA. Bias power PB is 84 mW.
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1
VF, INSTANTANEOUS VOLTAGE (V) Loss Budget
Figure 9. Forward Drop of MBRD320 Summing the theoretical losses for Q1's conduction and
As can be seen from Figure 9, the typical forward drop gate drive, inductor winding, freewheel diode , current sense
VFWD at 3.0 A is 0.4 V at 75°C. The conduction loss PFWD and bias power, we obtain a loss budget of 101 mW
for the free wheel diode is given by the equation: +180mW + 234 mW + 520 mW + 450 mW + 84 mW or
1.57W, neglecting hysteresis losses in the inductor and esr
P D + I OUT @ V D @ (1 * D MOD) (eq. 13)
losses in the input and output capacitors. The converter's
PFWD = 3.0 A * 0.4 V * 0.43 = 0.52 W maximum theoretical efficiency is 15/16.57 or 90.5%.
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90 5.0 V
EFFICIENCY (%)
3.3 V
80
70
60
50
0 0.5 1.0 1.5 2.0 2.5 3.0
The waveforms across freewheel diode D3 and ramp DMOD, the gated oscillator operates in a near continuous
capacitor C4 are illustrated in Figure 11 at the full load mode, providing drive pulses every clock cycle.
condition of 5 V and 3 A. By reducing the duty cycle to
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Figure 12 illustrates the output ripple, under the same test Note the ripple frequency is 52 mV p/p and approximately
condition, together with the switch node (D3) for reference. one third of the converter's 200 kHz clock frequency.
Conclusion
By summing an external current source into the CT pin of to be designed for lower stress. Input capacitors, output
the NCP3063, it is possible to optimize the open loop gain capacitors, inductor, switches and diodes can all benefit
of buck, boost or buck boost topologies for any given from the DMAX reduction. In the case of a 12 V to 5 V buck
application. Reducing the controller's maximum duty cycle converter, the selection criteria of each component is
of 0.86 to a lower value DMOD allows the power components discussed and experimental data and waveforms presented.
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