A High-Efficiency AC-to-DC Adaptor with a Low Standby Power Consumption

Yu-Kang Lo, Shang-Chin Yen and Jin-Yuan Lin

Dept. of Electronics, NTUST
No. 43, Sec. 4, Keelung Road
Taipei, 10607, Taiwan, ROC
Email: yklo@et.ntust.edu.tw

voltage and a delay signal in turn enable the burst modes of

Abstract⎯A two-stage burst mode control scheme for a the HB-SPRC and the DCM PFC. At light loads, the
high-efficiency AC-to-DC adaptor is proposed in this paper. HB-SPRC provides higher voltage gains to store more
The boost power factor corrector (PFC) is operated at the energy and to shorten the burst mode period. Thus the
discontinuous conduction mode (DCM). The half-bridge
no-load or standby power consumption may be reduced.
series-parallel resonant converter (HB-SPRC) is adopted as the
DC/DC topology. An upper limit for the output voltage is set to Operating principles of the power circuit and the burst mode
turn off both two control IC’s at either a light load or no load. control will be described. Design considerations are given.
One lower limit for the output voltage and a delay signal in turn Satisfactory experimental results are recorded on a 80 W/12
enable the burst modes of the HB-SPRC and the DCM PFC. At V prototype adaptor.
light loads, the HB-SPRC provides higher voltage gains to store
more energy and to shorten the burst mode period. Thus the II. CIRCUIT OPERATIONS
no-load or standby power consumption may be reduced. An
average active-mode efficiency of 90 % and a 50 mW no-load The block diagram of the proposed adaptor is shown in
power loss are observed on a 80 W/12 V prototype adaptor. Fig. 1. The DCM PFC converts the AC input to a
loosely-regulated high DC output voltage with a unity input
power factor (PF). The HB-SPRC then converts the output
I. INTRODUCTION voltage of the PFC into a tightly-regulated low DC output
voltage with zero-voltage switching. The burst mode
Owing to gradual exhaustion of usable energy, the
controller sends signals to disable the PFC and SPRC
exploitation of various kinds of energies and restriction of
controllers at light loads. Since the DCM PFC also features
energy use are now becoming a common consensus
zero-current switching characteristics, the average efficiency
worldwide. Well-developed countries like the US, Europe,
of the adaptor in the active mode (arithmetic average of the
and Japan have made appropriate energy policies for energy
efficiencies measured at 25 %, 50 %, 75 % and 100 % load)
use. Adaptors are the devices that convert incoming high
can be as high as 85 %. As for the no load consumption,
voltage ac power from wall outlets into low voltage dc power
several schemes such as pulse skipping, burst mode and
needed by various electronic products. These power supplies
off-time modulation are usually adopted to reduce the
represent the most obvious opportunity for energy savings.
standby power.
Roughly 75% of the total energy savings opportunity is in
Fig. 2 depicts the gating signals for burst mode
products’ active or operational mode, rather than in the
operations. When the output voltage drops to its lower bound
standby or low power modes. Unfortunately, most current
VL, the controller is enabled and thus the converter starts to
power supplies are only 30 to 60 % efficient when operating,
transfer energy to the output and brings Vo up. Once Vo rises
and consume 1 to 3 watts even with no product attached to
to its upper limit VH, the controller is disabled and there are
them (no load). Improved designs are 70 to 90% efficient and
consume less than 0.2 watts at no load. The standards of
power consumption in the standby mode (i.e., green power) is
of electrical products are generally set below 0.5-1 watt.
Manufacturers of relevant electronic products have vs DCM HB-
PFC SPRC 80 W/12 V
developed appropriate products (power-saving ICs,
special-function control ICs, power supplies and so on) for
future probable system standards and specifications [1].
In this paper, a two-stage burst mode control scheme for PFC SPRC
a high-efficiency AC-to-DC adaptor is proposed. The boost controller controller
power factor corrector (PFC) is operated at the discontinuous
conduction mode (DCM). The half-bridge series-parallel
Burst
resonant converter (HB-SPRC), or the Class D SPRC is mode Vo
adopted as the DC/DC topology [2]-[4]. An upper limit for controller
the output voltage is set to turn off both two control IC’s at
either a light load or no load. One lower limit for the output Fig. 1: The block diagram of the proposed adaptor.
 The magnitude frequency response of (1) is drawn in Fig.
Vo 4, where frs, frp and fsw are the series-resonant frequency,
VH parallel-resonant frequency and switching frequency,
respectively. The switching frequency is often chosen to be
VL higher than the resonant frequency such that the resonant
t tank appears inductive. It is observed that the SPRC acts like
a series-resonant converter (SRC) at normal loads (smaller
gating signals Rr), since the impedance of Cpr is much larger than Rr. To
regulate Vp and thus the output voltage, it is required to adjust
the switching frequency. As the load decreases (Rr increases),
the switching frequency rises, and vice versa. At lighter loads
t (larger Rr), the SPRC acts like a parallel-resonant converter
Fig. 2: Operations of the burst mode. (PRC). A voltage gain higher than unity may be experienced.
To regulate the output voltage at this circumstance, a much
no gating signals. The load power is solely provided by the higher switching frequency must be adopted. However, this
output energy storage elements. And the power consumption is sometimes unfeasible. Thus, burst mode control or other
is mainly contributed by the enabled controllers. It can be schemes can be utilized to regulate Vo at light loads or even
seen that to reduce the power consumption at light loads by no load.
the burst mode control, either the on-time of the controller To reduce the no-load consumption of the discussed
must be shortened or the off-time of the controller must be adaptor, a two-stage burst mode control method is proposed.
extended. The operation of the proposed burst mode controller is
The power circuit of the HB-SPRC is illustrated in Fig. characterized in Fig. 5. When Vo reaches VH, both PFC and
3(a). It should be noted that there is no filter inductor in the SPRC controllers are turned off to save up the energy usage
output. Cs is the capacitor of the series-resonant tank, also during light loads. As Vo decreases to the lower bound VL,
serves as a DC blocking capacitor. The HB-SPRC can be the controller of the HB-SPRC is first enabled. As described
equivalently modeled as shown in Fig. 3(b). Vi is the
fundamental component of Vn, which is a train of pulses |M(jω)|
fluctuating between 0 and Vd. Cpr and Rr are the reflected 2
capacitance and resistance from the secondary to the primary. 1.8
1.6 Decreasing Rr
The transfer function of the voltage gain for the equivalent 1.4
circuit is thus 1.2
1
0.8
1 0.6
s
Vp (s) LsCpr 0.4
M(s) = = (1) 0.2
Vi (s) 3 1 2 1 1 0 fsw
s + s + s+ frs frp
CprRr Ls (Cs + Cpr ) LCsCprRr
Fig. 4: The magnitude frequency response of the circuit in Fig. 3(b).

Vo
S1 D1 Coss1 VH
Cs Ls
+ +
Vd Vn VL
− D3 Cp
+
Vo t
Vp D4 R
S2 Coss2 −
D2 −
HB-SPRC
(a)

+ t
Cs Ls
Vi Vp PFC
Cpr Rr
−
(b)
t
Fig. 3: (a) The power circuit and (b) the equivalent circuit of the HB-SPRC. Fig. 5: Operations of the two-stage burst mode control.
above, the SPRC provides a higher voltage gain at light loads. the controllers are disabled when Vo exceeds VH. Once Vo
Thus the on-duration of the burst mode can be shortened. If drops to VL, the HB-SPRC is activated. The DCM PFC is
the energy supplied by operating the HB-SPRC alone can lift only enabled when the SPRC alone cannot provide enough
up the output voltage soon enough, the PFC controller energy to the output in a preset time. The experimental results
remains disabled. However, if the increasing rate of Vo is are summarized in Table I. The average PF at 25 %, 50 %, 75
slow, the PFC controller is also enabled after a preset time. % and 100 % loads is 0.988. And the average efficiency at the
Since the output voltage of the PFC will be established in this four active modes is nearly 90 %. The switching frequency
interval, the output voltage of the whole adaptor can then be range is from 59 kHz to 220 kHz. Notably, the power
increased faster. consumption at no load is only 50 mW under the proposed
As for the design consideration, the DCM PFC is two-stage burst mode control scheme.
operated at the boundary mode with a constant on-time. The
switching frequency range of the HB-SPRC is first set to
determine the resonant capacitance and inductance.
Implementation of the proposed burst mode controller is as vs: 100 V/div
illustrated in Fig. 6. The output voltage is sensed and is: 2 A/div
compared to VH, and VL. The outputs of the comparators are vs Time: 4 ms/div
sent to determine the operations of the controllers for the PFC
and the SPRC. Prototypes of the proposed 80-W/12-V
adaptor is built to demonstrate the feasibility of the presented
scheme. is
III. EXPERIMENTAL RESULTS
The circuit parameters are listed as follows: Vs = 110
Vrms, VH = 12.4 V, VL = 11.6 V, Ls = 60 µH, and Cs = 0.168
µF. Fig. 7 shows the waveforms of vs and is. It can be seen
that the fundamental component of is is an in-phase sinusoid.
Fig. 8 depicts the zero-voltage switching characteristics of Fig. 7: Waveforms of vs and is
the HB-SPRC. vDS and vGS are the drain-to-source voltage
and the gate signal for the switches. The two-stage burst
mode control operations are shown in Fig. 9. At no load, both
vDS
vGS
Disable DCM PFC
Vo + controller

12.4 V −
HB-SPRC
Enable controller
+ vDS: 100 V/div
vGS: 5 V/div
11.6 V − Delay Time: 2 µs/div
Fig. 6: Implementation of the burst mode controller. Fig. 8: Zero-voltage switching characteristic of the HB-SPRC.

TABLE I
SUMMARY OF THE EXPERIMENT RESULTS

No Load Active Power Values

Percent of Nameplate Current 0% 25 % 50 % 75 % 100 % Average
DC Output Current (A) 1.67 3.4 5 6.7
DC OUTPUT VOLTAGE (V) 12 11.9 11.89 11.89 11.87
DC Output Power (W) 19.87 40.43 59.45 79.53
Switching frequency (kHz) 220 123 103 86 59
AC Input Voltage (V) 115 115 115 115 115
AC Input Power (W) 0.0495 23.48 45.05 64.86 86.09
Power Factor (W/VA) 0.97 0.990 0.994 0.997 0.988
Efficiency 84.6 % 89.7 % 91.7 % 92.4 % 89.6 %
 REFERENCES
Vo
[1] J. H. choi, D. Y. Huh and Y. S. Kim, “The improved
burst mode in the stand-by operation of power supply,”
IEEE Conf. APEC '04, Vol. 1, pp. 426 – 432, 2004.
[2] X. Jin, W. Wu, X. Sun, and J. Liu, “Resonant tank and
transformer design in series resonant converter,” IEEE
Conf. IAS '05, Vol. 2., pp. 1475 – 1482, 2005.
HB-SPRC Time: 100 ms/div [3] B. K. Lee, S. B. Yoo, B. S. Suh, and D.S. Hyun, "A new
class-D voltage source series-loaded resonant inverter
topology considering stray inductance influences," in
DCM-PFC IEEE Conf. APEC '96, vol. 1, pp. 187 – 193, 1996.
[4] Youssef, M.Z., Jain, P.K. ,”Self-sustained oscillation
series-parallel resonant converter with the high
frequency effects: analysis, modeling, and design,”
Fig. 9: Two-stage burst mode control. IEEE Conf. APEC '04, Vol. 3., pp. 1416 – 1422, 2004.

IV. Conclusions
The proposed two-stage burst mode control features a
very low standby power. Also the adoptions of the DCM PFC
and the HB-SPRC for the main power circuits promote the
active-mode efficiencies. One possible arrangement of the
burst mode controller is presented and tested. Experiments
show satisfactory results.