Design and Simulation

of Electronic
Communication Adolfo del Solar
application engineer

Systems and RF
Board
October 2017
Why Simulation? What is the Value?

Without Simulation:
Learn from Try and Error

Simulation allow the user to observe the impact of their choices

without the outcome having any impact on the real operation and
predicts the functionality

Page 2
Electronic Design Automation (EDA)

IDEA

CONCEPT | DESIGN

PRODUCT

Page 3
 Keysight EEsof EDA : Design flow Proposal
System, Analog, HSD, RF/MW, EM, EMI/EMC Analysis and integration with third party tools up to final Test

System simulation:
Baseband, RF/MW
Communication systems,
Radar Analog, Signal Integrity,
Circuit simulation:
RF/MW Physical Design:
Layout
Physical analysis:
EM, SI/PI, EMI/EMC &
Electro-Thermal
Simulation

Verification & Test

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Converting Concept to Product

Final
Packaging, Product
Antenna
RF Board
Integration
RFIC
Design &
Module
System
Concept

Page 5
Converting Concept to Product
Keysight EDA Software help

Final
Packaging, Product
Antenna
RF Board
Integration
RFIC
Design &
Module
System
Concept

Page 6
Outline Page 7

System Level Electronic Design with SystemVue

RF Board Design with ADS, EMPro and Genesys

Impedance Matching Application

PCB Signal Integrity & Power Integrity

consideration with ADS, SIPro and PIPro
Signal Integrity
Power Integrity
 What is SystemVue?
System-level design cockpit, focused on Communications
#1 SystemVue models Physical Layer (PHY) architectures
across multiple Baseband & RF domains, for better system designs

#2 SystemVue provides
an implementation path to
FPGA/DSP hardware

#3 SystemVue enables cross-domain verification, connecting Baseband

algorithm to RF tools, Standards references, and Test & Measurement.

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 Validate Comms before/after R&D commitments
Transition naturally from DesignTest with a single cockpit
IP Reference Libraries
4G LTE-Advanced, LTE
STANDARDS
3G HSPA+, WCDMA, etc
REFERENCES
WLAN 802.11ac/n/a/
WPAN 802.11ad, 802.15.3c

BB Algorithm RF / Analog
Modeling Channel Modeling
BASEBAND
MATLAB .m RF SYSTEM
MIMO Channel (OTA)
MODELING
FixedPoint,
Embedded C++
HDL/FPGA Digital Pre-Distortion (DPD)
MODELING
RF System Design
Filtering, EQ, Modem RF EDA platforms

Test Software Test Equipment

LINKS
RF TO
I/O Lib, ComExpert
Sources & Analyzers
89600 VSA AWG & Digitizers
REAL WORLD,
Signal StudioScopes, Logic, Modular
3rd Party
HARDWARE TEST

Page 99
 Validate Comms before/after R&D commitments
Transition naturally from DesignTest with a single cockpit
IP Reference Libraries
4G LTE-Advanced, LTE Quickly capture system level
3G HSPA+, WCDMA, EDGE, GSM design concepts
WLAN 802.11ac/n/a/b/g
WPAN 802.11ad, 802.15.3c Model implementation-level
impairments

BB Algorithm RF / Analog
Modeling Channel Modeling
MATLAB .m MIMO Channel (OTA)
FixedPoint, HDL/FPGA Digital Pre-Distortion (DPD)
Embedded C++ RF System Design
Filtering, EQ, Modem RF EDA platforms

Test Software Test Equipment

I/O Lib, ComExpert RF Sources & Analyzers
89600 VSA AWG & Digitizers Connect BB, RF, and T&M
Signal Studio Scopes, Logic, Modular for rapid validation
3rd Party
Rapid prototyping with
integrated measurement

10
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Who uses SystemVue?
System Architects
Simple and easy model based design workflow
Multi-domain modeling for RF, baseband, and algorithms
Fast link level analysis of Layer 1 systems Typical Design
Baseband Architects & Algorithm Developers Organization
Multi-language Modeling
Target Neutral IP development
Cross domain debugging of IP

RF System Architects
Accurate models and analysis in native Frequency domain
Flow integrity with circuit level design (ADS) 1010 1011
0110 0010
Integration with vector modulation analysis 1100 0110

Embedded FPGA and DSP HW Designers

Advanced analysis and heuristics for fixed point systems
Link algorithms to HW in common formats
Structured verification from design to implementation

System Verifiers
Use measurement-grade reference IP, or create custom signals
Verify system block level interoperability at all levels of H/W abstraction
IP aggregation, including both BB and RF Systems

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 SystemVue FPGA Design Flow
SYSTEM
LEVEL

POLYMORPHIC MODEL
FIXED
POINT

Co-sim Wrapper Co-sim Wrapper

Aldec Riviera-PRO Mentor ModelSim
RTL VHDL/Verilog VHDL/Verilog
File Hierarchy File Hierarchy

Altera Quartus II Xilinx ISE Riviera-PRO ModelSim

IP, Place & Route, IP, Place & HDL simulation HDL simulation
Synthesis Route, Synthesis UI, Libraries UI, Libraries
FPGA Simulation Simulation
Stratix Cyclone Visualization Visualization
Virtex
IV/V IV Debugger Debugger

Hardware in-the-Loop (HIL)

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12
SystemVue Demo

13
 Result: An integrated, tops-down design flow
Cross-domain model-based design: RF, Comms, and C++/HDL
MEASUREMENT, ANALYSIS
System design
RF Architecture
Baseband design
PHY Reference Dataflow Simulation
Algorithms
C++, .m

FlexDCA software VSA software

Handwritten .m/C++ ALGORITHM

HDL
Custom IP
HDL Simulator(s)
Target-neutral Infiniium Scope
MXA / PXA
HDL Generation

SIMULATED H/W
.bit
MXG / ESG
Files FPGA Target Logic Analyzer
FPGA
Synthesis

Wideband AWG RF sensor

DIGITAL BITS, or MODULATED CARRIERS
REAL HARDWARE

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14
Outline Page 15

System Level Electronic Design with SystemVue

RF Board Design with ADS, EMPro and Genesys

Impedance Matching Application

PCB Signal Integrity & Power Integrity

consideration with ADS, SIPro and PIPro
Signal Integrity
Power Integrity
RF Board Design
Front-end & Back-end design with ADS
Schematic entry & simulation
Tuning, Optimisation, Monte Carlo

Layout editing

3D Electromagnetic Co-simulation

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 ADS - Advanced Design System
Premier High-Frequency & High-Speed Design Platform
Schematic Entry
RF Layout and Verification ADS helps designers fully characterize,
Data Display and Post Processing optimize and produce designs.
Industry leading simulation technology
Tuning/Optimization & Statistical
design
3D planar & full 3D EM field solvers
Best and broadest selection of
Foundry developed PDKs & SMD
libraries
Design Flow Integration with Cadence,
Mentor, Zuken, Intercept,
X-parameter model generation from
circuit schematic and Keysight's
NVNA
Wireless Libraries enable design and
verification of designs to emerging
wireless standards

Page 17
ADS & EMPro RF Design Environment

ADS Platform EMPro Environment

Electromagnetic Co-simulation

EMDS AMDS

Momentum FEM FDTD

Simulator Simulator Simulator
Method of Moments Finite Element Method Finite Difference
Time Domain

Page 18
 EMPro ADS Common Database
Integration improves your productivity.
ADS Layout (3D View)
Common Database

EMPro 3D Design

ADS Schematic

EMPro projects now saved as ADS libraries

3D models now directly available in ADS as schematic and layout views
Changes made in EMPro dynamically update in ADS
Parameters created in EMPro available in ADS for EM sweep/optimization

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Impedance Matching Application

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 Designing with Off-The-Shelf components For IoT
Impedance Matching for Sub 1GHz Frequency (Sub 1 GHz) and
Narrow Bandwidth (200 kHz), e.g. ZigBee, SIGFOX, LoRa, Weightless

Matching Chipset to Antenna

Impedance Antenna IoT Module

Chipset Matching

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Designing with Off-The-Shelf components For IoT
Impedance Matching for 802.15.4 Frequency (2.4 GHz) and Broader
Bandwidth (20MHz)

Matching Chipset to Amplifier to Antenna

Impedance Impedance IoT Module

Chipset Amplifier Antenna
Matching Matching

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Impedance Matching Applications

RF and Microwave Design

Impedance matching for power transfer, low noise, gain and
efficiency. You are here because you want to do this better.

Internet of Things IoT

Lots of gadgets with antennas to match to IoT chips
Economic and easy to realize

5th Generation Wireless

Broad band matching
Multi-antenna matching

RF chipset integration
Reference design for demanding clients

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 Impedance Matching Network Design
Increasing Levels of Difficulty
1-Stage Matching
Network

Zsource Zload

Input Output
2-Stage
Matching Network Matching Network

Zsource Zload
3-Stage

Antenna
Input Interstage Output
Matching Matching Matching
Network Network Network

Zload

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 Putting Impedance Matching Synthesis to Work

Antenna
Complex RLC equivalent circuit
R=72 , C=10pF, L=0.405nH, Fc= 2.5GHz

Input Interstage Output

Matching Matching Matching
Network Network Network
2 port
Zload
2 port
S-parameters S-parameters 50
+ stabilizing
circuit for
unconditional
stability

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 Automatic Impedance Matching Synthesis
Quickly design impedance matching for economic
and practical implementation

4. Matching
networks
1. Define Freq and synthesized
BW to do in seconds
Impedance Match 5. Quality of
match is
2. Browse to S-, X or Sys- automatically 6. Experiment with
parameters of Chip, Amplifier and optimized lumnped / distributed
Antenna that needs matching matching for economy
3. Select matching topology-
simpler is cheaper to realize

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Automatic Impedance Network Synthesis Demo

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Synthesized Input, Interstage and Output
Distributed Matching networks
TRL matching network

Synthesized Microstrip matching schematic from above TRL network

Microstrip matching layout

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Microstrip Layout Realization Demo

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A New cohesive
flow for Signal &
Power Integrity
Outline Page 31

System Level Electronic Design with SystemVue

RF Board Design with ADS, EMPro and Genesys

Impedance Matching Application

PCB Signal Integrity & Power Integrity

consideration with ADS, SIPro and PIPro
Signal Integrity
Power Integrity
 ADS: SIPro and PIPro
A Cohesive Workflow for SI and PI Analyses
Layout Import into ADS Transient Convolution
(Direct *.brd Import, Allegro ADFI SIPro / PIPro Analysis Channel Sim
or ODB++ flow) DDR Bus Sim

Layout

ADS Schematic

Set up and run analyses

Manage nets, VRMs, sinks,

components

3D layout view and results

visualization

4 New EM Simulators

PI-DC PI-AC Power Plane Power-Aware Signal

IR Drop PDN Impedance Resonances Integrity

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 Increased Productivity for Post-layout Analysis
Seamless flow from EM-analyses back into schematic for both SI and PI
Decap Tuning, Optimization,
Circuit-level VRM modeling

Channel simulation
and
Transient simulation

I/O SSN Analysis

ports Automated
Sub-circuit
Generation
Automated
Test Bench
Generation
Data with VCC Bounce

DDR4
Low BER
PDN Impedance Simulation And
More
Simulation!

Compliance
Test

S-parameter Extraction

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Outline Page 34

System Level Electronic Design with SystemVue

RF Board Design with ADS, EMPro and Genesys

Impedance Matching Application

PCB Signal Integrity & Power Integrity

consideration with ADS, SIPro and PIPro
Signal Integrity
Power Integrity
 SIPro
Simulation Technology Overview

A composite technology of fast FEM + Planar EM

Speed and Accuracy

Power-Aware A purely EM-based simulation, capturing more EM

Signal Integrity effects than 2D-hybrid solutions

SI-specific, net-driven use-model and flow

Easily plot Transmission, Return loss, Xtalk

and TDR/TDT

Automatic-schematic generation

EM model flows back to schematic ready for further

simulation with Transient, Channel Sim, DDR Bus
Sim and more

Power-Aware
Signal Integrity

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SIPro
Simulation technology comparison for high-speed digital PCBs

Speed/Capacity

40GHz

Full-Wave 3D EM
Frequency

20GHz

3D-Planar EM
10GHz
New Technology
Area
5GHz
Hybrid
2D Tline
+ FEM

Accuracy

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 SIPro: Speed and Accuracy
Xilinx KCU105 FPGA Platform Board

Example : SFP (Small Form Factor Pluggable) TX channel

Very good agreement!

SIPro finished in 18 min, a fraction of simulation time compared to FEM

SIPro: 1GB memory, 6 secs per frequency point

FEM:8GB memory, 12 mins per point

Page 38
 SIPro: Accuracy
DDR4 DQ Channel, Measured vs SIPro Measurement: Courtesy
of GigaTest Labs

28-layer Xilinx UC1650B DDR4 memory characterization board

DDR4_C2_DQ4 single ended line (cookie cut)

DDR4_C2_DQ4, Single Ended

2431 mil path length

(~4.12 @ 20GHz or 2 with Er=4)

Er as specified by
the designer,
not as fabricated

Red = SIPro Black = Measured

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 SIPro: SI-specific use-model and flow
Layout to results in less than 20 clicks

No layout simplification
required!

Net-driven

Guided port creation

Quickly plot all crosstalk

elements from the same
component

Easily plot
TDR/TDT

Mixed-mode
S-parameters

Page 40
Outline Page 41

System Level Electronic Design with SystemVue

RF Board Design with ADS, EMPro and Genesys

Impedance Matching Application

PCB Signal Integrity & Power Integrity

consideration with ADS, SIPro and PIPro
Signal Integrity
Power Integrity
The Power Distribution Network
Why doing a PDN analysis?
VRM
Sinks
1.2V Power Rail
1.189V

Ground Rail
0.002V

Roles of the PDN (Source: Signal and Power Integrity Simplified, Second Edition, Eric Bogatin)
Keep a constant supply voltage on the pads of the chips, from DC up to the bandwidth of
the switching current.

Carry the return currents for the signal lines and avoid these overlap. The latter causes
ground bounce or simultaneous switching noise (SSN).

Seen the PDN has the largest size, carries the highest currents including HF noise, it has
the potential of creating most radiated emissions.

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PIPro
Simulation Technology Overview
PIPro has an efficient net-driven PI analysis setup with 3 new simulator engines

Speed and Accuracy

PI-specific net-driven use-model and flow

Change decap values/models without

needing to re-simulate

Automatic-schematic generation

EM model flows back to schematic ready for

further simulation with behavioral and circuit-
level simulations of VRMs, sinks and more

PI-DC Power Plane

IR Drop Resonances

PI-AC
PDN Impedance

Page 43
 PIPro: Accuracy
Customer validated test-case, Simulation vs.
Measured Data
Bare-Board PDN populated with Decaps
1
2 10
10 measurement measurement
PIPro
PiPro PIPro
PiPro
1
10 0
10
Z11 [Ohm]

Z11 [Ohm]
0 Customer used ideal cap
10
values with no ESR specified,
-1 hence sharp resonances.
10
-1
10

-2 -2
10 -2 -1 0
10 -2 -1 0
10 10 10 10 10 10
Frequency [GHz] Frequency [GHz]
Ideal VRM model.
Test case: Customer did not have IC data.
ATE test card PDN traverses many layers

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Designed for Usability

Filter by Net Filters

Filter by Component

Right-click to add-to- Context

sensitive menus

analysis

Drag & Drop

Hierarchical search for

Easily copy
complex selections setups from one
analysis to 3D Layout View
another

Context sensitive menus

e.g. Select instances
connected to ONLY the Color coded
Nets
selected nets

Page 45
 PIPro DC IR Drop

Sink : U63
1.1479 V
Vdrop= 53 mV

Sink : U62
1.14745 V
Vdrop= 52 mV Voltage and current reported per Via, Sink, VRM
and more!

VRM: U4
1.2 V Power Dissipation
and Current Density
visualization

Sink : U61
1.14747 V
Vdrop= 52 mV

Sink : U60
1.14755 V
Vdrop= 52 mV Xilinx KCU105 VCC1V2 PDN

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 PIPro AC PDN Impedance Analysis
Component Model assignment:
Lumped
SnP
Murata
Samsung
TDK
Create custom parts from
Voltage, current and Power Loss Density Plots Schematic models

Easy setup:
Filter, drag and Drop
Components

+ Full scripting support for setup, simulation and post-processing

Page 47
PIPro AC PDN Impedance Analysis
Decap Selection in PIPro

Analyze effect of decap

Voltage, current and Power Loss Density Plots model changes without any
need to re-simulate

Original PDN
Impedance
New Model
Selected

Page 48
 PIPro AC PDN Impedance Analysis
Decap tuning from schematic
Top-level Model

VRM Choke

VRM

Memory-1

Memory-2
Decaps

Memory-3

Memory-4

Controller

Values Tuning
From PIPro Completely
PCB Model flexible PDN
optimization
One Group of Decaps

strategy

Page 49
PIPro The power of the workflow
Including the DC-DC converter in the Simulation

Behavioral representations of
VRM together with EM-model of
the PDN, to analyze true
performance with feedback

Circuit-level modeling for Power

Supply design

Page 50
PIPro Power Plane Resonance Analysis
Self resonances

Analyze self-resonances
of the PCB and inspect
trouble areas that have the
highest field strength

Page 51
ADS 2016: SIPro / PIPro New Features

SIPro: Innovative new composite EM technology

Speed and Accuracy
A cohesive workflow for SI and PI analyses

Software
People
Hardware

Page 52
Keysight Training Services
Build new skills. Extract more value

Enable your teams to achieve the mastery necessary to use their design
software to its fullest potential

Access a comprehensive portfolio of technical training courses

Utilize modular materials that focus on developing expertise in specific

instruments, technologies or software tools

www.keysight.com/find/Training

Page 53
Keysight EEsof EDA
Your software partner for IoT development

Final
Packaging, Product
Antenna
RF Board
Integration
RFIC
Design &
Module
System
Concept

Page 54