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Active Source Current Filtering to Minimize the

DC-Link Capacitor in Switched Reluctance Drives


Annegret Klein-Hessling, Bernhard Burkhart, Rik W. De Doncker
Institute for Power Electronics and Electrical Drives (ISEA), RWTH Aachen University
Jaegerstrasse 17/19, 52066 Aachen, Germany
post@isea.rwth-aachen.de http://www.isea.rwth-aachen.de

AbstractSwitched reluctance machines receive increased at- In addition, the use of a boost converter might have ad-
tention by the automotive industry because of their cost efficiency. vantages because it is able to eliminate the effects of a
However, the comparatively larger inverter is a disadvantage of dc-link voltage level variation due to the battery state of
this machine type. This paper evaluates the effects of the usage
of a dc-dc converter to reduce the size of the dc-link capacitor by charge (SOC) [3]. Common 400 V automotive batteries suffer
active filtering of the source current. The active filter is compared a voltage drop of around 100 V in the discharge state. On
to a passive filter. Besides, the influence of a variable dc-link SRMs in single-pulse operation this might have a considerable
voltage level on the machine is investigated. effect on the machine efficiency.
II. ACTIVE F ILTERING U SING A DC-DC C ONVERTER
I. I NTRODUCTION
An equivalent circuit model of the proposed filter topology,
Switched reluctance machines (SRMs) need a comparatively the battery, the cable and the SRM inverter is shown in Fig. 1.
large dc-link capacitor to smoothen the dc-link voltage due The battery is modeled as an ideal voltage source ubat and
to the high amount of magnetization energy that oscillates an internal resistance Ri,bat . The cable which connects the
between the dc-link and the machine [1]. A high ripple on the battery with the inverter is assumed as series connection of a
dc-link voltage is unwanted to avoid the risk of over voltage resistance Rcable and an inductance Lcable . The SRM inverter
across the semiconductor. A ripple on the dc-link voltage also consists of a dc-link capacitance CDC and an asymmetric half
results in a source current ripple, if the dc-link is directly bridge with the switches S1 and S2 .
connected to a voltage source (e.g. a battery). This current The dc-dc converter consists of two switches SDC,1 and
ripple produces ohmic losses on the internal resistance of the SDC,2 , an inductance LDC and an input capacitance Cin . The
source. For a 20 kW-SRM in an automotive application these depicted dc-dc converter in Fig. 1 is a boost converter, hence
losses can reach a few hundreds watts. uin < uDC . To allow the SRM being operated in motor and
A large dc-link capacitor increases the size, weight and generator mode the dc-dc converter has to be bidirectional.
prize of the SRM inverter compared to inverters for conven- When the SRM operates as a motor the current through
tional three phase drives based on an induction machine or the inductor (iL > 0) is controlled with the switch SDC,1 .
synchronous machine. Recent publications recommend phase When the SRM operates as a generator the current (iL < 0)
switching techniques to minimize the size of the dc-link ca- is controllable with the switch SDC,2 . Hence, the energy
pacitor [1], [2]. These switching techniques aim to commutate flow between the battery and the dc-link capacitor can be
the magnetization energy stored in one phase to the next active controlled.
phase without buffering it in the dc-link capacitor. However The aim of the boost converter is to supply the SRM
the switching techniques assume an overlap between the SRM converter with a reference dc-link voltage uDC and simulta-
phases. This assumption is only fulfilled by SRMs with at least
three phases. Additionally, the current in the SRM has to be
still active controllable. Therefore, these switching techniques
are not applicable for a two-phase SRM and/or an SRM in
single-pules operation.
[2] additionally proposes a passive input filter to reduce
the ripple on the source current. The presented passive input
filter consists of an inductance LDC and a dc-link capacitance
CDC .
The active filter proposed in this paper is a bidirectional dc-
dc boost converter. The converter switches allow to actively
control the current between the dc-link and the voltage source
and, therefore, the switches are reducing the ripple on the
source current. Fig. 1. Equivalent circuit of SRM with proposed active filter
neously filter the source current ibat . Filtering of the source For simplification voltage drops across the switches and
current means holding the current through the inductor iL diodes are not considered in the shown equation but used in
on a nearly constant level and therefore suppress greater the controller. The duty cycle for in the next PWM step k + 1
oscillation on the source current. This can be achieved by can be determined by solving the equation for d. As mentioned
controlling the average dc-link voltage uDC instead of the before, only one switch of the bidirectional dc-dc converter is
instantaneous dc-link voltage uDC . In a stationary operating controlled. For a positive current iL the duty cycle d is > 0
point the instantaneous dc-link voltage then is periodic with and is applied on SDC,1 . Vice versa, in the case of a negative
the electric frequency of the SRM times the number of SRM current the switch SDC,2 has to be used and the calculated
phases. duty cycle is < 0.
The control of the dc-link voltage is shown in Fig. 2. At
The usage of the measured voltages uin (k) and udc (k) at
the start of each voltage period the average reference dc-link
the end of the last PWM step k is another simplification. It
voltage uDC is compared with the actual average voltage of the
assumes that the voltages between two PWM steps do not vary.
last period uDC . The difference is the input to a PI-controller
This does not necessary apply for the dc-link voltage. The
which provides the reference value for the inductor current
difference between udc (k) and udc (k + 1) depends on CDC
iL . Afterwards a current controller determines the switching
and the length of the PWM period T . To improve the PWM
signals for the boost converter.
current controller the voltage udc (k+1) can be predicted. With
The current through the inductor can either be controlled by
this an average voltage within the PWM step can be calculated
hysteresis control or pulse-width modulation (PWM). Figure 3
and used in (2).
depicts the two approaches. For hysteresis control only the
instantaneous current iL is required. Dependent on the current The PWM current controller provides a constant switching
the states of the switches are chosen. Therefore the switching frequency. At the same time compared to the hysteresis
frequency is not constant. The maximal switching frequency approach the measurement and calculation effort for the in-
depends on the hysteresis width I, the boost inductance LDC stantaneous values is higher. Additionally, the ripple on the
and the voltages uDC and uin . current is not constant.
For the PWM approach before each PWM period T the duty
To reduce the current through the inductor and increase
cycle d has to be calculated. The current through an inductor is
the effective total switching frequency it is possible to use
determined by the integration of the voltage across it divided
an interleaved dc-dc converter [4]. The interleaved dc-dc
by its inductance:
converter consists of multiple single dc-dc converter connected
Zt in parallel as depicted in Fig. 4.
1
iL (t) = iL (t0 ) + uL ( ) d (1) For an interleaved dc-dc converter the PWM current control
LDC
t0 approach is recommended. When phase shifting the PWM
With this equation the predicted current in the next discrete periods of each individual phase one to each other, the total
PWM step k + 1 can be determined. switching frequency of the converter can be increased by
keeping the switching frequency of each phase unchanged. In
iL (k + 1) contrast, when applying a hysteresis current controller to each
dT (1 d)T phase, due to the variable switching frequency, the positive and
iL (k) + uin (k) + (uin (k) uDC (k)) (2) negative peaks of the single phases do not necessarily overlap
LDC LDC
each other.

Fig. 2. Control of average DC-link voltage with active filter

(a) Hysteresis control (b) Center aligned PWM control


Fig. 3. Approaches for current controller Fig. 4. Equivalent circuit of active filter with interleaved dc-dc converter
III. S IMULATION R ESULTS a dc-link capacitance of Cdc = 1 mF experience a similar
voltage ripple of approximately 20 %. Due to the 2-phase SRM
For the comparison of the different topologies simulations
the ripple appears twice per electric period of the SRM.
are carried out using MATLAB Simulink [5] coupled with
Since the active filter is a dc-dc boost converter the average
PLECS [6]. The SRM is modeled by look-up tables obtained
dc-link voltage of the active filter (uDC = 335 V) is higher
from a stationary 2D finite element analysis (FEA)
than the voltage of the other topologies. The filter ability of
A 2-phase SRM with rated speed of 7500 rpm at 22 kW the dc-dc converter can only be used if udc > uin . Otherwise,
for a range extender application is used. Therefore, the SRM the diode of switch SDC,1 conducts and the current iL is no
operates as a generator and the source current is negative. The longer actively controllable.
rated dc-link voltage of the SRM is 300 V. At rated speed the The ripple on the dc-link voltage has only a slight influence
SRM operates in single-pulse operation [7]. on the SRM behavior. Due to the higher voltage at the
The active filter is compared to two topologies: a con- unaligned position ( = 180 el) the phase can be magnetized
ventional dc-link capacitor and a passive filter as presented a little faster. The influence of the average dc-link voltage level
in [2]. The passive filter consists of a dc-link capacitor and an on the SRM behavior will be discussed in section III.B.
inductor in series with the cable connecting the battery and
the SRM inverter. For all topologies a real cable and a battery A. Influence of Different Operating Points
with an internal resistance are modeled. The passive filter is designed for one specific operating
The comparison of the resulting battery currents ibat and point. In this paper for a better comparison between the
the dc-link voltages udc for the rated operation point of the topologies the passive filter is designed for the rated operating
SRM is shown in Fig. 5. It depicts the simulation results for point of the SRM. In [2] a design for the worst operating
two dc-link configurations: reduced capacitance (Cdc = 1 mF) point is recommended. For the observed SRM in this paper
and needed capacitance (Cdc = 5 mF). Only the larger dc-link this operating point would be at low speed and high power.
capacitance suppresses the battery current reversal. The ripple The design for this point would result in a big value for the
on the current however is still around 75 %. inductance or the capacitance. A big inductance limits the
The passive filter is able to reduce the current ripple with dynamic behavior of the SRM, e.g. during speed up. Fast
the reduced capacitance of Cdc = 1 mF to the same level as changes of the SRM load are no longer possible because of
a 5 mF dc-link capacitance without any filter. The active filter the slower current gradient (diL/dt 1/LDC ).
decreases the current ripple on the battery current even further. A comparison of the resulting battery current ibat and the
In this simulation an active filter with two dc-link phases is dc-link voltage udc for two different speeds for the passive and
used. In this case the dc-dc converter and the SRM inverter the active filter is displayed in Fig. 6. The mechanical input
can be build up using two B6 modules. For the dc-dc converter power of the switched reluctance generator for all operating
the PWM current control is applied. points is 22 kW. It can be seen, that in case of the passive
The comparison of the dc-link voltages shows that only the filter the current ripple increases with decreasing speed. At
topology with the big capacitance reduces the ripple to about 4500 rpm the peak current reaches up to 0 A while the peak-
4 % of the average voltage uDC = 310 V. All topologies with to-peak ripple is about 200 % of the average source current.

50 0
Current ibat in A
Current ibat in A

0 no filter:
CDC = 1 mF 50
50
no filter: 100
100
CDC = 5 mF
150 150 passive filter: 4500 rpm
passive filter: 7500 rpm
0 90 180 270 360 passive filter: 0 90
CDC = 1 mF active filter: 4500 rpm
LDC = 100 H active filter: 7500 rpm
Voltage uDC in V
Voltage uDC in V

350
350
325 active filter:
CDC = 1 mF
300 LDC = 100 H 300
Cin = 0.1 mF
275 250
0 90 180 270 360 0 90 180 270 360
Electrical Position in el Electrical Position in el

Fig. 5. Influence of different filters on source current and dc-link voltage at Fig. 6. Influence of variable speed on active and passive current filter at
mechanical input power Pmech = 22 kw and speed n = 7500 rpm mechanical input power Pmech = 22 kW
The same simulations are carried out for the active filter. The SRM losses are determined by a coupled 2D-FEA sim-
In this case the different operating points have no influence ulation using MATLAB Simulink [5] and FLUX 2D [10]. The
on the ripple of the battery current. The battery current stays simulation considers copper losses Pcu including eddy current
nearly constant for both speeds. The ripple in the dc-link losses in the windings [8] and iron losses Pfe in the rotor
voltage is affected similar for both filters by the different and stator [11]. Due to the non-sinusoidal flux waveforms for
operating points. Therefore, the big advantage of the active the iron loss calculation the improved generalized Steinmetz
filter compared to the passive filter is, that its behavior and equation (iGSE) is used [12].
filter capability is independent of the operation point. The losses in the semiconductor of the SRM inverter Pinv
are calculated according to data sheets provided by the manu-
B. Influence of DC-Link Voltage on SRM facturer. Switching and conduction losses in the switches and
diodes are considered. The modeled SRM inverter is based on
Besides filtering the source current, the dc-dc converter can HybridPACK Light IGBT modules provided by Infineon [13].
be used to adjust the dc-link voltage level. The average dc-link The resulting total losses of the SRM and the SRM inverter
voltage has an influence on the phase current iph and the phase for the rated operating point at a mechanical input power of
flux linkage ph of the SRM. Both values are important for 22 kW and 7500 rpm are shown in Fig. 8. The copper and
the losses occurring in the SRM and, therefore, the efficiency the inverter losses are strongly dependent on the rms current
of the drive system. and, therefore, are reduced by higher voltages. The iron losses
Figure 7 shows the effect of the different dc-link voltages depend on the peak flux-linkage and the gradient of the flux
on the trajectories of phase current and phase flux-linkage for linkage d/dt. According to the observation from Fig. 7 the
one electrical period at the rated operating point (7500 rpm, iron losses increase with increased dc-link voltage level.
22 kW). The SRM is rated for a battery with a voltage of 300 V. In total the overall losses decrease with an increasing dc-
The minimum voltage at a low SOC level is assumed to be link voltage level. Between 200 V and 300 V the efficiency
200 V. 400 V is assumed to be the maximum boosted voltage improves by 1.6 % and stays nearly constant up to 400 V
of the dc-dc converter. Each operating point is optimized for when exceeding 300 V. If only the SRM and its inverter are
the best efficiency as presented in [9]. The gradient of the flux considered it is recommended to operate the SRM at a dc-link
linkage is proportional to the dc-link voltage. Therefore, the voltage of 300 V or higher.
conduction time per period increases with decreasing dc-link
voltages. The efficiency optimization of the parameters results C. Influence of DC-Link Voltage on DC-DC Converter
in an increased free-wheeling time with increasing the dc-link Similar to the SRM and its inverter the efficiency of the
voltages. dc-dc converter also depends on the choice of the average dc-
Due to the efficiency optimization the peak value of the link voltage. As visible in (2) the current through the inductor
phase currents remain nearly constant for the different voltage depends on the input voltage uin and the difference between
levels. The rms value of the phase current however increases the input voltage and the dc-link voltage u = uin uDC .
for decreased dc-link voltages, as a longer conduction time is The inductor current and dc-link voltage trajectories for
required. a battery voltage of ubat = 200 V at 22 kW and 7500 rpm
for different levels of average dc-link voltages are shown in
400
Fig. 9. The PWM current control approach with a switching
frequency f = 15 kHz for all cases is chosen.
Current iph in A

300 udc = 400 V


udc = 300 V
200 udc = 200 V
100
2000 Pinv
0
Pfe
0 90 180 270 360 1500
Losses P in W

Pcu
Flux Linkage ph in Vs

0.1 1000

0.05 500

0
0
0 90 180 270 360 200 250 300 350 400
Electrical Position in el
DC-Link Voltage UDC in V

Fig. 7. Phase current and flux-linkage trajectories for different dc-link voltages
at mechanical input power Pmech = 22 kw and 7500 rpm Fig. 8. Influence of different dc-link voltage on SRM losses
The average inductor current iL is independent of the the inductors consist of iron losses and copper losses. For
average dc-link voltage. It is determined by the battery voltage, the simulation, inductors with ferrite cores and litz wire are
the mechanical power of the SRM and the number of dc- considered. The flux density in the inductor is calculated
dc converter phases. The ripple on the current increases with with an analytical approach. Due to the non-sinusoidal current
the voltage difference u because the gradient diL/dt during waveform again the improved generalized Steinmetz equation
the current decreasing time is proportional to this difference. (iGSE) is used [12]. For the copper loss calculation of the
The gradient of the current during the increasing time is windings eddy currents are neglected because litz wire is
proportional to the input voltage (eq. (2)), hence this gradient used. For the considered operating points the copper losses
is constant for all cases. clearly dominate the iron losses. Therefore, the inductor losses
Figure 9 also shows that the ripple on the dc-link voltage increase only slightly with the increasing average dc-link
depends on the average dc-link voltage level. The ripple voltage as the rms inductor current slightly increases with the
decreases at increased voltage levels. higher current ripple.
The resulting inductors losses PL as well as the losses in In total, the losses in the dc-dc converter are mainly de-
the IGBTs and diodes of the dc-dc converter are depicted in termined by the switching losses. The switching losses also
Fig. 10. The semiconductor losses are separated into switching depend on the switching frequency of the converter. Figure 11
losses Psw and conduction losses Pcond . The switching losses shows this dependency for a battery voltage of 200 V and
of the IGBTs depend on the switching frequency, the voltage an average dc-link voltage of 235 V. This average dc-link
across the device and the instantaneous current during turn- voltage is the minimum value for which at ubat = 200 V
on and turn-off. The switching frequency is the same for the necessary condition uDC > uin is always fulfilled. At
all investigated average dc-link voltage levels. The negative around 90 el and 270 el the voltage difference u becomes
current peaks and the voltage difference between input and nearly zero. Therefore, the gradient of the inductor current
dc-link voltage increase for higher average dc-link voltages becomes also very small. This results in reduced switching
(Fig 9). Therefore also the switching losses of the IGBTs losses. Additionally, a decreased switching frequency reduces
increase. the switching losses. The reduction of the switching frequency
The conduction losses are mainly affected by the rms is limited by the saturation of the inductor at the negative peak
current through the semiconductors. The duty cycle determines current.
the ratio of the period in which the switch is closed and current
is conducted through it. The average absolute duty cycle |d| per D. Total Efficiency of the Electric Drive Train
electrical period decreases with increasing the average dc-link At a switching frequency of 6 kHz the efficiency of the
voltage. Therefore, according to the duty cycle the conduction dc-dc converter is above 99 %. Figure 12 presents the total
losses of the IGBT decrease while the conduction losses of losses of the electric drive train comprising a dc-dc converter,
the diode increase for an increasing dc-link voltage. The total a machine inverter and an SRM (solid lines). For each set of
semiconductor losses of the inverter increase for an increased voltage levels (ubat , udc ) the switching frequency is adapted
dc-link voltage. to minimize the dc-dc converter losses without operating the
Similar to the losses in an SRM the losses occurring in inductors in saturation. Additionally, the occurring losses in
the drive train with a big capacitor and without the use of
the dc-dc converter are shown in Fig. 12 (dashed line). The
Current iL in A

25

400
50
Psw,IGBT
75 Psw,diode
udc = 400 V 300
PL
Losses P in W

udc = 350 V
0 90 180 Pcond,diode
udc = 300 V
200 Pcond,IGBT
udc = 250 V
Voltage uDC in V

400
100
300

0
200
250 300 350 400
0 90 180 270 360
Average DC-Link Voltage uDC in V
Electrical Position in el

Fig. 9. Inductor current trajectories for different average dc-link voltages at Fig. 10. Semiconductor losses for different average dc-link voltages at
ubat = 200 V ubat = 200 V
Current iL in A
A range extender in an electric car is mostly operated when
25 the SOC and the battery voltage are at low level. Therefore, it
50
can be assumed that the system efficiency is not reduced with
the additional dc-dc converter.
75
IV. C ONCLUSION
0 90 180 270 360 The investigations in this paper have shown that by using
Electrical Position in el a dc-dc converter it is possible to actively filter the source
400
current. By this measure the size of the dc-link capacitor can
f = 6 kHz
be reduced by 80 %. Contrary to the behavior of a passive
f = 9 kHz
filter, the operating point of the SRM has no effect on the
f = 12 kHz
300 filter quality. Additionally, the investigations have shown that
f = 15 kHz
Losses P in W

the ability of the dc-dc converter to adjust the dc-link voltage


independent of the state of charge of the battery improves the
200 Psw,IGBT
efficiency of the switched reluctance machine and its inverter.
Psw,diode The total efficiency of the electric drive train, therefore,
100 PL remains nearly unchanged despite the extra losses in the dc-dc
Pcond,diode
converter.

0 Pcond,IGBT ACKNOWLEDGMENTS
6 9 12 15 The research was funded by the German Federal Ministry
Switching Frequency f in kHz of Economic Affairs and Energy (BMWi) within the public
project HiREX (FKZ: 01MY14003A). The work was addition-
Fig. 11. Inductor current and total converter losses for different switching ally supported by the German Research Foundation (DFG) as
frequencies at ubat = 200 V and udc = 235 V
part of the post graduate program mobilEM (GRK 1856).
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