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NCP81105, NCP81105H

DrMOS Supporting, 1/2/3


Phase Power Controller
with SVID Interface for
Desktop and Notebook
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VR12.5 & VR12.6 CPU
Applications MARKING
DIAGRAM
The NCP81105 is a DrMOS supporting controller optimized for
1
Intel VR12.5 & VR12.6 compatible CPUs. The controller combines
true differential voltage sensing, differential inductor DCR current NCP
81105
sensing, input voltage feedforward, and adaptive voltage positioning 1 36
AWLYYWWG
to provide accurately regulated power for both Desktop and Notebook
QFN36
CPU applications. The control system is based on DualEdge CASE 485CC
pulsewidth modulation (PWM), to provide the fastest initial response
to dynamic load events plus reduced system cost. The NCP81105 is A = Assembly Location
compatible with DrMOS type power stages such as NCP5367, WL = Wafer Lot
YY = Year
NCP5368, NCP5369 and NCP5338.
WW = Work Week
The NCP81105s output can be configured to operate in single phase G = PbFree Package
during light load operation improving overall system efficiency. A
high performance operational error amplifier is provided to simplify
compensation of the system. Patented Dynamic Reference Injection
ORDERING INFORMATION
further simplifies loop compensation by eliminating the need to See detailed ordering and shipping information in the package
compromise between closedloop transient response and Dynamic dimensions section on page 35 of this data sheet.
VID performance. Patented Total Current Summing provides highly
accurate current monitoring for droop and digital current monitoring.

Features
Meets Intels VR12.5 Specifications Reduced Enable to First SVID Command Latency
Implements VR12.6 PS4 State and SVID Reporting PhasetoPhase Dynamic Current Balancing
Mixed Voltage/Current Mode, Dual Edge Modulation Switching Frequency Range of 280 kHz to 1.5 MHz
for Fastest Initial Response to Transient Loading Starts up into PreCharged Loads while Avoiding False
High Impedance Differential Voltage Amplifier OVP
High Performance Operational Error Amplifier Compatible with DrMOS Power Stages
High Impedance Total Current Sense Amplifier Powersaving Phase Shedding
True Differential Current Sense Amplifiers for Vin Feedforward Ramp Slope Compensation
Balancing Current in Each Phase Pin Programming for Internal SVID parameters
Digital Soft Start Ramp Output Over Voltage Protection (OVP) & Under
Dynamic Reference Injection Voltage Protection (UVP)
Accurate Total Summing Current Amplifier Over Current Protection (OCP)
Lossless Inductor DCR Current Sensing Power Good Output with Internal Delays
Summed, Thermally Compensated Inductor Current This is a PbFree Device
Sensing for Adaptive Voltage Positioning (AVP)
Applications
48 mV/ms Fast Output Slew Rate (NCP81105)
Desktop and Notebook Microprocessors
10 mV/ms Fast Output Slew Rate (NCP81105H)
Programmable Slow Slew Rates as a Fraction of Fast
Slew Rate

Semiconductor Components Industries, LLC, 2013 1 Publication Order Number:


October, 2013 Rev. 2 NCP81105/D
NCP81105, NCP81105H

1.3V
EN 1 ENABLE CSREF
UVLO & EN
VCC 2 COMPARATORS
VSP VSN 36 VSP
VRMP VSP
DIFF
OVP AMP VSN
OVP
THERMAL _
VRHOT# 3 35 VSN
MONITOR
DAC DAC
DAC CSCOMP
34 DIFFOUT
SDIO 4 SVID ENABLE DAC
INTERFACE FEED
ALERT# 5 & LOGIC DRVON FORWARD
SCALING
OCP
SCLK 6
OVP _ 33 FB
ENABLE PS#
+
DATA ERROR
REGISTERS AMP 1.3V
VR READY OVERCURRENT
VR_RDY 8
LOGIC COMPARATORS 32 COMP
CURRENT
ROSC 7 OCP MONITOR
28 IOUT
IOUT
TSENSE 9
MUX Buffer OVERCURRENT
27 ILIM
IMAX 16 PROGRAMMING
(VSP VSN) 26 CSCOMP
INT_SEL 17 ADC
IOUT ENABLE _ 25 CSSUM
VBOOT 30

DGAIN 31 PS# + 24 CSREF


CURRENT
OSCILLATOR SENSE OVP
VRMP 29 AMP MAX
& RAMP
VRMP OVP
GENERATORS
VRMP
23 CSN2
COMP
CURRENT 22 CSP2

BALANCE 21 CSN3
PWM
GENERATORS AMPLIFIERS
20 CSP3
I2
PWM2

PWM3

PWM1

I3 19 CSN1
I1
18 CSP1
DRVON
15 DRVON
PS#
ZERO 11 SMOD
OVP CURRENT
DETECTION 14 PWM1
OCP
DRVON

PS# 13 PWM3
POWER
STATE 12 PWM2

NCP81105 GATE
10 OD#

Figure 1. Block Diagram

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2
NCP81105, NCP81105H

DIFFOUT

VBOOT
DGAIN
COMP

VRMP

IOUT
VSN
VSP

FB
36

35

34

33

32

31

30

29

28
EN 1 27 ILIM

VCC 2 26 CSCOMP

VRHOT# 3 25 CSSUM

SDIO 4 24 CSREF
NCP81105
ALERT# 5 23 CSN2
TAB: GROUND
SCLK 6 22 CSP2

ROSC 7 21 CSN3

VR_RDY 8 20 CSP3

TSENSE 9 19 CSN1
11
10

12

13

14

15

16

17

18
DRVON
OD#

IMAX
SMOD

PWM2

PWM3

PWM1

INT_SEL

CSP1
Figure 2. Pin Connections
(Top View)

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3
NCP81105, NCP81105H

PIN LIST AND DESCRIPTION


Pin
No. Symbol Description
1 EN Logic input. Logic high enables the NCP81105 and logic low disables it.
2 VCC Power for the internal control circuits. A decoupling capacitor must be connected from this pin to ground.
3 VR_HOT# Open drain (logic level) output for overtemperature reporting. Low indicates high temp.
4 SDIO Bidirectional Serial VID data interface.
5 ALERT# Open drain Serial VID ALERT# output.
6 SCLK Serial VID clock input.
7 ROSC This pin outputs a constant current. A resistance from this pin to ground programs the switching fre-
quency.
8 VR_RDY Open drain output. High indicates that the NCP81105 is regulating the output.
9 TSENSE Temperature sense input.
10 OD# Phase Disabling Output, tied to the Enable, SMOD or ZCD_EN# pin of phases 2 and 3 DrMOS. Except
in PS0 mode, this output pulls low to disable the DrMOS if connected to an enable input. If connected to
a DrMOS SMOD or ZCD_EN# input, both HS & LS FETs are held off since PWM2 & PWM3 are also low.
Actively pulls high in PS0 mode.
11 SMOD Phase 1 Zero Cross Detection (ZCD) disable output. In PS2 & PS3, SMOD pulls LOW when phase 1
inductor current is negative to perform (or allow the DrMOS ZCD function to perform) diode emulation,
and pulls HIGH when phase 1 inductor current is positive. In PS0 & PS1, SMOD stays high to force the
phase 1 DrMOS into Continuous Conduction.
12 PWM2 PWM output to Phase 2 DrMOS
13 PWM3 PWM output to Phase 3 DrMOS
14 PWM1 PWM output to Phase 1 DrMOS
15 DRVON Enable output for DrMOS
16 IMAX During startup, a resistor from this pin to ground programs ICC_MAX.
17 INT_SEL During startup, a resistor from this pin to ground programs the low frequency compensator pole of the
NCP81105 voltage control feedback loop.
18 CSP1 Positive input to phase 1 current sense amplifier for balancing phase currents
19 CSN1 Negative input to phase 1 current sense amplifier
20 CSP3 Positive input to phase 3 current sense amplifier for balancing phase currents
21 CSN3 Negative input to phase 3 current sense amplifier
22 CSP2 Positive input to phase 2 current sense amplifier for balancing phase currents
23 CSN2 Negative input to phase 2 current balance sense amplifier
24 CSREF Noninverting input for the total output current sense amplifier. Also, the absolute OVP input.
25 CSSUM Inverting input of total output current sense amplifier.
26 CSCOMP Output of total output current sense amplifier.
27 ILIM Input to program the overcurrent shutdown threshold.
28 IOUT Total current monitor output. A resistor from this pin to ground calibrates SVID output current reporting.
29 VRMP VDC applied to this pin provides feedforward compensation for the pulsewidth modulator. The current
into this pin controls the slope of PWM ramp. A low voltage on this pin will inhibit NCP81105 startup.
30 VBOOT During startup, a resistor from this pin to ground programs the BOOT voltage
31 DGAIN During startup, a resistor from this pin to ground programs the scaling of the output Droop with respect to
the total output current signal produced between CSCOMP and CSREF.
32 COMP Output of the error amplifier.
33 FB Error amplifier voltage feedback input.
34 DIFFOUT Output of the differential remote sense amplifier.
35 VSN Inverting input to the differential remote sense amplifier (VSS sense).
36 VSP Noninverting input to the differential remote sense amplifier (VCC sense).
37 GND Power supply return (QFN Flag)

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NCP81105, NCP81105H

VCIN VIN
BOOT
DRVON
EN
CB1
DRMOS
PWM1 PHASE
PWM
VSWH
SMOD
SMOD

NCP81105
VCIN VIN
BOOT
EN
CB2
DRMOS
PWM2 PHASE
PWM
VSWH
OD#
SMOD

VCIN VIN
BOOT
EN
CB3
DRMOS
PWM3 PHASE
PWM
VSWH

SMOD
COUT

Figure 3. Three Phase Application Diagram

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5
R50 37.4 C56 270pF R43 4.75K
DIFFOUT FB C57
R37 1.00K 10pF CSPP2
DIFFOUT COMP R138 R27
R34 100 100K
DGAIN 10.0K
VSN
C85
VSS_SENSE R12 22nF

Figure 4. Three Phase Control Circuit Application


VBOOT CSN2
C51 10.0
VSENSE R19 RT11
place
R139
1nF close
69.8K 220K CSPP3
VCC_SENSE VSP 100K
NCP81105, NCP81105H

R48 100 R40


to L1 R10
VCCU VRMP 10.0K
VDC
IMON 1.0K C83
ENABLE C82 RCS11 RCS12 R8 22nF
ENABLE C61 CSN3

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0.01uF 73.2K
37
36
35
34
33
32
31
30
29
28

R38 165K
R71 10.0
V_1P05_VCCP V5S R161
0.15uF 23.7K C155
VBOOT
COMP
VSP

VRMP
DGAIN
EPAD
VSN
DIFFOUT

IOUT R140
FB

4.99 1.0K R18 680pF


C79 CSPP1
1uF 1 27 17.4K C156 100K R9
ILIM
R157

R156
R162

R155

75.0
130

130

54.9

EN ILIM

6
VCC 2 26 CSCOMP 68pF
VCC CSCOMP 10.0K
VR_HOT3 U1 25 CSSUM C80
VR_HOT SDIO 4 VRHOT# CSSUM 24 CSREF
SDIO R78 43.2 ALERT_VR 5 SDIO NCP81105 CSREF 23 R185 22nF
ALERT SCLK 6 ALERT# CSN2 22 CSN1
SCLK ROSC 7 SCLK CSP2 21 10.0
VR_RDY 8 ROSC CSN3 20 C66
VR_RDY 9 VR_RDY CSP3 19 10nF
TSENSE CSN1

INT_SEL
R154

DRVON
SMOD
PWM2
PWM3
PWM1
80.6K CSN2

CSP1
IMAX
OD#
CSP2
CSN3
CSP3

10
12
13
14
15
16
17
18
11
TSENSE CSN1
CSP1
RT12 R31 INT_SEL
220K 11.0K C81 IMAX 790kHz switching frequency
place 1nF
DRVON R25 R26 95A maximum output current
PWM1 75.0K 51.1K
close to L1
PWM3 114A current limit
PWM2
SMOD
1.5mOhm loadline
OD# 1.7V boot voltage
VDC V5S VDC
VDC
1

+ C1 C25 C26 C20 + C2 C27 C30 C36


CA1 CB1 R121 CA2 CB2
10uF 10uF 33uF 1k 10uF 10uF 33uF
1uF 1uF 1uF THWN 1uF 1uF 1uF
THWN
2

2
42
14
13
12

10

38

42
14
13
12

10

38
11

11
C37
9
8

9
8

4
V5S C4 V5S
2 2
0.22uF V5S 0.22uF
BOOT

BOOT
VCIN VCIN
VIN
VIN
VIN
VIN
VIN
VIN
VIN
VIN

VIN
VIN
VIN
VIN
VIN
VIN
VIN
VIN
THWN

THWN
3 7 3 7
NC PHASE L1 NC PHASE L2
C5 15 MPCG0740LR12 C44 15 MPCG0740LR12
1uF VSWH 43 120nH VCCU 1uF VSWH 43 VCCU
U2 U3 120nH
VSWH 35 0.7mOhm VSWH 35 0.7mOhm
1 NCP5338 VSWH 34 CSN1 1 NCP5338 VSWH 34
SMOD OD# CSNN2
ZCD_EN# VSWH 33 ZCD_EN# VSWH 33
32 SW1 32 SW2

Figure 5. Three Phase Power Stage Circuit


VSWH VSWH
VSWH 31 VSWH 31
39 VSWH 30 39 VSWH 30
NCP81105, NCP81105H

DRVON DISB# VSWH 29 DRVON DISB# VSWH 29


VSWH CSPP1 VSWH CSPP2
40 40
PWM1 PWM PWM2 PWM
CGND
CGND
CGND

CGND
CGND
CGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND

PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND

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GH

GH
GL

GL
36

41

37

16
17
18
19
20
21
22
23
24
25
26
27
28

36

41

37

16
17
18
19
20
21
22
23
24
25
26
27
28
6

5
Total VCORE Output

7
VDC Capacitor: VCCU
26 X 22uF(0805)
1

C31 C32 C9 LOCATE BETWEEN L2 & L3 (PRIMARY SIDE)


CA3 CB3 + C3
10uF 10uF 33uF + 11 X 10uF(0805)
1uF 1uF 1uF C42 C43 C45 C46 C95 C97 C189 C190 C210 C222
THWN
22uF DNP DNP 22uF 22uF DNP 22uF 22uF 22uF 22uF
2

42
14
13
12

10

38
11

V5S C28
9
8

2 4
0.22uF
BOOT
VCIN
VIN
VIN
VIN
VIN
VIN
VIN
VIN
VIN

THWN
C52 C67 C68 C78 C84 C98 C99 C100 C196
3 7 22uF 22uF 22uF 22uF 22uF 22uF 22uF 22uF DNP
NC PHASE L3
C29 15 MPCG0740LR12
1uF
U4 VSWH 43 120nH VCCU LOCATE BETWEEN L1 & L2 (PRIMARY SIDE)
VSWH 35 0.7mOhm
1 NCP5338 VSWH 34 CSNN3
OD# ZCD_EN# VSWH 33
VSWH 32 SW3 C214 C41 C48 C49 C215 C216 C217 C204 C205 C206 C207
VSWH 31 10uF 10uF 10uF 10uF 10uF 10uF 10uF 10uF 10uF 10uF 10uF
39 VSWH 30
DRVON DISB# VSWH 29
VSWH CSPP3 LOCATE IN CENTER OF SOCKET rPGA989 CAVITY (BOTTOM SIDE)
40
PWM3 PWM

CGND
CGND
CGND

PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
GH

GL
C212 C213 C226 C227 C176 C177 C183 C184 C273 C271 C272
22uF 22uF 22uF 22uF 22uF 22uF 22uF 22uF 22uF 22uF 22uF

36

41

37

16
17
18
19
20
21
22
23
24
25
26
27
28
6

5
LOCATE IN CENTER OF SOCKET rPGA989 CAVITY (PRIMARY SIDE)
R50 37.4 C56 270pF R43 4.75K
DIFFOUT FB C57
R37 1.00K 10pF
DIFFOUT COMP
R34 100
VSN
DGAIN
VSS_SENSE

Figure 6. Two Phase Control Circuit Application


VBOOT
C51
VSENSE R19 R16 RT11
place
R139
1nF close
69.8K 24.9K 220K CSPP3
VCC_SENSE VSP 49.9k
NCP81105, NCP81105H

R48 100 R40


to L1 R10
VCCU VRMP 10.0K
VDC
IMON 1.0K C83
ENABLE C82 RCS11 RCS12 R8 22nF
ENABLE C61 CSN3

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0.01uF 73.2K
37
36
35
34
33
32
31
30
29
28

R38 165K
R71 10.0
V_1P05_VCCP V5S R161
0.15uF 23.7K C155
VBOOT
COMP
VSP

VRMP
DGAIN
EPAD
VSN
DIFFOUT

IOUT R140
FB

4.99 1.0K R18 680pF


C79 CSPP1
1uF 1 27 20.0k C156 49.9k R9
ILIM
R157

R156
R162

R155

75.0
130

130

54.9

EN ILIM

8
VCC 2 26 CSCOMP 68pF
VCC CSCOMP 10.0K
VR_HOT3 U1 25 CSSUM C80
VR_HOT SDIO 4 VRHOT# CSSUM 24 CSREF
SDIO R78 43.2 ALERT_VR 5 SDIO NCP81105 CSREF 23 R185 22nF
ALERT SCLK 6 ALERT# CSN2 22 CSN1
SCLK V5S 10.0
ROSC 7 SCLK CSP2 21
VR_RDY 8 ROSC CSN3 20 C66
VR_RDY 9 VR_RDY CSP3 19 R128 10nF
TSENSE CSN1

INT_SEL
R154 1K

DRVON
SMOD
PWM2
PWM3
PWM1
80.6K CSN2

CSP1
IMAX
OD#
CSN3
CSP3

10
12
13
14
15
16
17
18
11
TSENSE CSN1
CSP1
RT12 R31 INT_SEL
220K 11.0K C81 IMAX 790kHz switching frequency
place 1nF
DRVON R25 R26 55A maximum output current
PWM1 43.2K 51.1K
close to L1
PWM3 66A current limit
SMOD
1.5mOhm loadline
OD# 1.7V boot voltage
VDC V5S
1

CA1 CB1 + C1 C25 C26 C20 R121


10uF 10uF 33uF 1uF 1uF 1uF 1kTHWN
2

Total VCORE Output


42
14
13
12
10

38
11
9
8

V5S C4
2
0.22uF
Capacitor:
BOOT
THWN

VCIN
VIN
VIN
VIN
VIN
VIN
VIN
VIN
VIN

3 7 20 X 22uF(0805)
NC PHASE L1
C5 + 11 X 10uF(0805)
15 MPCG0740LR12
1uF U2 VSWH 43 120nH VCCU
VSWH 35 0.7mOhm
1 NCP5338 VSWH 34 CSN1
SMOD ZCD_EN# VSWH 33
32 SW1
C52 C67 C68 C78 C84 C98 C99 C100 C196
VSWH 22uF 22uF 22uF 22uF 22uF 22uF 22uF 22uF 22Uf

Figure 7. Two Phase Power Stage Circuit


VSWH 31
39 VSWH 30
DRVON DISB# VSWH LOCATE BETWEEN L1 & L2 (PRIMARY SIDE)
NCP81105, NCP81105H

29
VSWH CSPP1
40
PWM1 PWM
CGND
CGND
CGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND

C214 C41 C48 C49 C215 C216 C217 C204 C205 C206 C207
GH
GL

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10uF 10uF 10uF 10uF 10uF 10uF 10uF 10uF 10uF 10uF 10uF
36

41
37
16
17
18
19
20
21
22
23
24
25
26
27
28
6

LOCATE IN CENTER OF SOCKET rPGA989 CAVITY (BOTTOM SIDE)

9
VDC C212 C213 C226 C227 C176 C177 C183 C184 C273 C271 C272
22uF 22uF 22uF 22uF 22uF 22uF 22uF 22uF 22uF 22uF 22uF
1

CA3 CB3 + C3 C31 C32 C9


10uF 10uF 33uF 1uF 1uF 1uF LOCATE IN CENTER OF SOCKET rPGA989 CAVITY (PRIMARY SIDE)
THWN
2

42
14
13
12
10

38
11

V5S C28
9
8

4
2
BOOT
VCIN THWN 0.22uF
VIN
VIN
VIN
VIN
VIN
VIN
VIN
VIN

3 7
NC PHASE L3
C29 15 MPCG0740LR12
1uF U4 VSWH 43 120nH VCCU
VSWH 35 0.7mOhm
1 NCP5338 VSWH 34 CSNN3
OD# ZCD_EN# VSWH 33
VSWH 32 SW3
VSWH 31
39 VSWH 30
DRVON DISB# VSWH 29
VSWH CSPP3
40
PWM3 PWM

CGND
CGND
CGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
GH
GL
36

41
37
16
17
18
19
20
21
22
23
24
25
26
27
28
6

5
R50 37.4 C56 270pF R43 4.75K
DIFFOUT FB C57
R37 1.00K 10pF
DIFFOUT COMP
R34 100
VSN
DGAIN
VSS_SENSE
VBOOT
C51
VSENSE R19 R16 RT11
place
1nF close
69.8K 24.9K 220K
VCC_SENSE VSP
R48 100 R40
to L1
VCCU VRMP
VDC

Figure 8. Single Phase Control Circuit Application


IMON 1.0K
ENABLE C82 RCS11 RCS12
ENABLE C61
0.01uF 73.2K
37
36
35
34
33
32
31
30
29
28

R38 165K R140


R71
V_1P05_VCCP V5S R161
0.15uF 23.7K C155 CSPP1
VBOOT

75.0K
COMP
DIFFOUT

VRMP
DGAIN
VSP
EPAD
VSN

IOUT
FB
NCP81105, NCP81105H

4.99 1.0K R18 680pF


C79 R9
1uF 1 27 8.87K C156
R157

R156

ILIM
R162

R155

75.0

10.0K
130

130

54.9

VCC 2 EN ILIM 26 CSCOMP 68pF


VCC CSCOMP C80
VR_HOT3 U1 25 CSSUM 22nF
VR_HOT VRHOT# CSSUM R185

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SDIO 4 24 CSREF
SDIO R78 43.2 ALERT_VR 5 SDIO NCP81105 CSREF 23 CSN1
ALERT SCLK 6 ALERT# CSN2 22 10.0
SCLK ROSC 7 SCLK CSP2 21 V5S
VR_RDY 8 ROSC CSN3 20 C66
VR_RDY 9 VR_RDY CSP3 19

10
R128 10nF

INT_SEL
R154 TSENSE CSN1 1K

DRVON
SMOD
PWM2
PWM3
PWM1
80.6K CSN3

CSP1
IMAX
OD#
CSN1
10
12
13
14
15
16
17
18
11
TSENSE
CSP1
RT12 R31 INT_SEL
220K 11.0K C81 IMAX 790kHz switching frequency
place 1nF
DRVON R25 R26 32A maximum output current
close to L1 PWM1
PWM3
25.5K 51.1K
39A current limit
PWM2
SMOD
2.0mOhm loadline
OD# 1.7V boot voltage
VDC V5S
1

+ C1 C25 C26 C20 R121


CA1 CB1
1k
10uF 10uF 33uF
1uF 1uF 1uF THWN
2

Figure 9. Single Phase Power Stage Circuit


Total VCORE Output
42
14
13
12

10

38
11

V5S
9
8

2
C4 Capacitor:
NCP81105, NCP81105H

0.22uF
BOOT

VCIN 16 X 22uF(0805)
VIN
VIN
VIN
VIN
VIN
VIN
VIN
VIN

THWN

3 7
NC PHASE L1 + 11 X 10uF(0805)
C5 15 MPCG0740LR12

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1uF VSWH 43 VCCU
U2 120nH
VSWH 35 0.7mOhm
1 NCP5338 VSWH 34 CSN1
SMOD ZCD_EN# VSWH 33
VSWH 32
SW1 C52 C67 C68 C78 C84 C98 C99 C100 C196

11
VSWH 31 DNP DNP DNP 22uF 22uF 22uF 22uF 22uF DNP
39 VSWH 30
DRVON DISB# VSWH 29
VSWH CSPP1 LOCATE NEAR L1 (PRIMARY SIDE)
40
PWM1 PWM
CGND
CGND
CGND

PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
C214 C41 C48 C49 C215 C216 C217 C204 C205 C206 C207
GH

GL

10uF 10uF 10uF 10uF 10uF 10uF 10uF 10uF 10uF 10uF 10uF
6

5
36

41

37

16
17
18
19
20
21
22
23
24
25
26
27
28
LOCATE IN CENTER OF SOCKET rPGA989 CAVITY (BOTTOM SIDE)
C212 C213 C226 C227 C176 C177 C183 C184 C273 C271 C272
22uF 22uF 22uF 22uF 22uF 22uF 22uF 22uF 22uF 22uF 22uF
LOCATE IN CENTER OF SOCKET rPGA989 CAVITY (PRIMARY SIDE)
NCP81105, NCP81105H

ABSOLUTE MAXIMUM RATINGS

ELECTRICAL INFORMATION all signals referenced to GND unless noted otherwise.


Pin Symbol VMAX VMIN ISOURCE ISINK
COMP, CSCOMP, DIFFOUT VCC + 0.3 V 0.3 V 3 mA 3 mA
VSN GND + 300 mV GND 300 mV
VR_RDY VCC + 0.3 V 0.3 V N/A 5 mA
VCC 6.5 V 0.3 V N/A N/A
VRMP +25 V 0.3 V
VR_HOT#, SDIO & ALERT# VCC + 0.3 V 0.3 V 0 mA 30 mA
OD#, SMOD, PWM1, PWM2, VCC + 0.3 V 0.3 V 5 mA 5 mA
PWM3 & DRVON

All Other Pins VCC + 0.3 V 0.3 V


Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.

THERMAL INFORMATION
Description Symbol Typ Unit
Thermal Characteristic RqJA _C/W
QFN36 Package (Notes 1 and 2) 68

Operating Junction Temperature Range* TJ 10 to 125 _C


Operating Ambient Temperature Range 10 to 100 _C
Maximum Storage Temperature Range TSTG 40 to +150 _C
Moisture Sensitivity Level MSL 1
*The maximum package power dissipation must be observed.
1. JESD 515 (1S2P DirectAttach Method) with 0 LFM
2. JESD 517 (1S2P DirectAttach Method) with 0 LFM

ELECTRICAL CHARACTERISTICS (VCC = 5.0 V, VEN = 2.0 V, CVCC = 0.1 mF unless specified otherwise) Min/Max values are valid
for the temperature range 10C TA 100C unless noted otherwise, and are guaranteed by test, design or statistical correlation.

Parameter Symbol Conditions Min Typ Max Unit


VCC INPUT
Supply Voltage Range 4.75 5.25 V
EN = high; PS0, 1, 2 modes 23 29 mA
Quiescent Current EN = high; PS3 Mode 14 17.5 mA
EN = low 30 mA
VCC rising 4.5 V
UVLO Threshold
VCC falling 4.0 V
UVLO Hysteresis 160 mV
VRMP (VIN monitor)
UVLO Threshold VRMP falling 3.0 3.2 3.4 V
UVLO Hysteresis 600 800 mV
Leakage current PS0, PS1, PS2, PS3; VVRMP = 3.2 V 70 mA
Leakage current PS4, VVRMP = 20 V 500 nA
Leakage current VEN = 0 V, VVRMP = 20 V 500 nA
ENABLE INPUT
Enable High Input Leakage Current External 1k pullup to 3.3 V 1.0 mA

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NCP81105, NCP81105H

ELECTRICAL CHARACTERISTICS (VCC = 5.0 V, VEN = 2.0 V, CVCC = 0.1 mF unless specified otherwise) Min/Max values are valid
for the temperature range 10C TA 100C unless noted otherwise, and are guaranteed by test, design or statistical correlation.

Parameter Symbol Conditions Min Typ Max Unit


ENABLE INPUT
Upper Threshold VUPPER 0.8 V
Lower Threshold VLOWER 0.3 V
Total Hysteresis VUPPER VLOWER 300 mV
Time from Enable transitioning HI to when
Enable Delay Time 2.4 ms
DRVON goes high.
SCLK, SDIO, ALERT#
SCLK Input Low Voltage VILSCLK 0.45 V
SCLK Input High Voltage VIHSCLK 0.66 V
SDIO Input Low Voltage VILSDIO 0.42 V
SDIO Input High Voltage VIHSDIO 0.72 V
Hysteresis Voltage (SCLK, SDIO) VHYS 100 mV
Output High Voltage (SDIO, ALERT#) VOH External resistive pullup to 1.05 V 1.05 V
Output Low Voltage (SDIO, ALERT#) VOL Sinking 20 mA 100 mV
Buffer On Resistance (SDIO, ALERT#) RON Measured sinking 4 mA 5 13 W
Leakage Current Pin voltage between 0 and 1.05 V 100 100 mA
Pin Capacitance 4.0 pF
Time between SCLK rising edge and valid
VR clock to data delay TCO 4 8.3 ns
SDIO level
Time before SCLK falling (sampling) edge
Setup time TSU 7 ns
that SDIO level must be valid
Time after SCLK falling edge that the
Hold time THLD 14 ns
SDIO level remains valid
VR12.5 & VR12.6 DAC
1.5 V DAC < 2.3 V, 10C TA 85C 0.5 0.5 %
System Voltage Accuracy 1.0 V DAC < 1.49 V, 10C TA 85C 8 8 mV
0.5 V DAC < 0.99 V, 10C TA 85C 10 10 mV
DAC SLEW RATES (NCP81105)
Soft Start Slew Rate SVID Register 2Ah = default 12 mV/ms
Slew Rate Slow Selectable Fraction of Fast Slew 3 24 mV/ms
Slew Rate Fast 48 mV/ms
DAC SLEW RATES (NCP81105H)
Soft Start Slew Rate SVID Register 2Ah = default 2.5 mV/ms
Slew Rate Slow Selectable Fraction of Fast Slew 15 mV/ms
Slew Rate Fast 10 mV/ms
DIFFERENTIAL SUMMING AMPLIFIER
VSP Input Leakage Current VVSP = 1.3 V 0 15 mA
VSN Bias Current 0.3 V VVSN 0.3 V 1 1 mA
DVID UP Feedforward Charge 0.3 V VVSN 0.5 V 6.8 pC
Charge per 5 mV DAC increment
VSP Input Voltage Range 0.3 3.0 V
VSN Input Voltage Range 0.3 0.3 V
3dB Bandwidth CL = 20 pF to GND, RL = 10 kW to GND 10 MHz
DC gain VSx to DIFFOUT VSP VSN = 0.5 V to 2.3 V 1.0 V/V

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NCP81105, NCP81105H

ELECTRICAL CHARACTERISTICS (VCC = 5.0 V, VEN = 2.0 V, CVCC = 0.1 mF unless specified otherwise) Min/Max values are valid
for the temperature range 10C TA 100C unless noted otherwise, and are guaranteed by test, design or statistical correlation.

Parameter Symbol Conditions Min Typ Max Unit


DIFFERENTIAL SUMMING AMPLIFIER
Maximum Output Voltage ISOURCE = 2 mA 3.0 V
Minimum Output Voltage ISINK = 2 mA 0.5 V
ERROR AMPLIFIER
Input Bias Current VFB = 1.3 V; Internal integrator active 25 25 mA
CL = 20 pF to GND,
Open Loop DC Gain 80 dB
RL = 10 kW to GND
CL = 20 pF to GND,
Open Loop Unity Gain Bandwidth 20 MHz
RL = 10 kW to GND
DVin = 100 mV, G = 10 V/V,
Slew Rate DVout = 1.5 V 2.5 V, 20 V/ms
Load = 20 pF to GND + 10 kW to GND
Maximum Output Voltage ISOURCE = 2.0 mA 3.5 V
Minimum Output Voltage ISINK = 2.0 mA 1 V
VR_RDY (Power Good) OUTPUT
Output Low Saturation Voltage IVR_RDY = 4 mA 0.3 V
1 kW external pullup to 3.3 V,
Rise Time 100 ns
CTOT = 45 pF
1 kW external pullup to 3.3 V,
Fall Time 10 ns
CTOT = 45 pF
Output Voltage at Powerup VR_RDY pulled up to 5 V via 2 kW 1.0 V
Output Leakage Current When High VR_RDY = 5.0 V 1.0 1.0 mA
VR_RDY Delay (rising) DAC = TARGET to VR_RDY high 5.5 6 ms
VR_RDY Delay (falling) From OCP or OVP to VR_RDY low 5 ms
OUTPUT OVER VOLTAGE & UNDER VOLTAGE PROTECTION (OVP & UVP)
Absolute Over Voltage Threshold
2.8 2.9 3.0 V
During SoftStart
Over Voltage Threshold Above DAC VSP rising 350 400 425 mV
Over Voltage Delay VSP rising to PWMx low 50 ns
Under Voltage Threshold Below DAC VSP falling 300 mV
Undervoltage Delay 5 ms
CURRENT BALANCE AMPLIFIERS
Input Bias Current (after phase
CSPx = CSNx = 1.7 V 50 50 nA
detection)
Common Mode Input Voltage Range CSPx = CSNx 0 2.3 V
Differential Mode Input Voltage Range CSNx = 1.7 V 100 100 mV
Closed loop Input Offset Voltage CSPx = CSNx = 1.7 V,
1.5 1.5 mV
Matching Measured from the average offset
Amplifier Gain 0 V < CSPxCSNx 0.1 V 5.7 6.0 6.3 V/V
Gain Matching 10 mV CSPxCSNx 30 mV 3 3 %
3 dB Bandwidth 8 MHz
1 & 2 PHASE DETECTION
CSN Pin Resistance to Ground During phase detection only 50 kW
CSN Pin Threshold Voltage 4.5 V
Time from Enable transitioning HI to
Phase Detect Timer 3.5 ms
removal of phase detect resistance

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NCP81105, NCP81105H

ELECTRICAL CHARACTERISTICS (VCC = 5.0 V, VEN = 2.0 V, CVCC = 0.1 mF unless specified otherwise) Min/Max values are valid
for the temperature range 10C TA 100C unless noted otherwise, and are guaranteed by test, design or statistical correlation.

Parameter Symbol Conditions Min Typ Max Unit


CURRENT SUMMING AMPLIFIER
Offset Voltage VOS VCSREF = 1.0 V 300 300 mV
CSSUM Input Bias Current CSSUM = CSREF = 1 V 7.5 7.5 nA
CSREF Input Bias Current CSSUM = CSREF = 1 V 0 4.25 mA
Open Loop Gain 80 dB
Current Sense Unity Gain Bandwidth CL = 20 pF to GND, RL = 10 kW to GND 10 MHz
Max CSCOMP Output Voltage Isource = 2 mA 3.5 V
Isink = 500 mA 100 mV
Minimum CSCOMP Output Voltage
Isink = 25 mA 7.0 30 mV
IOUT OUTPUT
Maximum Output Voltage RIOUT = 5 kW 2.0 V
Input Referred Offset Voltage ILIM minus CSREF 1.9 1.9 mV
Output Source Current ILIM sink current = 80 mA 700 mA
(IOUTCURRENT) / (ILIMCURRENT);
Current Gain AIIOUT RILIM = 20 kW; RIOUT = 5.0 kW; 9.5 10 10.5 A/A
VCSREF = 1.7 V
DIMON Full Scale Voltage VDIFS 2.0 V
OVERCURRENT PROTECTION (ILIM pin)
3 & 2phase PS0 Threshold Current, mA
1phase allPS Threshold Current
Delayed shutdown IDS 9.0 10 11.0
Immediate shutdown IIS 13.5 15 16.5
3phase, nonPS0 Threshold Current mA
Delayed shutdown IDS PS1, 2 or 3 mode (1phase active) 4
Immediate shutdown IIS PS1, 2 or 3 mode (1phase active) 6
2phase, nonPS0 Threshold Current mA
Delayed shutdown IDS PS1, 2 or 3 mode (1phase active) 6.7
Immediate shutdown IIS PS1, 2 or 3 mode (1phase active) 10
Time for Delayed Shutdown 55 ms
OSCILLATOR
Maximum Switching Frequency See Precision Oscillator description 1425 kHz
Minimum Switching Frequency See Precision Oscillator description 275 kHz
Switching Frequency Tolerance PS0 mode; RROSC = 110 kW 925 1025 1125 kHz
ROSC Pin Output Current VROSC = GND 9.5 10 10.5 mA
MODULATORS (PWM Comparators)
Minimum Pulse Width 20 ns
COMP voltage when the PWM outputs
0% Duty Cycle 1.3 V
remain Lo (Dualedge modulation only)
COMP voltage when the PWM outputs
100% Duty Cycle remain HI, VRMP = 12.0 V; (Dualedge 2.5 V
modulation only)
Between adjacent phases, 3phase
PWM Phase Angle Error 20 20 deg
operation
Ramp Feedforward Voltage range VRMP pin voltage 5 20 V
PWM OUTPUTS (PWM1/2/3)
VCC
Output High Voltage Sourcing 500 mA V
0.2
Output Low Voltage Sinking 500 mA 0.7 V

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NCP81105, NCP81105H

ELECTRICAL CHARACTERISTICS (VCC = 5.0 V, VEN = 2.0 V, CVCC = 0.1 mF unless specified otherwise) Min/Max values are valid
for the temperature range 10C TA 100C unless noted otherwise, and are guaranteed by test, design or statistical correlation.

Parameter Symbol Conditions Min Typ Max Unit


PWM OUTPUTS (PWM1/2/3)
CL (PCB) = 50 pF, measured between
Rise and Fall Times 10 ns
10% & 90% of VCC
DRVON OUTPUT
Output High Voltage Sourcing 500 mA 3.0 V
Output Low Voltage Sinking 500 mA 0.1 V
Rise Time CL (PCB) = 20 pF, DVo = 10% to 90% 150 ns
Fall Time CL (PCB) = 20 pF, DVo = 90% to 10% 5 ns
PWM delay time Time from DRVON high to first PWM 110 120 ms
Internal Pull Down Resistance EN = Low 70 kW
OD# OUTPUT
Output High Voltage Sourcing 500 mA 3.0 V
Output Low Voltage Sinking 500 mA 0.1 V
Entering PS0; from fall of the earlier of
PS0 Delay 15 ns
PWM2 or PWM3 to OD# rising
Rise/Fall Time CL (PCB) = 20 pF, DVo = 10% to 90% 10 ns
Internal Pull Down Resistance EN = Low 70 kW
SMOD OUTPUT
Output High Voltage Sourcing 500 mA 3.0 V
Output Low Voltage Sinking 500 mA 0.1 V
PS2/3 Delay PS2&3; PWM1 rising to SMOD rising 10 50 ns
Rise/Fall Time CL (PCB) = 20 pF, DVo = 10% to 90% 10 ns
Internal Pull Down Resistance EN = Low 70 kW
VR_HOT# OUTPUT
Output Low Voltage I_VRHOT# = 4 mA 0.3 V
Output Leakage Current High Impedance State, VVRHOT# = 3.3 V 1.0 1.0 mA
TSENSE INPUT
Alert# Assert Threshold TA = 85C 458 mV
Alert# Deassert Threshold TA = 85C 476 mV
VRHOT# Assert Threshold TA = 85C 437 mV
VRHOT# Deassert Threshold TA = 85C 457 mV
TSENSE Bias Current VTSENSE = 0.4 V, TA = 85C 57.7 60 62.7 mA
VBOOT PIN
Sensing Current VVBOOT = GND 10 mA
IMAX PIN
Sensing Current IIMAX VIMAX = GND 9.5 10 10.5 mA
IMAX Full Scale Voltage VIMAXFS 2.0 V
INT_SEL PIN
Sensing Current VINT_SEL = GND 10 mA
DGAIN PIN
Sensing Current VDGAIN = GND 10 mA
ADC
Input Voltage Range 0 2 V

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NCP81105, NCP81105H

ELECTRICAL CHARACTERISTICS (VCC = 5.0 V, VEN = 2.0 V, CVCC = 0.1 mF unless specified otherwise) Min/Max values are valid
for the temperature range 10C TA 100C unless noted otherwise, and are guaranteed by test, design or statistical correlation.

Parameter Symbol Conditions Min Typ Max Unit


ADC
Total Unadjusted Error (TUE) 1 +1 %
Differential Nonlinearity (DNL) 8bit 1 LSB
Power Supply Sensitivity 1 %
Conversion Time 10 ms
Time to cycle through all inputs 250 ms

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NCP81105, NCP81105H

VR12.5 & VR12.6 VID TABLE


Voltage Voltage
VID7 VID6 VID5 VID4 VID3 VID2 VID1 VID0 (V) HEX VID7 VID6 VID5 VID4 VID3 VID2 VID1 VID0 (V) HEX
0 0 0 0 0 0 0 0 OFF 00 0 0 1 1 1 1 1 0 1.11 3E
0 0 0 0 0 0 0 1 0.50 01 0 0 1 1 1 1 1 1 1.12 3F
0 0 0 0 0 0 1 0 0.51 02 0 1 0 0 0 0 0 0 1.13 40
0 0 0 0 0 0 1 1 0.52 03 0 1 0 0 0 0 0 1 1.14 41
0 0 0 0 0 1 0 0 0.53 04 0 1 0 0 0 0 1 0 1.15 42
0 0 0 0 0 1 0 1 0.54 05 0 1 0 0 0 0 1 1 1.16 43
0 0 0 0 0 1 1 0 0.55 06 0 1 0 0 0 1 0 0 1.17 44
0 0 0 0 0 1 1 1 0.56 07 0 1 0 0 0 1 0 1 1.18 45
0 0 0 0 1 0 0 0 0.57 08 0 1 0 0 0 1 1 0 1.19 46
0 0 0 0 1 0 0 1 0.58 09 0 1 0 0 0 1 1 1 1.20 47
0 0 0 0 1 0 1 0 0.59 0A 0 1 0 0 1 0 0 0 1.21 48
0 0 0 0 1 0 1 1 0.60 0B 0 1 0 0 1 0 0 1 1.22 49
0 0 0 0 1 1 0 0 0.61 0C 0 1 0 0 1 0 1 0 1.23 4A
0 0 0 0 1 1 0 1 0.62 0D 0 1 0 0 1 0 1 1 1.24 4B
0 0 0 0 1 1 1 0 0.63 0E 0 1 0 0 1 1 0 0 1.25 4C
0 0 0 0 1 1 1 1 0.64 0F 0 1 0 0 1 1 0 1 1.26 4D
0 0 0 1 0 0 0 0 0.65 10 0 1 0 0 1 1 1 0 1.27 4E
0 0 0 1 0 0 0 1 0.66 11 0 1 0 0 1 1 1 1 1.28 4F
0 0 0 1 0 0 1 0 0.67 12 0 1 0 1 0 0 0 0 1.29 50
0 0 0 1 0 0 1 1 0.68 13 0 1 0 1 0 0 0 1 1.30 51
0 0 0 1 0 1 0 0 0.69 14 0 1 0 1 0 0 1 0 1.31 52
0 0 0 1 0 1 0 1 0.70 15 0 1 0 1 0 0 1 1 1.32 53
0 0 0 1 0 1 1 0 0.71 16 0 1 0 1 0 1 0 0 1.33 54
0 0 0 1 0 1 1 1 0.72 17 0 1 0 1 0 1 0 1 1.34 55
0 0 0 1 1 0 0 0 0.73 18 0 1 0 1 0 1 1 0 1.35 56
0 0 0 1 1 0 0 1 0.74 19 0 1 0 1 0 1 1 1 1.36 57
0 0 0 1 1 0 1 0 0.75 1A 0 1 0 1 1 0 0 0 1.37 58
0 0 0 1 1 0 1 1 0.76 1B 0 1 0 1 1 0 0 1 1.38 59
0 0 0 1 1 1 0 0 0.77 1C 0 1 0 1 1 0 1 0 1.39 5A
0 0 0 1 1 1 0 1 0.78 1D 0 1 0 1 1 0 1 1 1.40 5B
0 0 0 1 1 1 1 0 0.79 1E 0 1 0 1 1 1 0 0 1.41 5C
0 0 0 1 1 1 1 1 0.80 1F 0 1 0 1 1 1 0 1 1.42 5D
0 0 1 0 0 0 0 0 0.81 20 0 1 0 1 1 1 1 0 1.43 5E
0 0 1 0 0 0 0 1 0.82 21 0 1 0 1 1 1 1 1 1.44 5F
0 0 1 0 0 0 1 0 0.83 22 0 1 1 0 0 0 0 0 1.45 60
0 0 1 0 0 0 1 1 0.84 23 0 1 1 0 0 0 0 1 1.46 61
0 0 1 0 0 1 0 0 0.85 24 0 1 1 0 0 0 1 0 1.47 62
0 0 1 0 0 1 0 1 0.86 25 0 1 1 0 0 0 1 1 1.48 63
0 0 1 0 0 1 1 0 0.87 26 0 1 1 0 0 1 0 0 1.49 64
0 0 1 0 0 1 1 1 0.88 27 0 1 1 0 0 1 0 1 1.50 65
0 0 1 0 1 0 0 0 0.89 28 0 1 1 0 0 1 1 0 1.51 66
0 0 1 0 1 0 0 1 0.90 29 0 1 1 0 0 1 1 1 1.52 67
0 0 1 0 1 0 1 0 0.91 2A 0 1 1 0 1 0 0 0 1.53 68
0 0 1 0 1 0 1 1 0.92 2B 0 1 1 0 1 0 0 1 1.54 69
0 0 1 0 1 1 0 0 0.93 2C 0 1 1 0 1 0 1 0 1.55 6A
0 0 1 0 1 1 0 1 0.94 2D 0 1 1 0 1 0 1 1 1.56 6B
0 0 1 0 1 1 1 0 0.95 2E 0 1 1 0 1 1 0 0 1.57 6C
0 0 1 0 1 1 1 1 0.96 2F 0 1 1 0 1 1 0 1 1.58 6D
0 0 1 1 0 0 0 0 0.97 30 0 1 1 0 1 1 1 0 1.59 6E
0 0 1 1 0 0 0 1 0.98 31 0 1 1 0 1 1 1 1 1.60 6F
0 0 1 1 0 0 1 0 0.99 32 0 1 1 1 0 0 0 0 1.61 70
0 0 1 1 0 0 1 1 1.00 33 0 1 1 1 0 0 0 1 1.62 71
0 0 1 1 0 1 0 0 1.01 34 0 1 1 1 0 0 1 0 1.63 72
0 0 1 1 0 1 0 1 1.02 35 0 1 1 1 0 0 1 1 1.64 73
0 0 1 1 0 1 1 0 1.03 36 0 1 1 1 0 1 0 0 1.65 74
0 0 1 1 0 1 1 1 1.04 37 0 1 1 1 0 1 0 1 1.66 75
0 0 1 1 1 0 0 0 1.05 38 0 1 1 1 0 1 1 0 1.67 76
0 0 1 1 1 0 0 1 1.06 39 0 1 1 1 0 1 1 1 1.68 77
0 0 1 1 1 0 1 0 1.07 3A 0 1 1 1 1 0 0 0 1.69 78
0 0 1 1 1 0 1 1 1.08 3B 0 1 1 1 1 0 0 1 1.70 79
0 0 1 1 1 1 0 0 1.09 3C 0 1 1 1 1 0 1 0 1.71 7A
0 0 1 1 1 1 0 1 1.10 3D 0 1 1 1 1 0 1 1 1.72 7B

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NCP81105, NCP81105H

VR12.5 & VR12.6 VID TABLE


Voltage Voltage
VID7 VID6 VID5 VID4 VID3 VID2 VID1 VID0 (V) HEX VID7 VID6 VID5 VID4 VID3 VID2 VID1 VID0 (V) HEX
0 1 1 1 1 1 0 0 1.73 7C 1 0 0 1 1 0 0 1 2.02 99
0 1 1 1 1 1 0 1 1.74 7D 1 0 0 1 1 0 1 0 2.03 9A
0 1 1 1 1 1 1 0 1.75 7E 1 0 0 1 1 0 1 1 2.04 9B
0 1 1 1 1 1 1 1 1.76 7F 1 0 0 1 1 1 0 0 2.05 9C
1 0 0 0 0 0 0 0 1.77 80 1 0 0 1 1 1 0 1 2.06 9D
1 0 0 0 0 0 0 1 1.78 81 1 0 0 1 1 1 1 0 2.07 9E
1 0 0 0 0 0 1 0 1.79 82 1 0 0 1 1 1 1 1 2.08 9F
1 0 0 0 0 0 1 1 1.80 83 1 0 1 0 0 0 0 0 2.09 A0
1 0 0 0 0 1 0 0 1.81 84 1 0 1 0 0 0 0 1 2.10 A1
1 0 0 0 0 1 0 1 1.82 85 1 0 1 0 0 0 1 0 2.11 A2
1 0 0 0 0 1 1 0 1.83 86 1 0 1 0 0 0 1 1 2.12 A3
1 0 0 0 0 1 1 1 1.84 87 1 0 1 0 0 1 0 0 2.13 A4
1 0 0 0 1 0 0 0 1.85 88 1 0 1 0 0 1 0 1 2.14 A5
1 0 0 0 1 0 0 1 1.86 89 1 0 1 0 0 1 1 0 2.15 A6
1 0 0 0 1 0 1 0 1.87 8A 1 0 1 0 0 1 1 1 2.16 A7
1 0 0 0 1 0 1 1 1.88 8B 1 0 1 0 1 0 0 0 2.17 A8
1 0 0 0 1 1 0 0 1.89 8C 1 0 1 0 1 0 0 1 2.18 A9
1 0 0 0 1 1 0 1 1.90 8D 1 0 1 0 1 0 1 0 2.19 AA
1 0 0 0 1 1 1 0 1.91 8E 1 0 1 0 1 0 1 1 2.20 AB
1 0 0 0 1 1 1 1 1.92 8F 1 0 1 0 1 1 0 0 2.21 AC
1 0 0 1 0 0 0 0 1.93 90 1 0 1 0 1 1 0 1 2.22 AD
1 0 0 1 0 0 0 1 1.94 91 1 0 1 0 1 1 1 0 2.23 AE
1 0 0 1 0 0 1 0 1.95 92 1 0 1 0 1 1 1 1 2.24 AF
1 0 0 1 0 0 1 1 1.96 93 1 0 1 1 0 0 0 0 2.25 B0
1 0 0 1 0 1 0 0 1.97 94 1 0 1 1 0 0 0 1 2.26 B1
1 0 0 1 0 1 0 1 1.98 95 1 0 1 1 0 0 1 0 2.27 B2
1 0 0 1 0 1 1 0 1.99 96 1 0 1 1 0 0 1 1 2.28 B3
1 0 0 1 0 1 1 1 2.00 97 1 0 1 1 0 1 0 0 2.29 B4
1 0 0 1 1 0 0 0 2.01 98 1 0 1 1 0 1 0 1 2.30 B5

Setup and Hold times CPU Driving SDIO

SCLK
VR
latch

SDIO

tHLD
tSU

VR Driving SDIO, Clock to Data Delay

SCLK

VR
send

SDIO

TCO_VR TCO_VR = clock to data delay in VR

Figure 10. SVID Timing Diagrams

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NCP81105, NCP81105H

STATE TRUTH TABLE


VR_RDY Error AMP
State Pin Comp Pin OVP & UVP DRVON Pin SMOD Pin OD# Pin Method of Reset

VCC UVLO N/A N/A N/A Resistive pull Resistive pull down Resistive pull down
0 < VCC < threshold down
VRMP > threshold

VRMP UVLO N/A N/A N/A Resistive pull Resistive pull down Resistive pull down
VCC > threshold down
0 < VRMP < threshold

Disabled Low Low Disabled Low Low Low


EN < threshold
VCC > threshold
VRMP > threshold

Start up Delay & Low Low Disabled Low Low Low


Calibration
EN > threshold
VCC > threshold
VRMP > threshold

Soft Start Low Operational Active High Low until first PWM1 Low until first PWM2
EN > threshold pulse or PWM3 pulse
VCC > threshold
VRMP > threshold

Normal Operation High Operational Active High High in PS0 & PS1; High in PS0; Low in N/A
EN > threshold High or may toggle in PS1, PS2, & PS3
VCC > threshold PS2 & PS3
VRMP > threshold

Over Voltage Low Low DAC + 400 mV High High/ Toggles during High/ Toggles during EN low or cycle
output rampdown output rampdown power

Under Voltage Low Operational DACDroop High High High Output voltage >
300 mV DACDroop
300 mV

Over Current Low Operational Last DAC Code Low Low Low EN low or cycle
+ 400 mV power

VID Code = 00h Low Low Disabled High (PWM Low Low Set Valid VID
outputs low) Code

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NCP81105, NCP81105H

Controller VCC > UVLO


Disable
POR

EN = 0 EN = 1
VCC < UVLO

Calibrate
Drive Off

3.5 ms and CAL DONE

VDRP > ILIM


Phase
NO_CPU
Detect
INVALID VID

VCCP > UVLO and DRON HIGH

Soft Start
Ramp

DAC = Vboot

Soft Start
Ramp

OVP

DAC = VID

VS > OVP

Normal
VR_RDY

VS > UVP
VS < UVP

UVP

Figure 11. State Diagram

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NCP81105, NCP81105H

General
The NCP81105 is a single output, onetothree phase, dualedge modulated PWM controller with a serial VID control
interface designed to meet the Intel VR12.5 & VR12.6 specifications. The NCP81105 implements PS0, PS1, PS2, PS3 and
PS4 power states. It is designed to work in notebook and desktop CPU power supply applications.
Power Status PWM Output Operating Mode
PS0 Multiphase, fixed frequency, dual edge modulation (RPM modulation when optioned for single phase), inter-
leaved PWM outputs (CCM mode)

PS1 Singlephase (PWM1) COT (CCM mode; Phases 2 & 3 disabled by OD#)
PS2 Singlephase (PWM1) RPM (DCM mode by SMOD; Phases 2 & 3 disabled by OD#)
PS3 Singlephase (PWM1) RPM (DCM mode by SMOD; Phases 2 & 3 disabled by OD#)
PS4 No switching; Memory retained; SVID active

For 81105, the VID code change rate is controlled with the SVID interface with three options as below:
Register Address (Contains
SVID Command the slew rate of VID code
DVID Option Code Feature change)
SetVID_Fast 01h 48 mV/ms VID code change slew rate 24h
SetVID_Slow 02h 12 mV/ms VID code change slew rate** 25h
SetVID_Decay 03h No control, VID code down N/A
**The Slow VID code change slew rate can be modified by writing to the 2Ah register with the SVID bus.

For 81105H, the VID code change rate is controlled with the SVID interface with three options as below:
Register Address (Contains
SVID Command the slew rate of VID code
DVID Option Code Feature change)
SetVID_Fast 01h 10 mV/ms VID code change slew rate 24h
SetVID_Slow 02h 2.5 mV/ms VID code change slew rate** 25h
SetVID_Decay 03h No control, VID code down N/A
**The Slow VID code change slew rate can be modified by writing to the 2Ah register with the SVID bus.

Serial VID
The NCP81105 supports the Intel serial VID (SVID) interface. It communicates with the microprocessor through three wires
(SCLK, SDIO, ALERT#). The table of supported registers is shown below.
Index Name Description Access Default
Uniquely identifies the VR vendor. The vendor ID assigned by Intel to
00h Vendor ID R 1Ah
ON Semiconductor is 0x1Ah

01h Product ID Uniquely identifies the VR product. The VR vendor assigns this number. R 15h
Product Uniquely identifies the revision or stepping of the VR control IC. The VR
02h R 04h
Revision vendor assigns this data.

Product date
03h R 00
code ID

05h Protocol ID Identifies the SVID Protocol the NCP81105 supports R 03h
Informs the Master of the NCP81105s Capabilities,
1 for supported, 0 for not supported
Bit 7: Iout_format; Reg 15 FFh = Icc_Max (=1)
Bit 6: ADC Measurement of Temp; Supported (= 1)
Bit 5: ADC Measurement of Pin; Not supported (= 0)
06h Capability R D7h
Bit 4: ADC Measurement of Vin; Supported (= 1)
Bit 3: ADC Measurement of Iin; Not supported (= 0)
Bit 2: ADC Measurement of Pout; Supported (= 1)
Bit 1: ADC Measurement of Vout; Supported (= 1)
Bit 0: ADC Measurement of Iout; Supported (= 1)

Data register read after the ALERT# signal is asserted. Conveying the status
10h Status_1 R 00h
of the VR.

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Index Name Description Access Default


11h Status_2 Data register showing optional status_2 data. R 00h
Data register showing temperature zones the system is operating in
12h Temp zone R 00h
(thermometer format with 3 degree resolution).

8 bit binary word ADC of current. This register reads 0xFF when the output
15h I_out R 01h
current is at ICC_Max

8 bit binary word ADC of output voltage, measured between VSP and VSN.
16h V_out R 01h
LSB size is 8 mV

17h VR_Temp 8 bit binary word ADC of temperature. Binary format in deg C, IE 100C = 64h. R 01h
8 bit binary word representative of output power. The output voltage is
18h P_out R 01h
multiplied by the output current value and the result is stored in this register.

8 bit binary word ADC of input voltage, measured at VRMP pin. LSB size is
1Ah V_in R 00h
112 mV

Status 2 Last When the status 2 register is read, its contents are copied into this register.
1Ch R 00h
read The format is the same as the Status 2 Register.

Data register containing the ICC_Max supported by the platform. The value is
21h ICC_Max measured at the IMAX pin upon power up and placed in this register. From R 00h
that point on, the register is read only.
Data register containing the max temperature the platform supports and the
22h Temp_Max level VR_hot asserts. This value defaults to 100C and is programmable over R/W 64h
the SVID Interface
Slew Rate for SetVID_fast commands. Binary format in mV/ms.
24h SR_fast NCP81105 R 32h
NCP81105H R 0Ah
Slew Rate for SetVID_slow commands. A fraction of the SR_fast rate (register
24h) determined by register 2Ah. Binary format in mV/ms
25h SR_slow
NCP81105 R 0Ch
NCP81105H R 03h
The Boot voltage is programmed using a resistor on the VBOOT pin which is
26h Vboot sensed on power up. The NCP81105 will ramp to Vboot and hold at Vboot until R 00h
it receives a new SVID SetVID command to move to a different voltage.
0001 = Fast_SR/2
SR_Slow 0010 = Fast_SR/4: default
2Ah R/W 02h
selector 0100 = Fast_SR/8
1000 = Fast_SR/16
Reflects the latency of exiting the PS4 state. The exit latency is defined as the
PS4 exit
2Bh time duration, in us, from the ACK of the SETVID Slow/Fast command to the R 8Ch
latency
beginning of the output voltage ramp.
Reflects the latency of exiting the PS3 state. The exit latency is defined as the
PS3 exit
2Ch time duration, in us, from the ACK of the SETVID Slow/Fast command until the R 55h
latency
NCP81105 is capable of supplying max current of the commanded PS state.
Reflects the latency from Enable assertion to the VR controller being ready to
Enable to accept an SVID command. The latency is defined as the time duration, in ms:
2Dh ready for SVID (x/16)*2Y. R CAh
time X = bits [3:0]: 4 bit value 0000 to 1111
Y = bits [7:4]: 4 bit value 0000 to 1111
Programmed by master and sets the maximum VID the VR will support. If a
higher VID code is received, the VR will respond with a not supported
30h Vout_Max RW B5h
acknowledgement. VR12.5 & VR12.6 VID format, e.g., B5h = 2.3 V (see VID
Table)
Data register containing currently programmed VID voltage. VID data format.
31h VID setting RW 00h
VR12.5 & VR12.6 VID format, e.g., 97h = 2.0 V

32h Pwr State Register containing the current programmed power state. RW 00h

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Index Name Description Access Default


Sets offset in VID steps added to the VID setting for voltage margining. Bit 7 is
sign bit, 0 = positive margin, 1 = negative margin. Remaining 7 BITS are # VID
steps for margin 2s complement.
00h=no margin
33h Offset RW 00h
01h=+1 VID step
02h=+2 VID steps
FFh=1 VID step
FEh=2 VID steps.
Bit 0 set to 1 causes VR_RDY to respond to a SetVID (0.0 V) command as a
valid VID voltage setting instead of a disable command (only after ramping to a
34h MultiVR Config nonzero VID after startup). RW 00h
Bit 1 set to 1 locks the current VID and Power State settings until such time as
the VR is issued a SetPS(00h) command.

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Phase Detection Sequence


During startup, the number of operational phases is determined by the internal circuitry monitoring the CSN inputs.
Normally, NCP81105 operates as a 3phase PWM controller. Connecting the CSN2 pin to VCC programs 2phase operation
using phases 1 and 3. Connecting the CSN3 pin to VCC programs 1phase operation using phase 1.
Prior to soft start, while ENABLE is high, the CSN2 and CSN3 pins have approximately 50 kW to ground. An internal
comparator checks the voltage of the CSN pins and compares them to a reference voltage. If either pin is tied to VCC, its voltage
is above the reference voltage and the controller is configured for reducedphase operation. Otherwise, the resistance pulls the
pin voltages to ground, which is below the reference, and the part operates in 3 phase mode.

PHASE COUNT TABLE


Number
of Phases Programming Pins (CSNx) What to do with Unused Pins
3 All CSN pins connected normally No unused pins
2 Tie CSN2 to VCC through 2 kW; Tie CSP2 to ground;
CSN3, CSN1 connected normally Float PWM2

1 Tie CSN3 to VCC through 2 kW; Tie CSN2, CSP2 & CSP3 to ground;
CSN1 connected normally Float PWM2, PWM3 & OD#

BOOT Voltage Programming


The NCP81105 has a VBOOT voltage register that can be externally programmed. The Boot voltage for the NCP81105 is
set using the VBOOT pin on power up. A 10 mA current is sourced from the VBOOT pin into an external resistance connected
to ground, and the resulting voltage is measured. This is compared with the thresholds in the table below and the corresponding
value is placed in the VBOOT register (26h). This value is set on power up and cannot be changed after the initial power up
sequence is complete.

BOOT VOLTAGE TABLE


Resistance Boot Voltage
30.1k 0V
49.9k 1.65 V
69.8k 1.70 V
Open 1.75 V

Addressing the NCP81105


The NCP81105 has fixed SVID device address 0000.

Remote Sense Amplifier


A high performance, high input impedance, differential amplifier is provided to accurately sense the output voltage of the
regulator. The VSP and VSN inputs should be connected to the regulators output voltage sense points. The remote sense
amplifier takes the difference of the output voltage with the DAC voltage and adds the droop voltage and a voltage to bias the
output above ground.
V DIFFOUT + V VSP * V VSN ) 1.3 V * V DAC * V DROOP * V CSREF

V DROOP + V CSCOMP Droop Gain Scaling (see the Droop Gain Table)

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High Performance Voltage Error Amplifier


The Remote Sense Amplifier output is applied to a Type 3 compensation network formed by the error amplifier, external
tuning components, and internal integrator. The noninverting input of the error amplifier is connected to the same reference
voltage used to bias the Remote Sense Amplifier output. The integrating function of the Type 3 feedback compensation is
performed internally and does not require external capacitor Cf1 (see below).

Rin1 Cf

Rf Cf1
Cin Rin2
_ COMP
+
Vbias ERROR

Figure 12. Traditional Type 3 External Compensation

Cf
Rin1

Cin Rin2 Rf
_ COMP
+
Vbias ERROR

Figure 13. NCP81105 Modified Type 3 External Compensation

Initial tuning should be based on traditional Type 3 compensation. When ideal Type 3 component values have been
determined, the closest setting for the internal integrator is given by the following equation:
INT_SETTING + 4.83 10 12 Rf Rin1 CF1; Rf & Rin1 in Ohms , Cf1 in nF
The internal integrator is programmed using the INT_SEL pin according to the following table:

INTEGRATOR TABLE
RINT_SEL INT_SETTING
10k 1
22k 2
36k 4
51k 8
68k 10
91k 12
120k 16
160k 32
220k 64
Recalculation of the initial tuning should be performed using the Cf1 value given by the Cf1 equation below in order to
determine whether readjustment of other components would provide more optimal compensation.
Cf1 (nF) + 2.07 10 5 INT_SETTING(Rf Rin1)
If an acceptable tuning cannot be produced by the closest Equivalent Type 3 Cf1, then reoptimization should be tried with
a different internal integrator setting.

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Differential Current Balance Amplifiers


Each phase has a low offset differential amplifier to sense the current of that phase in order to balance current. The CSNx
and CSPx pins are high impedance inputs, but it is recommended that the external filter resistor RCSN not exceed 10 kW to
avoid offset due to leakage current. It is also recommended that the voltage sense element be no less than 0.5 mW for best current
balance. The external filter RCSN and CCSN time constant should match the inductor L/DCR time constant, but fine tuning
of this time constant is not required.

CSNx
CSPx
RCSN CCSN

SWNx VOUT
L PHASE
R CSN + DCR LPHASE
C CSN * DCR 1 2

Figure 14.

The individual phase current signals are combined with the COMP and ramp signals at each PWM comparator input. In this
way, current is balanced via a current mode control approach.

Total Current Sense Amplifier


The NCP81105 uses a patented approach to sum the phase currents into a single, temperature compensated, total current
signal. This signal is then used to produce the output voltage droop, monitor total output current, and shut off switching if
current exceeds the set limit.
The Rref resistors average the voltages at the output sides of the inductors to create a low impedance reference voltage at
CSREF. The Rph resistors sum currents from the switchnodes to the virtual CSREF potential created at the CSSUM pin by
the amplifier. The total current signal at the amplifier output is the difference between CSCOMP and CSREF. The amplifier
lowpass filters and amplifies the voltage across the inductors to extract only the voltage across the inductor series resistances
(DCR).

CSN1

Cref
CSN2 Rref1

CSN3 Rref2 CSREF


CSCOMP
SWN1 Rref3 CSSUM

SWN2 Rph1
Ccs1
SWN3 Rph2
Ccs2
Rph3

RCS2 RCS1

Rth

Figure 15.

The equation for the DC total current signal is:


Rcs1*Rth
Rcs2 ) Rcs1)Rth
V CSCOMPCSREF + * Iout Total * DCR
Rph
Set the DC gain by adjusting the value of the Rph resistors to make the ratio of total current signal to output current equal
to the desired loadline. The Rph resistor value must be high enough to keep Rph current below 0.5 mA when switchnodes are
at nominal input voltage. If the voltage from CSCOMP to CSREF at ICCMAX is less than 100 mV, increase the gain of the
CSCOMP amp by a multiple of 2 until it is at or above 100 mV, and insert the resistor between the DGAIN pin and ground
that results in the correct loadline. See the Droop Gain Table. This is recommended to provide a high enough total current signal
to avoid impacts of offset voltage on current monitoring and the overcurrent shutdown threshold.

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An NTC thermistor (Rth) in the feedback network placed near the Phase 1 inductor senses the inductor temperature and
compensates both the DC gain and the filter time constant for the DCR change with temperature. The values of Rcs1 and Rcs2
are set based on the effect of temperature on both the thermistor and inductor. The thermistor should be placed near the Phase
1 inductor so that it measures the temperature of the inductor providing current in the PS1 power mode.
The pole frequency (FP) of the CSCOMP filter should be set equal to the zero frequency (FZ) of the output inductor. This
causes the total current signal to contain only the component of inductor voltage caused by the DCR voltage, and therefore to
be proportional to inductor current. Connecting Ccs2 in parallel with Ccs1 allows fine tuning of the pole frequency using
commonly available capacitor values. It is best to perform fine tuning during transient testing.
DCR@25 C
FZ +
2 * PI * L Phase

1
FP +
2 * PI * Rcs2 ) * (Ccs1 ) Ccs2)
Rcs1*Rth@25 C
Rcs1)Rth@25 C

Programming the Loadline (Droop Gain)


An output loadline is a power supply characteristic wherein the regulated (DC) output voltage decreases proportional to load
current. This characteristic reduces the amount of output capacitance needed to minimize output voltage variation during load
transients that exceed the speed of the regulation loop. In the NCP81105, a loadline is produced by adding a signal proportional
to output load current to the output voltage feedback signal thereby satisfying the voltage regulator at an output voltage
reduced in proportion to load current.
The loadline is programmed by the combined gains of the Total Current Sense Amplifier and the gain from the output of
this amplifier to the input of the Remote Sense Amplifier. The latter gain is referred to as Droop Gain Scaling, and has four
possible values programmed by the value of resistance connected from the DGAIN pin to ground. For systems with full load
output voltage droop greater than 100 mV, the Droop Gain Scaling can be 100%. Other systems should use lower Droop Gain
Scaling and correspondingly higher Total Current Sense Amplifier gain, such that at full load the CSCOMP to CSREF voltage
is 100 mV or greater. The following table shows the DGAIN resistances required to program different Droop Scalings.

Droop Gain Table


RDGAIN Droop Gain Scaling Effect
10k 100% Droop equals the CSCOMP to CSREF voltage
25k 50% Droop equals half of the CSCOMP to CSREF voltage
45k 25% Droop equals one quarter of the CSCOMP to CSREF voltage
w70k 0% Zero milliohm loadline (no loadline)

Programming the Current Limit


The current limit thresholds are programmed with a resistor between the ILIM and CSCOMP pins. The ILIM pin voltage
is a buffered replica of the CSREF voltage. The ILIM current is mirrored internally to the current limit comparators and to IOUT
(increased by the IOUT Current Gain). The 100% current limit trips if ILIM current exceeds the Delayed Shutdown Threshold
for the Delayed Shutdown Time. Current limit trips with minimal delay if ILIM current exceeds the Immediate Shutdown
Threshold. Set the value of the current limit resistor based on the CSCOMPCSREF voltage as shown below.
Rcs1*Rth

Rcs2 ) Rcs1)Rth
Rph
* Iout LIMIT * DCR V CSCOMPCSREF@ILIMIT
R LIMIT + or R LIMIT +
I DS I DS

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Rth

SWN1 Rcs2 Ccs2 Rcs1

Rph1 Ccs1
SWN2
Rph2
SWN3
_ CONTROLLER
Rph3 CSSUM CSCOMP
CSN1 CSREF +
Rref1
CSN2 SCALING DGAIN
Rdgain
Rref2
CSN3
to Remote
Rref3 Cref Sense Amplifier
ILIM
Rilim
buffer IOUT
Current Riout
Mirror

Current Limit
Comparators

Figure 16.

Programming IOUT
The IOUT pin sources a current equal to the ILIM current gained by the IOUT Current Gain. The voltage on the IOUT pin
is monitored by the internal A/D converter and should be scaled with an external resistor to ground such that a load equal to
ICCMAX generates a 2 V signal on IOUT. A pullup resistor to 5 V VCC can be used to offset the IOUT signal positive if
needed.
V DIMAX * R LIMIT
R IOUT +
* Iout
R CS1*Rth
R )
CS2 R )Rth
AI IOUT * CS1
ICC_MAX * DCR
Rph

Programming ICC_MAX
The SVID interface conveys the platform ICC_MAX value to the CPU from register 21h. A resistor to ground on the
IMAX pin programs this register at the time the part in enabled. Current is sourced from this pin to generate a voltage on the
program resistor. The value of the register is 1 A per LSB and is set by the equation below. The resistor value should be no less
than 10k.
R * I IMAX * 256 A
ICC_MAX 21h +
V IMAXFS

Improving Dynamic VID (DVID) Settling Time


Upon each increment of the internal DAC following a DVID UP command, the NCP81105 outputs a pulse of current from
the VSN pin. If a parallel RC network is inserted into the path from VSN to VSS_SENSE, the voltage between VSP and VSN
is temporarily decreased, which causes the output voltage during DVID to be regulated slightly higher to compensate for the
response of the Droop function to output current flowing into the output capacitors.

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VCC_SENSE VSP REMOTE SENSE


VSS_SENSE VSN
+
_ AMPLIFIER
RFF
CONTROLLER
+_
CFF

DVID UP

INCREMENT
CURRENT
PULSES

DAC
DAC

VSN

Figure 17.

The R and C values should be chosen according to the following equations:


Loadline * Cout
R FF + W
1.35 * 10 9
200
C FF + nF
R FF

Programming TSENSE
A temperature sense input is provided. A precision current is sourced out the output of the TSENSE pin to generate a voltage
on the temperature sense network. The voltage on the temperature sense input is sampled by the internal A/D converter and
then digitally converted to temperature and stored in SVID register 17h. A 220k NTC similar to the Murata
NCP15WM224E03RC should be used.

Precision Oscillator
A programmable precision oscillator is provided to control the switching frequency of each phase. The oscillator serves as
the master clock to the ramp generator circuits, which each run at the same frequency. The ROSC pin sources a current into
an external programming resistor. The voltage present at the ROSC pin is read by the internal ADC and used to set the frequency
according to the following table.

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SWITCHING FREQUENCY TABLE (PS0)


ROSC Frequency ROSC Frequency ROSC Frequency ROSC Frequency
(kW) (kHz) (kW) (kHz) (kW) (kHz) (kW) (kHz)

10 246 37.4 445 75 656 127 1132


13.3 272 42.2 468 80.6 720 133 1185
16.2 298 46.4 492 86.6 785 143 1236
19.6 323 49.9 515 93.1 845 150 1285
23.2 348 54.9 538 100 906 162 1333
26.1 373 60.4 561 105 966 169 1377
29.4 397 64.9 584 113 1023 187 1426
33.2 421 69.8 605 121 1078 210 1475

Ramp Generator Circuits


In PS0, the oscillator controls the frequency of triangle ramps for the pulse width modulator. Ramp amplitude depends on
the VRMP pin voltage in order to provide input voltage feed forward compensation. The ramps have equal phase displacement
with respect to each other.

Ramp FeedForward Circuit and Ramp UVLO


The ramp generator includes voltage feedforward control that varies the ramp magnitude proportional to the VRMP pin
voltage. The PWM ramp voltage is changed according to the following:

Vin

Vramp_pp V RAMPpk+pkPP + 0.1 * V VRMP


CompIL

Duty

The VRMP pin also has a UVLO function. The VRMP UVLO is only active after the controller is enabled. The VRMP pin
is a high impedance input when the controller is disabled or put into PS4. The resistance of an RC filter at the VRMP pin should
not exceed 10 kW.

PWM Comparators
The noninverting input of each comparator (one for each phase) is connected to the summation of the output of the error
amplifier (COMP) and each phase current (IL * DCR * Phase Balance Gain Factor). The inverting input is connected to the
triangle ramp voltage of that phase. The output of the comparator generates the PWM output.
During steady state PS0 operation, the main rail PWM pulses are centered on the valley of the triangle ramp waveforms and
both edges of the PWM signals are modulated. During a transient event, the duty cycle can increase rapidly as the error amp
signal increases with respect to the ramps, to provide a highly linear and proportional response to the step load.

Power State 1 (PS1)


The NCP81105 supports PS1 by providing the OD# output. When the OD# output is connected to the phase 2 and 3 DrMOS
ZCD inputs, the PS1 state causes the NCP81105 to send low levels on OD#, PWM2 and PWM3, causing the power stages of
phases 2 and 3 to be tristated (both high and low side FETs off). The modulation mode changes from constantfrequency
dualedge modulation to Constant ON Time modulation.

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PS0 PS1 PS2 PS1 PS0


(PWM2 & PWM3 ACTIVE) (PWM2 & PWM3 LOW) (PWM2 & PWM3 LOW) (PWM2 & PWM3 LOW) (PWM2 & PWM3 ACTIVE)

OD#

PWM1

DRVH1SW1

PH1
INDUCTOR
CURRENT
AVERAGE PHASE CURRENT
0

SMOD

DRVL1

Figure 18.

Zero Cross Detect (ZCD) Enabling (PS2)


The NCP81105 supports the DrMOS ZCD function (diode emulation) by providing the SMOD output.
When the controller receives an SVID command asking for PS2 mode (lighter load current condition), PWM2, PWM3 and
OD# are held low, causing the power stages of phases 2 and 3 to be inactive (open circuit). When the NCP81105 detects that
inductor current is no longer positive, SMOD is pulled LOW to enable the DrMOS diode emulation function, and the PWM1
output continues fullrange twostate outputs (from 0 V to the VCC rail).
For DrMOS without a ZCD function, when SMOD goes low in response to the NCP81105 detecting that inductor current
is no longer positive, DrMOS synchronous rectification is immediately disabled.
For PS0 and PS1 states, SMOD stays HIGH, disabling the DrMOS ZCD function.

Protection Features

Input Under Voltage Protection


NCP81105 monitors the VCC supply voltage at the VCC pin and the VDC power source at the VRMP pin in order to provide
under voltage protection. If either supply dips below their threshold, the controller will shut down the outputs. Upon recovery
of the supplies, the controller reenters its startup sequence, and soft start begins.

Soft Start
Soft start is implemented internally. A digital counter steps the DAC up from zero to the target voltage based on the
predetermined slew rate in the spec table. The CSN2 and CSN3 pins will start out applying a test resistance to collect data on
phase count. After the configuration data is collected, the controller is enabled and sets the OD# and SMOD signals low to force
the drivers to stay in diode mode. DRVON will then be asserted to enable the drivers. A period of time after the controller senses
that DRVON is high, the COMP pin is released to begin softstart. The DAC ramps from zero to the target DAC code and the
PWM outputs will begin to fire. SMOD will go high when the first PWM1 pulse is produced to preclude discharge of a
precharged output. Upon PWM2 or PWM3 going high for the first time, OD# is set high.

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SoftStart Sequence

VCC TA

EN
DrMOS Enabled
DRON

Softstart Delay
DAC

COMP

PWM1

SMOD

PWM2

OD#

VOUT

Figure 19.

Over Current LatchOff Protection


The NCP81105 provides two different types of current limit protection. During normal operation a programmable total
current limit is provided that is scaled back during reducedphase, power saving operation. This limit is programmed with a
resistor between the CSCOMP and ILIM pins. The current from the ILIM pin to this resistor is then compared to internal IDS
and IIS currents. If the ILIM pin current exceeds the IDS level, an internal latchoff timer starts. When the timer expires, the
controller shuts down if the fault is not removed. If the current into the pin exceeds IIS, the controller will shut down
immediately. To recover from an OCP fault, the EN pin must be cycled low.
The overcurrent limit is programmed by a resistor from the ILIM pin to the CSCOMP pin. The resistor value can be
calculated by the following equation:
V CSCOMP * V CSREF
R ILIM +
I DS

Output Under Voltage Monitor


The output voltage is monitored by a dedicated differential amplifier. If the output falls below target by more than the Under
Voltage Threshold Below DACDroop, the UVL comparator sends the VR_RDY signal low.

Over Voltage Protection


During normal operation the output voltage is monitored at the differential inputs VSP and VSN. If the output voltage
exceeds the DAC voltage by the Over Voltage Threshold Above DAC, PWMs will be forced low, and the SMOD pin will
also go low when the voltage drops below that threshold. After the OVP trip the DAC will ramp slowly down to zero to avoid
a negative output voltage spike during shutdown. If the DAC + OVP Threshold drops below the output, SMOD will again go
high, and will toggle between low and high as the output voltage follows the DAC + OVP Threshold down. When the DAC
gets to zero, the PWMs will be held low and the SMOD and DRVON pin voltages will remain high. To reset the part, the EN
pin must be cycled low. During softstart, the OVP threshold is set to the Absolute Over Voltage Threshold. This allows the
controller to start up without false triggering the OVP if residual voltage from a prior period of operation is already present
at the output.

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OVP Threshold Behavior Normal PS0 and PS1 Operation

VSPVSN VSPVSN
DAC DAC

Fault Fault
(VSP short OVP (VSP short OVP
to ground) Triggered to ground) Triggered
Rampdown Rampdown
Latched Latched

DAC DAC

Latch Off Latch Off


PWM PWM
SMOD SMOD
OD# OD#

PS0 PS1
Figure 20.

OVP Threshold Behaviour During Softstart into Precharged Output

OVP Threshold during Softstart

OVP Threshold after Softstart

VSPVSN (precharged)

Target VID
Reached

DAC
0
PWM
SMOD

OD#
Figure 21.

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Printed Circuit Board Layout Notes


The NCP81105 has differential voltage and current monitoring. This improves signal integrity and reduces noise issues
related to layout for easy design use. To ensure proper function there are some general PCB layout rules to follow:
Careful layout for perphase and total current sensing are critical for jitter minimization, accurate current balancing and
limiting, and IOUT reporting. Give the first priority in component placement and trace routing to per phase and total current
sensing circuits. The per phase inductor current sense RC filters should always be placed as close to the CSN and CSP pins
on the controller as possible. The filter cap from CSCOMP to CSSUM should also be close to the controller. The temperature
compensating thermistor should be placed as close as possible to the Phase 1 inductor. The wiring path between Rcs2 and Rphx
should be kept as short as possible and well away from switch node lines. The above layout notes are shown in the following
diagram:

CONTROLLER
CSCOMP
43
Ccs1 Ccs2 Rcs1 Rth
KEEP THIS PATH AS SHORT PLACE AS CLOSE
AS POSSIBLE, AND WELL AWAY AS POSSIBLE TO
_ 42
CSSUM FROM SWITCHNODE LINES PHASE 1 INDUCTOR
CSREF Rcs2
+ 40
Rph1 Rph2 Rref1 Rref2

TO INDUCTOR
_ 34
CSP1 SWITCHNODE
Ccsp1 Rcsp1 TERMINAL
CSN1
+ 35 TO INDUCTOR
VOUT TERMINAL

TO INDUCTOR
_ 38
CSP2 SWITCHNODE
TERMINAL
CSN2 Ccsp2 Rcsp2
+ 39 TO INDUCTOR
VOUT TERMINAL
PER PHASE CURRENT SENSE
RC SHOULD BE PLACED
CLOSE TO CSPx PINS
Figure 22.

Place the VCC decoupling caps as close as possible to the controller VCC pin. For any RC filter on the VCC pin, the resistor
should be no higher than 5 W to prevent large voltage drop.
The small feedback cap from COMP to FB should be as close to the controller as possible. Keep the FB traces short to
minimize their capacitance to ground.

ORDERING INFORMATION
Device Package Shipping
NCP81105MNTXG QFN36 5000 / Tape & Reel
(PbFree)

NCP81105HMNTXG QFN36 5000 / Tape & Reel


(PbFree)
For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.

http://onsemi.com
35
NCP81105, NCP81105H

PACKAGE DIMENSIONS

QFN36 5x5, 0.4P


CASE 485CC
ISSUE O
NOTES:
D A L L 1. DIMENSIONING AND TOLERANCING PER


B ASME Y14.5M, 1994.
2. CONTROLLING DIMENSIONS: MILLIMETERS.
L1


3. DIMENSION b APPLIES TO PLATED
PIN ONE TERMINAL AND IS MEASURED BETWEEN
LOCATION
0.15 AND 0.30mm FROM THE TERMINAL TIP.


DETAIL A 4. COPLANARITY APPLIES TO THE EXPOSED
ALTERNATE PAD AS WELL AS THE TERMINALS.
CONSTRUCTIONS
E MILLIMETERS
DIM MIN MAX


A 0.80 1.00
0.15 C EXPOSED Cu MOLD CMPD A1 0.05


A3 0.20 REF
b 0.15 0.25
0.15 C TOP VIEW D 5.00 BSC
D2 3.40 3.60
E 5.00 BSC
DETAIL B E2 3.40 3.60
DETAIL B (A3) ALTERNATE
0.10 C e 0.40 BSC
CONSTRUCTION
K 0.35 REF
A L 0.30 0.50
L1 0.15
0.08 C A1
SEATING
NOTE 4 SIDE VIEW C PLANE
RECOMMENDED
SOLDERING FOOTPRINT*
0.10 M C A B
D2 5.30
DETAIL A 36X
10
K 3.64 0.63
19 0.10 M C A B
1
E2
3.64 5.30
1

36
36X L 36X b
e
0.10 M C A B
PKG 36X
0.05 M C NOTE 3 OUTLINE 0.40 0.25
BOTTOM VIEW PITCH
DIMENSIONS: MILLIMETERS

*For additional information on our PbFree strategy and soldering


details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.

Intel is a registered trademark of Intel Corporation in the U.S. and/or other countries.

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copyrights, trade secrets, and other intellectual property. A listing of SCILLCs product/patent coverage may be accessed at www.onsemi.com/site/pdf/PatentMarking.pdf. SCILLC
reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any
particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without
limitation special, consequential or incidental damages. Typical parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications
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PUBLICATION ORDERING INFORMATION


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36