4.4 An n-channel device has k= 50 pA/V’, V,= 0.8 V, and W/L. = 20. The device is ta operate as a switch for small Ups, utilizing a control voltage vgs in the range 0 V to 5 V. Find the switch closure resistance, rps, and closure voltage, Vp, obtained when vgs = 5 V and i, = 1 mA. Recalling that H, =~ 0.4u,, what must W/L be for a p-channel device that provides the saine performance as the n-channel device in this application? 4.6 Consider a CMOS process for which Lyi, = 0.8 fm, f= {5 nm, 1, - 550 om/V- s, und V,=0.7V. (a) Find C,, and k}. (b) For an NMOS transistor with W/L = 16 m/0.8 pm, calcu- late the values of Vyy, Ves, and Vis... needed to operate the transistor in the saturation region with a de current Ip = 100 WA. (c) For the device in (b), find the valuc of Voy and Vas required to cause the device to operate as a LOQO-Q resistor for very small ups. 4.17 An NMOS wansistor having V,= 1 V is operated in the triode region with v,,, small. With V,;, = 1.5 V, it is found to have a resistance 7, of | kQ. What value of Ves is reqnired to obtain r,s = 200 22? Find the corresponding resistance valucs obtained with a device having twice the value of W. 4.72 A particular cnhancement MOSFET for which V, = 1 V and &, (W/L) =0.1 mA/V? is to be operated in the satura- tion region. If ip is to be 0.2 mA, find the required vgs and the minimum required v,,,. Repeat for ip =0.8 mA.D4.14 For a particular IC-fabrication process, the trans- conductance parameter 47, = 50 BAN, and V,= 1 V. nan application in which vgs = Ups = Veropty ='5 V, a drain current of 0.8 mA is required of a device of minimnm length of 2 zm. What value of channel width must the design use? 4.18 When the drain and gate of a MOSFET are connected together, a two-terminal device known as a “diode-connected transistor” results. Figure P4.18 shows such devices obtained. from MOS transistors of both polarities, Show that {a) the iy relationship is given by (b) the incremental resistance r for a device biased to operate atv = |V| + Voy is given by oF] = YR EY) FIGURE P4.184.19 Fora particular MOSFET operating in the satura- tion region at a constant vgs, ip is found to be 2 mA for ups = 4V and 2.2 mA for apy = 8 V. Whal values of r,, V,, and A correspond? 4.20 A particular MOSFET has V, = 50 V. For operation at 0.1 mA and | mA, what are the expected outpul resistances? In each case, for a change in ups of 1 V, what percentage change in drain current would you expect? 4.27 A p-channel transistor for which|V,| = 1 V and |Val = 50 V operates in saturation with |ugs] = 3 V, |eps|= 4 VY, and iy =3 mA. Find corresponding signed values for vgs, vsq: Ups: Usp, Vi, Vay A, and ky (W/L).*4.33 All the transistors in the circuits shown in Fig. P4.33 have the same values of |V,j, k’, W/L, and A. Moreover, A is negligibly small. All operate in saturation at J, = I and |Yos| = /Vos| = 3 V. Find the voltages V,, V,, V3, and V,. If lV] = 1 and f = 2 mA, how large a resistor can be inserted in series with each drain connection while maintain- ing saturation? What is the largest resistor that can be placed in series with each gate? If the current source / requires at least 2 V between its terminals to operate properly, what is the largest resistor that can be placed in series with each MOSFET source while ensuring saturated-mode operation of cach transistor at Jp = 7? In the latter limiting situation, what do V,, Vo, V3, and V, become? Hov +10v #5V ’ ! poLe ¥ ¥% po pH 2 r = -9v I -5v ® ® © w FIGURE P4.334.42 In the circuits shown in Fig. P4.42, transistors are characterized by |V,| =2 V, kK WiL=1 mA/V?, and a=0. (a) Find the fabelled voltages V, through V3. (b) In each of the circuits, replace the current source with a resistor. Select the resistor value to yield a current as clase to that of the current source as possible, while using resistors specificd in the 1% table provided in Appendix G. Find the new values of V, to V;. 4 +10V | 4 FOV a aka | dma +0¥ 4 : F Cr % % — ha Tima, ¥ £7 CC = v, . yO ¥ =, zmA om | 25 kt mA ) * ' + -10v = -10¥ = (@) «by © a FIGURE P4.421% Resistor Values (KO) ‘5% Resistor Values (K2) 100-174 178-309 316-549 562-576 10 100 178 316 562 u 102 182 a24 576 2 105 187 332 590 3 107 191 0 604 15 110 196 348 19 16 3 200 357 634 18 us 205 365 649 20 “118 20 374 665 2 121 28 383 681 24 104 221 392 698 a iba 226 402 15 30 130 22 412 732 33 133, 237 a2 750 36 137 m3 432 768 39 140 249 187 ee) 143 255 206 47 147 261 825 31 150 287 845 56 154 274 866 a 158 280 887 68 162 287 909 5 165 294 931 82 169 301 91 174, 3094.44 For each of the circuits shown in Fig. P4.44, find the labeled. node voltages. The NMOS transistors have V,= 1 V and EE W/L= 2 mAAV?, Assume A= 0, +10V tL L yy, | pt 1Ka “sv @ FIGURE P4.44 *4,.45 For the PMOS transistor in the circuit shown in Fig. P4.45, k= 8 WA/V?, W/L= 25, and |V,,| = 1 V. For Z= 100 WA, find the voltages Vey and Vy; for 30 kQ, and 100 k@. For what value of R is Vip = Vsc? Ven = Vag 2? Vep = Vsgll0? +10¥ 4 gno —+—¥, aA }, 10 kQ,, | $e Y FIGURE P4.45] Vv, A=0, y=0, 1,0, Se SO uA L=1| pm, and We= 104m. Find V; and /;. How do these values change if @, and Q, are made to have W= 100 um? 4,48 In the circuit of Fig. P4.48, transistors Q, and Q, have V,=LV, and the process transconductance parameter k’ = 100 wA/¥’. Assuming A= 0, find V,, V2, and V; for each of the following cases: (a) (W/L), = (W/L), = 20 (b) (W/L), = 1S(W/L), = 20 +5V | h V,;0—# OI 2 < = FIGURE P4.47 | FIGURE P4.484.49 Consider the CS amplificr of Fig. 4.26(a) for the case Von = 5 V, Rp =24kQ, ki (W/L) = | mA/V?. and V,=1 V. (a) Find the coordinates of the two end pomts of the saturation- fegion scgment of the amplifier transfer characteristic, that is, points A and B on the sketch of Fig. 4.26(c). (b) If the amplifier is biased to operate with an overdrive voltage Voy of 0.5 V, find the coordinates of the bias point Q, on the transfer characteristic. Also, find the value of /,, and of the incremental gain A, at the bias point. (c) For the situation in (b), and disregarding the distortion caused by the MOSFET’s square-law characteristic, what is the largest amplitude of a sine-wave voltage signal that can be applied at the iuput while the transistor remains in saturation’? What is the amplitude of the output voltage signal that results? What guin value does the combination of thesc ampli- tudes imply? By what percentage is this gain value different from the incremental gain value calculated above? Why is there a difference? Voo FIGURE 4,26 (a)4.54 Figure P4.54 shows a CS amplificr in which the load resistor Rp has been replaced with another NMOS transistor Q, connected as # two-terminal device. Note that because upg of Q, is zero, it will be operating in saturation at all times, even when v= 0 and ips = ip, = 0. Note also that the two transistors conduct equal drain currents. Using ip, = ip2, show that for the range of u, over which Q, is operating in saturation, that is, for Vy Su Supt Vy the output voltage will he given by W/L), Ww vo = Vpo- Vit i yl : iy (W/L); (W/L), where we have assumed V, = Vi = V,. Thus the circuit func- tions as a linear amplifier, even for large input signals. Por (W/D), = (0 um/05 jm) and (W/E), = (5 am/0.5 um), find the voltage gain. Von ty, “ie 2) —0 vy Yo FIGURE P4.544.58 An enhancement NMOS transistor is connected in the bias circuit of Fig. 4.30(c), with Vz = 4 V and R= 1 kQ. The transistor has V, = 2 V and k7(W/L) = 2 mA/V*, What bias current results? If a transistor for which kj(W/L) is 50% higher is used, what is the resulting percentage increase in /,,? 4.61 Design the circuit in Fig. P4.61 so that the transistor operates in saturation with Vp biased [ V [rom the edge of the triode region, with Ip = 1 mA and ¥,) = 3 V, for each of the following two devices (use a 10-4A current in the voltage divider): (a) ‘VJ=1V and KW/L= 0.5 mav* (b) [VJ=2 V and k, W/E = 1.25 mA‘v For each case, specify the values of Vg. Vp, Vs, Ry, Ro, Rs, and Rp. +10V R Ro FIGURE P4.6104,66 Figure P4.66 shows a variation of the feedhack-hias circuit of Fig. 4.32. Using a 6-V supply with an NMOS transis- tor for which V, = 1.2 V, k, WIL = 3.2 mA/V" and 1=0, provide a design which biases the transistor at /;, = 2 mA, with Vps large enough to allow saturation operation for a 2-V negative signal swing at the drain. Use 22 MQ as the largest resistor in the feedbeck-bias network. What values of Rp, Re) and Ry» have you chosen? Specit’y all resistors to two significant digits. Yop Rp Ror FIGURE P4.66 4.68 Consider an NMOS transistor having KWL = 2 mA/V?, Let the transistor be biased at Voy = 1 V. For operation in saturation, What de bias current /p results? If a +0.1-V signal is superimposed on V;s, find the corresponding increment in collector current by evaluating thc total collector current i, and subtracting the de bias current /y. Repeat for a -0.1-V signal. Use these results to estimate g,, of the FET at this bias point. Compare with the value of g,, obtained using Eq. (4.62).4.74 For the NMOS amplifier in Fig. P4.74, replace the transistor with its T equivalent circuit of Fig. 4.39(d). Derive expressions for the voltage gains v,/v, and u,/v;. 4.75 in the circuit of Fig. P4.75, the NMOS transistor has |¥| =0.9 V and ¥, = 50 V and operates with Vp = 2 V. What is the voltage gain v,/v;? What do Vp and the gain become for / increased to ] mA? +Vpp Rp —Vss FIGURE P4.74 FIGURE P4.754.77 Figure P4.77 shows a discrete-circuit CS amplifier employing the classical biasing scheme studied in Section 4.5. The input signal vu, is coupled to the gate through a very large capacitor (shown as infinite). The transistor source is connected to ground at signal frequencies via a very large capacitor (shown as infinite). The output voltage signal that develops at the drain is coupled to a load resistance via a very large capacitor (shown as infinite). (a) If the transistor has V,= 1 V, and k{ W/L =2 mASV’, ver- ify that the bias circuit establishes V,,, = 2 V. Jp = 1 mA. and Vp = +7.5 V. That is, assume these values, and verify that they aré consistent with the values of the circuit components and. the device parameters. (b) Find g,, and r, if ¥, = 100 V. (c) Draw a complete small-signal equivalent circuit for the ampiificr assuming all capacitors behave as short circuits at signal frequencies. (d) Find Rigs Ug5/ tage Up Uy, and ¥,/ D0. +15V 1oMo 7 ska a jst y rox at tH g IK v 5 Ay FIGURE P4.774.79 Calculate the overall voltage gain G, of a common- source amplifier for which g,,= 2 mA/V, r, = 50 kQ, R, = 10 kQ, and Re = 10 MQ. The amplifier is fed from a signal source with a Thévenin resistance of 0.5 MQ, and the ampli- fier output is coupled to a load resistance of 20 kQ2. 4.81 A common-gate amplifier using an n-channel enhance- ment MOS transistor for which g,, = 5 mA/V has a 5-kQ drain resistance (Rp) and a 2-kQ load resistance (R,). The amplifier is driven by a voltage source having a 200-Q resis- tance. What is ihe input resistance of the amplifier? What is the overall voltage gain G,,? If the circuit allows a hias-current increase by a factor of 4 while maintaining linear operation, what do the input resistance and voltage gain hecome? 4.85 The source follower of Fig. 4.46(a) uses a MOSFET biased to have g,,= 5 mA/V and y, = 20 kQ. Find the open- circuit voltage gain A,, and the output resistance, What will the gain become when a 1-k@2 oad resistance (K,) is connected? v, ‘ow ca Rig =| @*D4.87 The MOSFET in the circuit of Fig. P4.87 has V, = IV, KW/L = 0.8 mA/V’, and V, = 40 V. (a) Find the values of Ry, Rp, and Ry, so that J, = 0.1 mA, the largest possible value for Rp is used while a maximum signal swing at the drain of +1 V is possible, and the input resistance at the gate is 10 MQ. (b) Find the values of g,, and r, at the bias point. (c) If termmal Z is grounded, terminal X is connected to a signal source having a resistance of 1 M®, and terminal Y is connected to a load resistance of 40 kQ, find the voliage gain from signal source to load. (d) If terminal Y is grounded, find the voltage gain from X to Z with Z open-circuited. What is the output resistance of the source follower? {e) If terminal X is grounded and terminal Z is connected to a current source delivering a signal current of 10 4A and hav- ing a resistance of 100 kQ, find the voltage signal that can be measured at Y. For simplicity, neglect the effect of r,. FIGURE P4.874.115 A depletion-type #-channel MOSFET with k/ W/L = 2mA/V? and V, =—3 V has its source and gate grounded. Find the region of operation and the drain current Lor dp =0.1 V1 V, 3 Vand 5 V. Neglect the channel-length-modulation effect. 4.116 For a particular deplction-mode NMOS device, V, = -2V, KWL = 200 A/V", and A= 0.02 V~', When operated al Ugg =O, what is the drain current that flows for vps= 1 V, 2 V. 3 V. and 10 V? What does cach of these currents become if the device width is doubled with Z the same? With L also doubled? 4.117 Negiccting the channe)-length-modulation effect show that for the deplction-type NMOS transistor of Fig. P4.117 the (-v relationship is given by = LA (W/L) (FP 2,0), for v2 V, = AM (W/L)V;, fore $V, (Recall that ¥, is negative.) Skeich the i—v relationship for the case: V,=—2 V and AACW/E) = 2 mAV?. “ip” FIGURE P4.117*#4.123 In the amplifier shown in Fig. P4.123, transistors having V, = 0.6 V and V, = 20 V are operated at V-, = 0.8 V using the appropriate choice of W/L ratio. In a particular application, Q, is to be sized to operate at 10 WA, while Q, is intended to operate at | mA. For R, = 2 kQ, the (R,, R,) net- work sized to consume only 1% of the current in R,, v,,., having zero dc component, and J, = 10 eA, find the values of Ry and R, that satisfy all the requirements. (Hint: Vy must be +2 V.) What is the voltage gain u,/v,? Using a result from a theorem known as Miller’s theorem (Chupter 6), find the mput resis- tance R;, as R,/(1 - v,/v,). Now, calculate the value of the overall voltage gain w,/v,ip. Does this result remind you of the inverting configuration of the op amp? Comment. How would you modify the circuit at the input using an additional resistor and a very large capacitor to raise the gain of tjg to —3 V/V? Neglect the body effect. FIGURE P4.123