28n v1 0 IO Usage Guidelines

PMC 28nm I/O Usage Guidelines
Released
28nm v1_0 I/O Usage Guidelines
cad_tl_00419
Note Id: 2942
Issue 1
Proprietary and Confidential to PMC-Sierra, Inc. 1

Document No.: cad_tl_00419, Issue 1
Released
Revision History
Iss Issue Date Author Reviewer Details of Change
No.
1 August 2013 Brendan Francis Brendan Francis Document created.
Justin Chan
Patrick DeVera
TABLE OF CONTENTS
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Revision History........................................................................................................................................... 2
TABLE OF CONTENTS............................................................................................................................... 3
LIST OF TABLES......................................................................................................................................... 6
1.1 Known Issues............................................................................................................................... 8
2.1 Eng-docs.................................................................................................................................... 10
2.2 QA plans.................................................................................................................................... 10
2.3 Model docs................................................................................................................................. 10
2.4 Misc........................................................................................................................................... 10
3.1 Flip Chip Libraries...................................................................................................................... 11
3.1.1 1.8V LVCMOS, & Analog I/O (library name: pm20_00_216_fc).............................................11
3.1.2 1.8V LVDS RX (library name: pm20_00_217_fc)...................................................................11
3.1.3 1.8V LVDS TX (library name: pm20_00_225_fc)....................................................................11
3.1.4 Flip-Chip Utility (library name: io_util_28nm_fc).....................................................................11
3.1.5 TSMC CSR and Seal-ring (library name: tsmc_csr_seal)......................................................12
3.2 Additional resources:................................................................................................................. 12
4.1 Cadence/ExtremeDA Tool Setup................................................................................................ 13
4.2 IO Library setup......................................................................................................................... 13
4.3 Gate-level Simulation................................................................................................................. 13
5.1 Decap assumptions for SSO validity.........................................................................................15
5.2 Applying Uncertainties............................................................................................................... 16
5.3 IO OCV Pessimism Removal..................................................................................................... 17
5.4 Maximum Frequency................................................................................................................. 18
5.4.1 Drive strength selection.......................................................................................................... 18
6.1 North-South and East-West pad variants...................................................................................19
6.2 Description of I/O covercells...................................................................................................... 19
6.3 Pad and cut-cell general rules.................................................................................................... 20
6.3.1 Cut cell usage rules................................................................................................................ 22
6.3.2 Thermal diode usage rules..................................................................................................... 24
6.3.3 I/O abutment combination restrictions....................................................................................25
6.3.4 Digital std-cell placement guidelines near Digital I/O.............................................................25
6.4 I/O covercell usage rules............................................................................................................ 26
6.4.1 General covercell VBUS rules................................................................................................26
6.4.2 Covercell and pad specific VBUS restrictions........................................................................27
6.4.3 Cut cell impacts on VBUS...................................................................................................... 28
6.4.4 Padring VSS isolation............................................................................................................ 30
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6.4.5 Covercell placement limitations.............................................................................................. 30

6.5 Corner bumps / rules................................................................................................................. 32
6.6 User Added Decaps................................................................................................................... 32
6.7 Core Clamp and Back to Back Diodes.......................................................................................33
6.8 Efuse.......................................................................................................................................... 34
6.9 DTM........................................................................................................................................... 34
6.10 Sense pad.................................................................................................................................. 34
6.11 PMON PM20_00_218................................................................................................................ 35
6.12 Seal ring Placement................................................................................................................... 35
6.13 Layer-ID and Logo cells............................................................................................................. 36
7.1 Max power density under IO covercell.......................................................................................37
7.1.1 Power Density Calculation..................................................................................................... 37
7.2 I/O Power................................................................................................................................... 39
7.2.1 Power per pad........................................................................................................................ 39
7.2.2 Configurations violating bump EM limits................................................................................40
9.1 Running the Script (TA usage only)............................................................................................ 41
9.2 Reviewing Results..................................................................................................................... 41
9.3 Known Limitations...................................................................................................................... 42

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LIST OF FIGURES
FIGURE 1 APPROVED IO COVERCELLS, SHOWN IN ORIENTATION USED ON DIE LEFT EDGE.......................................20
FIGURE 2 - SAMPLE STD-CELL PLACEMENT, RESPECTING REQUIRED LATCH-UP RULES................................................26
FIGURE 3 VALID CONFIGURATIONS FOR USING CUTCOREPG_216_216* CELLS..........................................................29
FIGURE 4 STANDARD PATTERN FOR CORE BUMPS.......................................................................................................31
FIGURE 5 - SENSE PAD SCHEMATIC...............................................................................................................................34
FIGURE 6 LAYER-ID AND LOGO PLACEMENT..............................................................................................................36
Figure 7 Power density area calculation for lvcmos18 fc type covers...................................................................39

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LIST OF TABLES
TABLE 1 I/O DIMENSIONS.............................................................................................................................................7

TABLE 2 OXIDE REQUIRED BY 28NM I/OS...................................................................................................................8
TABLE 3 I/O INTERFACES...........................................................................................................................................14
TABLE 4 LOAD AND PG-RATIO FOR SSO GENERATION.........................................................................................15
TABLE 5 MAX LOAD AND FREQUENCY FOR LVCMOS18_OD PADS, FOR GENERIC APPLICATION.................................15
TABLE 6 28NM I/O MAXIMUM OPERATING FREQUENCY LINKS (FUNCTIONAL MODE DESIGN FREQUENCY)...........18
TABLE 7 28NM I/O COVERCELLS................................................................................................................................19
TABLE 8 COVERCELL SIGNAL SLOT AND PAD COMPATIBILITY...................................................................................21
TABLE 9 DECAP AND SPACER CELL DECAP ATTRIBUTES............................................................................................32
TABLE 10 LIST OF SEALRING AND CDU CELLS.........................................................................................................35
TABLE 11 POWER DENSITY RATING FOR FC TYPE I/O COVERCELLS...........................................................................37
Table 12 Max pad load to avoid bump EM audit.......................................................................................................40

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1 Overview
This document is part of the 28nm digital I/O ICDC component and contains usage
guidelines for 28nm v1_0 I/Os. All I/Os within library release v1_0 have gone
through QA and are ready for production release, available at:
/home/liblib/28n/ios/v1_0
The attached spreadsheet shows all the cells supported in v1_0.
28nm_Cell_List.xlsx
All I/O types may be used on a single device. If this is done, issues such as power
supply isolation on both the die and package will need to be considered.
The bi-directional I/Os in the LVCMOS libraries are provided and will be used even
where input and/or output-only pads are required. To do this, tie the output enable
pin appropriately. Output only-configurations must have register programmable
output enable pins such that the output drivers may be configured in high-
impedance (hi-Z) mode for leakage testing. It is recommended that the bi-
directional I/Os with Schmitt-trigger functionality should only be used for reset
pads. Do not use the Schmitt pads as an input-only data or clock pad.
Note that, to be reliability, no I/O in 28nm can tolerate significant voltage when not
powered due to parasitic diodes. Please consult with Technology Access or I/O
Development group if you are not certain.
Table 1 lists the dimensions of the various types of IOs released in the v1_0
library:
Table 1 I/O dimensions
Cell Library Width Height
analog_atbh_ew pm20_00_216_fc 130 35
analog_atbh_ns pm20_00_216_fc 35 130
analog_atbl_ew pm20_00_216_fc 130 35
analog_atbl_ns pm20_00_216_fc 35 130
analog_hv_ew pm20_00_216_fc 130 35
analog_hv_ns pm20_00_216_fc 35 130
analog_lv_ew pm20_00_216_fc 130 35
analog_lv_ns pm20_00_216_fc 35 130
lvcmos18_ew pm20_00_216_fc 130 35
lvcmos18_ns pm20_00_216_fc 35 130
lvcmos18_atb_ew pm20_00_216_fc 145 35
lvcmos18_atb_ns pm20_00_216_fc 35 145
lvcmos18_od_ew pm20_00_216_fc 175 35
lvcmos18_od_ns pm20_00_216_fc 35 175
lvcmos18_vdd_ew pm20_00_216_fc 130 30

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lvcmos18_vdd_ns pm20_00_216_fc 30 130

lvcmos18_vddo_ew pm20_00_216_fc 130 30
lvcmos18_vddo_ns pm20_00_216_fc 30 130
lvcmos18_vddo_pd_ew pm20_00_216_fc 145 30
lvcmos18_vddo_pd_ns pm20_00_216_fc 30 145
thermal_diode_ew pm20_00_216_fc 145 105
thermal_diode_ns pm20_00_216_fc 105 145
lvds18_rx_noterm_ew pm20_00_217_fc 175 70
lvds18_rx_noterm_ns pm20_00_217_fc 70 175
lvds18_rx_term_ew pm20_00_217_fc 175 70
lvds18_rx_term_ns pm20_00_217_fc 70 175
lvds18_tx_ew pm20_00_225_fc 185 70
lvds18_tx_ns pm20_00_225_fc 70 185
lvds18_vref_ew pm20_00_225_fc 185 35
lvds18_vref_ns pm20_00_225_fc 35 185
NOTE: Dimension are all pre-shrink, silicon dimension will be 0.9 of what listed above
Table 2 lists the oxides used in each of the various types of IOs released in the
v1_0 library:
Table 2 Oxide required by 28nm I/Os
Library Library Oxide
1.8V LVCMOS pm20_00_216_f 0.9V & 1.8V
c
1.8V LVDS RX pm20_00_217_f 0.9V & 1.8V
c
1.8V LVDS TX pm20_00_225_f 0.9V & 1.8V
c
1 Known Issues
The v1_0 library only supports 702 metal stack. If a different metal stack is
required file a CAD_PREP to request. All of the v1_0 IOs are designed using M8 as
the highest layer, and therefore can be used in 702 or 7011 stack configurations
depending on the covercells used.
o Verilog/.lib/vital model for covercells lacking VDD bump do not contain a
VDD pin. This is tracked in CAD_PREP 112507
o 315218 28nm LVDS_Rx worst case DCD numbers
o 307950 DC Current Capability of 1.8V LVCMOS IO`s

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o 314481 Request fix for LUP.2.1u violation in certain abutment combinations

o 308080 DC Spec violation for LVDS TX 28nm Prop request filed
o 300600 Power off leakage spec waive off for LVDS TX 28nm Prop request
filed
o 290038 Document Input Leakage Current Prop request filed
Note: The 25 signal covercell lvcmos18_25s_corner_fc is not available for production. It can
be provided in a beta library only, upon special request to tech-access. Again, it is NOT TAPE-OUT
READY. Backend verification is required before being put into production, and this will require some
lead time to arrange resources. If your project wishes to use this cell, please contact Technology-
Access IO group at least 4 months before your tape-in date.

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2 Reference Documentation
Reference documents for the various IO libraries, QA/model plans, and rules and
procedures are given below.
2 Eng-docs
PMC-2122797 1.8V LVCMOS 28nm GPIO in TSMC HPM Process Engineering Document
PMC-2122853 1.8V LVDS RX 28nm GPIO in TSMC HPM Process Engineering Document
PMC-2130128 1.8V LVDS TX 28nm GPIO in TSMC HPM Process Engineering Document
3 QA plans
PMC-2121753 1.8V LVCMOS 28nm I/O QA plan
PMC-2121754 1.8V LVDS RX 28nm I/O QA plan
PMC-2130475 1.8V LVDS TX 28nm I/O QA plan
4 Model docs
PMC-2123610 Model Generation Plan and Usage Guide for PM20_00_216_A 28nm 1.8V LVCMOS I/Os
PMC-2131583 Model Generation Plan and Usage Guide for PM20_00_217_A 28nm 1.8V LVDS RX I/Os
PMC-2124009 Model Generation Plan and Usage Guide for PM20_00_225_A 28nm 1.8V LVDS TX I/Os
5 Misc
IO SSO Generation Guidelines IO SSO Generation Guidelines
28nm IO Integration Design Specification 28nm IO Integration Design Specification
28n_covercells.vsd 28nm Covercell and VBUS testcase design document
28nm_Cell_List.xlsx 28nm IO and covercell cell list, and cut cell diagrams
28nm v1_0 IO Uncertainties 28nm v1_0 IO Uncertainties
PMC-2011270 I/O QA Procedure
PMC-1960315 Assembly Design Rules
PMC-2002148 Top-level Design for Testability Methodologies
efuse_appnote_28n.doc 28nm Efuse Application Note

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3 Approved IO Libraries
Release v1_0 supports 702 Flip Chip (FC) configurations only. If you need a
different metal stack option, please file an enhancement PREP. The general
expectation is no wire-bond implementation will be needed, the flip-chip package
cost should be low enough that wire-bond is not needed anymore. Wirebond
configuration is theoretically supportable; if required file an enhancement prep to
request development of a set of wirebond covers and analysis.
6 Flip Chip Libraries

The following libraries are production tested for flip-chip usage.
6.1 1.8V LVCMOS, & Analog I/O (library name: pm20_00_216_fc)

Refer to the engineering document for full list of features and
implementation notes, PMC-2122797
Refer to the model doc for timing model and verilog model usage,
PMC-2123610
I/Os are 1.8V tolerant and drive 1.8V, they are not over-voltage
tolerant
Open Drain (OD) pad is tolerant to 3.3V+5% external pull-up, or
3.3V+10% with reduced performance.
For driving LED's the MODE[1:0] bits of the lvcmos18_od must be set
to '11' to get maximum DC current capability (=10mA) for a 10 year
continuous operation
6.2 1.8V LVDS RX (library name: pm20_00_217_fc)

PMC-2131583
I/O supply is 1.8V tolerant.
6.3 1.8V LVDS TX (library name: pm20_00_225_fc)

PMC-2124009
I/O supply is 1.8V tolerant. Receive pins are 2.4V tolerant

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6.4 Flip-Chip Utility (library name: io_util_28nm_fc)

This library contains all utility cells to create a flip chip padring
This library contains the logo and layerid cells for TSMC tapeout
Contains 0.9V clamp and b2b diode for special pad/core isolation
schemes
Only the 702 metal-stack is supported, please file a PREP if any other
metal stack is needed. Note ROI will be needed to justify the
development to support different metal stack Only
Only flip-chip environment is supported, please file a PREP if
wirebond is needed. Note ROI will be needed to justify the
development of wirebond
Only 160um post-shrink minimum effective pitch is supported, please
file a PREP if a tighter pitch is needed. Note ROI will be needed to
justify the development to support different bump pitch
6.5 TSMC CSR and Seal-ring (library name: tsmc_csr_seal)

Contains all utility cells required to implement the TSMC seal ring
structure.
There are no front-end models for this library
7 Additional resources:
Details on the covercell constructions, including bump pattern and pitch can be
found:
28n_covercells.vsd: 28nm Covercell and VBUS testcase design document
Details on the cells contained in each library, and the cut utility cells can be
found:
28nm_Cell_List.xlsx: 28nm IO and covercell cell list, and cut cell diagrams

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4 Supported Tools and Versions

8 Cadence/ExtremeDA Tool Setup
Please consult tool Index page here, for the latest RC/goldtime/ncsim (IES)
versions to use.
9 IO Library setup
There are 4 types of IO libraries, but all are loaded simultaneously. A primary
library from ARM std-cells is first loaded, and the IO can be loaded into the setup
via the use of -subordinate switch. For example:
set ::m_vdd_set_tech_lib_remap::base_lib_names(io) ios
::CAD::setup::set_tech_lib ios 28n $corner v1_0 subordinate
$corner can be any of the supported corners. Setup applies to both RC and
goldtime.
10 Gate-level Simulation
ncsim
o /tools/lib/configs/pmc_compile/techaccess_ios/28n/ios/28n_ios_v1_0.mlist

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5 I/O interface timing

For LVDS I/Os (pm20_00_217* and pm20_00_225*), consultation with SI is needed
to determine if detailed SI analysis is required. If SI analysis is not required, the
timing uncertainties listed in the next sections and the timing model in liblib
should be used to close timing.
For all other I/Os, STA must be done in conjunction with the Synopsys Tables
provided in /home/liblib and uncertainties described below. When selecting I/Os,
refer to the Synopsys Tables to estimate propagation delays (linear interpolation
between the standard loads is necessary). When performing STA, the specified
load should be the load actually seen by the pad (i.e., external load). The pads
parasitic capacitances have been accounted for in the Synopsys Tables.
To aid in timing closure, select the same I/O type and mode for both clock and
data. This avoids the introduction of additional circuit variations and will
therefore reduce timing variability between clock and data (e.g., DO NOT use a
Schmitt input on a clock).
Please note that this section only supplements the STA uncertainty section in the
PMC - TSMC 28nm Design Environment Release v1_3 (component id:
cad_tl_00418). When considering the uncertainty numbers, designers must start
with the PMC - TSMC 28nm Design Environment Release v1_3 document and
consult this section for additional details regarding the application of I/O
uncertainties.
There are 4 scenarios for I/O interfaces:
Table 3 I/O interfaces
# Scenario Uncertainty
1 Data and clock I/O are - Both pads may see the same SSO noise. If this is the case,
same type (could be only the difference in the SSO-induced pad delays for each pad
same or different drive is applied. The difference may be nil.
strength) and in the same - If the clock and data are out of phase by a significant amount
voltage domain (e.g., 500ps) then the pads may not see the same SSO noise. In
this case the SSO-induced pad delay &/or speed-up for both
data and clock I/Os must be applied.
- Pad voltages correlate so do not need opposite voltage
corners
- Duty cycle distortion applied to data pad
2 Data and clock I/O are - Add SSO uncertainty for clock and data pads
same type (could be - Account for uncorrelated voltage seen on two pads1
same or different drive - Duty cycle distortion applied for both data pad and clock pad
strength) but are in
different voltage domain

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# Scenario Uncertainty
3 Data and clock I/O are - Both pads see same SSO noise but being different types, the
different type but in the SSO uncertainty will be bigger.
same voltage domain - Pad voltage will correlate
- Duty cycle distortion applied for both data pad and clock pad
4 Data and clock I/O are - Add pad type specific SSO uncertainty for clock and data pads
different type, and, are in - Account for uncorrelated voltage seen on two pads1
different voltage domain - Duty cycle distortion applied for both data pad and clock pad
Note 1: Accounting for different voltage domains requires extra sim to run SSO
across voltage splits in each process corner.
Designers should always try to design their padring using scenario 1 above. The
uncertainties described below apply to scenario 1 above only, with only one
exception. The only exception is use of lvds18_rx as input combined with
lvds18_tx as output (a subset of scenario 3).
These uncertainties also assume the drive and loadings given in Table 4. The
SRCv flip-chip package model is used specifically for SSO analysis. For any larger
loading, worse PG ratio, or lower drive strength, please apply a flat 1.5ns
uncertainty.
Table 4 Load and PG-Ratio for SSO Generation
IO Type Load Freq Drive PG-Ratio
lvcmos18 5pF 200MHz Mode[1:0] = 11 7:1
lvds18_tx 100 1000MHz N/A 3:1 **
lvds18_rx N/A 1000MHz N/A 3:1
Note**: Only 2x lvds18_tx per PG pair is allowed due to EM limits. The SSO is conservative.
This document does not contain I/O uncertainty values. Please refer to the latest
published IO uncertainty values at:
28nm v1_0 IO Uncertainties
Table 5 Max Load and frequency for lvcmos18_od pads, for generic application
IO Type Load Freq
lvcmos18_od 200pf 500 KHz
lvcmos18_od 200pF 1 MHz
lvcmos18_od 110pF 5 MHz

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IO uncertainties are all provided for the maximum rate supported by the IO. Note however that the
uncertainties are dependent on the following:
1. Load is less that that provided in Table 4 and Table 5
2. Drive strength, where applicable, is maximum
3. For lower than maximum frequency, but HIGHER load than in Table 4 and Table
5, the uncertainty has not yet been validated.
In addition, the uncertainty characterization has several other requirements for
validity:
11 Decap assumptions for SSO validity

Generic Decap requirements:
LVCMOS Generic: IO Uncertainties assume 0pF Cdie for VDDO
LVDS RX Generic: IO Uncertainties assume 100pF Cdie for VDDO, per 3 pads
LVDS TX Generic: IO Uncertainties assume 50pF Cdie for VDDO, per 3 pads
Luxor specific Interface Decap requirements:

LVCMOS18 RGMII:
- See 298313. Uncertainty/decap needs are provided by SI directly
- For floorplan, please plan on 10pF of 1.8V cap per pad on VDDO until SI
finalizes
LVCMOS18 PDTRACE:
- See 298313. Uncertainty/decap needs are provided by SI directly
- For floorplan, please plan on 10pF of 1.8V cap per pad on VDDO until SI
finalizes
LVCMOS18 SPI: IO Uncertainties assume 0pF Cdie for VDDO
LVDS RX Isolated Source Clock (e.g. PCIe): 100pF VDDO, 50pF VDD, See
295794
LVDS TX Isolated Output Clock (e.g. PCIe): 100pF VDDO, 50pF VDD, See
295794
LVDS SCIF: Please contact TA for analysis
ISI expectations:
We assume that full ISI is included in the SSO number, and that it does not vary
with the frequency, load, and drive, but this is not necessarily the case.

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Especially for lvcmos IOs which handle a wider range of loads and drives, the ISI
can be expected to increase with frequency for a given load and drive strength.
12 Applying Uncertainties
I/O interfaces need additional uncertainty to account for delay variation caused by
several factors. The three most significant are Simultaneous Switching Outputs
(SSO), Duty-Cycle Distortion (DCD, the difference between rise and fall delay), and
power supply variation (e.g., injected noise from the board). Inter-symbol
interference (ISI delay variation with data pattern) is another contributing factor
but is typically relatively insignificant compared to the three major factors. Even
for the same I/O, uncertainty varies with drive strength and loading conditions.
If the data and clock I/Os are of same type and share the same voltage island (i.e.,
will see similar SSO effects and power supplies), then their performance
degradation is similar and the applied uncertainty may be smaller. The closer that
the clock is to the data, the more the SSO jitter will track but this correlation can
never be guaranteed. If the clock and data are out of phase by a significant
amount (e.g., 500ps) then the pads may not see the same SSO noise. By default,
the SSO number includes the full effects of phase offset, by sweeping the noise
pattern by Period*0.5 vs the measured signal. If the worst phase offset between
clock and data is known, and is less than a period, then the SSO data can be
recomputed to only account for the maximum delay-delta that can occur in a more
limited data set.
In this case the SSO-induced pad delay &/or speed-up for both data and clock I/Os
must be considered.
Conversely, if two I/Os are same or different types, sitting in un-correlated SSO
and voltage domains, then their total uncertainties are greater. The process and
temperature conditions are expected to be similar, but voltage will not track.
These types of interface (scenarios 2 and 4) are not supported at this time, as
SSO sims across voltage splits do not exist. Please discuss with TA well before
tape-in.
NOTE 1: All uncertainties described below can be obtained from the 28nm v1_0 IO
Uncertainties document linked to above
NOTE 2: Timing must be closed with uncertainty numbers specific to the I/O
library
13 IO OCV Pessimism Removal

I/O pads are made with thick oxide transistors, which are much less sensitive to the process variation
than the thin oxide transistors in the core; therefore the OCV applied to the I/O pads is a pessimism
that should be removed. However there is no STA procedure that automatically removes this
pessimism at this time.

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In Goldtime it is very easy to remove the OCV timing_derating on specific cells or instances. For
example, if you want to avoid any derating on the cells in the LVCMOS and LVDS libraries you can
add these commands after the LOCV setup but before the update_timing.
# read LOCV based derate tables ::CAD::setup::read_locv_tables
# Ensure CRPR is enabled for hold settings TTimer/RemoveClockReconvergencePessimism

1settings TTimer/ClockReconvergencePessimism same_transition
# Use CRPR threshold of 1ps unless there is a runtime issue

settings TTimer/TimeDanglingPaths 1
settings TTimer/CrprThresholdPs 0
set_operating_conditions -analysis_type on_chip_variation

#LOCV based settings settings TTimer/EnableGraphBasedLOCV true
# Define OCV values

set_timing_derate -locv_guardband -early [expr {1.0 - $ocv_derate_min}]
set_timing_derate -locv_guardband -late [expr {1.0 + $ocv_derate_max}]
#Begin Added lines:

# Since IO PAD delays are dominated by thick-oxide logic there is no requirement to timing derate them
like other std cells
set_timing_derate -locv_guardband -late 1.0 [get_lib_cell "pm20_00_216_fc/* pm20_00_217_fc/*
pm20_00_225_fc/*"]
set_timing_derate -locv_guardband -early 1.0 [get_lib_cell "pm20_00_216_fc/* pm20_00_217_fc/*
pm20_00_225_fc/*"]

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14 Maximum Frequency
Table 6 lists where to find the maximum operating frequency for all 28nm I/Os.
None of the I/Os should be running at a rate higher then the specified limit. When
higher performance I/O is required, please consult with the Mixed-Signal I/O
Development and Technology Access I/O Delivery groups. Please keep in mind that
the maximum frequency is dependent on load drive and SI considerations. Please
see the listed eng-doc sections for additional details.
Table 6 28nm I/O maximum operating frequency links (functional mode design frequency)
Library PM number Eng-Doc See eng-doc

section:
1.8V LVCMOS pm20_00_216 PMC-2122797 12.1.1
1.8V LVCMOS OD pm20_00_216 PMC-2122797 12.1.1
1.8V LVDS RX pm20_00_217 PMC-2122853 10
1.8V LVDS TX pm20_00_225 PMC-2130128 11
Note that when LVCMOS I/Os are running at >75MHz combined with multi-drop load and/or long trace
lengths, signal integrity effects may impact performance. Please consult with Signal Integrity group for
any LVCMOS I/O > 75MHz.
Note that for LVDS pads, the uncertainties and DCD are strongly dependent on package, load,
frequency, slew-rate and Vod/Vid. Please contact SI for review of all LVDS interfaces.
14.1 Drive strength selection

For 1.8V lvcmos pads, drive strength is programmable, per section 12.1.1 of the eng-doc (see
Table 6). For non-timing sensitive applications which use the default 1.5ns IO-uncertainty
number, the drive strength may be selected according to the Maximum frequency for each
specified load+drive combination in the matrix tables 25/26 of the eng-doc.

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6 Padring Layout Design rules

This section describes how to layout a 28nm Flip-Chip pad ring. PD and layout designers should
consult with this document for all 28nm Flip-Chip pad ring designs. This document assumes some
familiarity with padring flow, and general concepts, including:
What a padring is, the difference between flip-chip and wirebond, and what covercells are
How to use a padring generation (orbit IO) or layout flow (Aprisa)
The primary target audiences for this document are:
Product-designers responsible for floor planning and/or padring design
ICPD engineers working on top-level layout
The 28nm process at PMC is drawn in layout using 32nm dimensions, and then during silicon
production these are optically shrunk down to 28nm. All dimensions in this document are given in the
drawn pre-shrink dimension unless otherwise noted. To convert from drawn dimension to silicon
dimension, multiply given drawn sizes by a factor of 0.9. For area, multiply given drawn area by a
factor of 0.81.
15 North-South and East-West pad variants

The 28nm low voltage POLY rules require that all low-voltage poly is aligned in the same direction on
die. Since IOs all contain some low-poly devices, this means that there is a separate version of the IO
for use in R0 and R180 (North-South) orientations vs. R90 and R270 (East-West) Orientations. The
cells for North-South and East-West have the same base name, but use the suffix ns and ew
respectively. All IOs placed on the North or South edges of the die MUST use ns type IOs. All IOs
placed on the East or West edges of the die MUST use ew type IOs.
For the remainder of the document, no distinction will be made between ns and ew pads. So, for
example given:
lvcmos18_ns
lvcmos18_ew
These pads will collectively be referred to as lvcmos18_*. It will always be assumed that as
designer, you will select the correct ns or ew pad variant for the correct edge of the die.
16 Description of I/O covercells

The v1_0 io_util_28nm_fc contains 4 covercells which are approved for use given in Table 7. There is
additionally a high-density corner covercell, which is not yet approved
Table 7 28nm I/O covercells
Covercell # Signal bumps Approval for v1_0 Notes

lvcmos18_7s_vss_312_fc 7 Approved
lvcmos18_7s_vdd_312_fc 7 Approved
lvcmos18_3s_lef_156_fc 3 Approved
lvcmos18_3s_right_156_fc 3 Approved
lvcmos18_25s_corner_fc 25 Not Approved

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The physical design of the covercells is illustrated below in Figure 1:
Figure 1 Approved IO Covercells, shown in orientation used on die left edge

Each covercell contains a number of signal slots where a signal pad is intended to be placed equal to
the number of signal bumps. Additionally, each contains one or more vddo slots, and may contain a
vdd slots; The number of vdd and vddo slots does not necessarily map 1:1 between the number of
slots and respective bumps in each covercell.
17 Pad and cut-cell general rules

The 28nm IOs have been designed to be very lenient in terms of compatibility between the signal slots
and the type of pads which are allowed to be placed in those slots. In general using the orbitIO
decoration rule defaults will produce DRC correct results, but it is always required to do some of the
following tasks:
1. Change pad to types other than the default

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2. Replace a signal pad with a power pad to increase ESD performance

3. Replace a signal pad with a large spacer to increase padring VDDO to VSS decap
4. Add a cut-cell to implement power isolation
For the purposes of changing signals (1.), power pads (2.), and large decap spacers (3.) The
compatibility for each covercell is given in Table 8. Cut cell usage (4.) is described in section 17.1.
Table 8 Covercell signal slot and pad compatibility
lvcmos18_7s_vdd_312_fc
lvcmos18_3s_lef_156_fc
lvcmos18_3s_right_156_fc
Note
lvcmos18_7s_vss_312_fc
Pad Type
analog* S1 though S7 S1 though S7 S1 though S3 S1 though S3 1

lvcmos18* S1 though S7 S1 though S7 S1 though S3 S1 though S3 1,3
thermal_diode* S1+S2+S3 OR S1+S2+S3 OR S1+S2+S3 S1+S2+S3 1
S2+S3+S4 OR S2+S3+S4 OR
S5+S6+S7 S5+S6+S7
lvds18_tx* Allowed: Allowed: Allowed: Allowed: 1,2
S1+S2 OR S1+S2 OR S3+S2 S1+S2
S3+S4 OR S3+S4 OR Not Allowed: Not Allowed:
S5+S6 S5+S6 S2+S3 S2+S3
Not Allowed: Not Allowed:
S2+S3 OR S2+S3 OR
S6+S7 S6+S7
lvds18_vref* S1 though S7 S1 though S7 S1 though S3 S1 though S3 1
lvds18_rx* Allowed: Allowed: Allowed: Allowed: 1,2
S1+S2 OR S1+S2 OR S3+S2 S1+S2
S3+S4 OR S3+S4 OR Not Allowed: Not Allowed:
S5+S6 S5+S6 S2+S3 S2+S3
Not Allowed: Not Allowed:
S2+S3 OR S2+S3 OR
S6+S7 S6+S7
sp35000_216* S1 though S7 S1 though S7 S1 though S3 S1 though S3 1
sp15000_216* No No No No 1,4
sp05000_216* No No No No 1,4
sp02000_216* No No No No 1,5
sp01000_216* No No No No 1,5
sp00100_216* No No No No 1,5

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Note 1: Please consult the cell list tab of 28nm_Cell_List.xlsx for the full list of IO types with a wildcard * in the name.
Note 2: lvds18* restrictions are purely an SI consideration so that lvds signal traces can be routed off chip in package next
to one another. If required, consult TA+Substrate+SI for waiver of this requirement.
Note 3: lvcmos18* includes power pads, e.g. lvcmos18_vddo_ns and lvcmos18_vdd_ew, etc. Compatibility for these
power pads is treated the same as for signal pads.
Note 4: 15um and 5um spacers are generally not needed to fill an unused signal slot, and it is always recommended to
use the 35um spacer instead, so that it provides the most decap.
Note 5: In signal slots, 0.1um/1um/2um spacers should only be used to pad the lvcmos18 power pads out to a width of
35um with 2.5um of spacer on each side. The power pads are 30um wide and this ensures that the pad is
centered over the pad signal connection with no DRC violation.
Any of the signals may be exchanged with this sequence of spacers and power pad:
sp00100_216_*
sp00100_216_*
sp00100_216_*
sp00100_216_*
sp00100_216_*
sp02000_216_*
lvcmos18_vddo_* OR lvcmos18_vdd_*
sp02000_216_*
sp00100_216_*
sp00100_216_*
sp00100_216_*
sp00100_216_*
sp00100_216_*
17.1 Cut cell usage rules

The cut cell usage is dependent on the covercell. For each of the four types of approved
covercells, the following section will list all of the slots in the covercell filler segments, signal
slots, and power slots. The cut-cell and spacer compatibility for each of the filler slots will be
described, along with the power isolation that can be achieved for each.
Covercells:
lvcmos18_7s_vdd_312_fc
lvcmos18_7s_vss_312_fc:
Pattern:
Filler slot cut-cell and spacer compatibility:

filler left:
cutvdd_216_216_* may be used to cut the VDD to any covercell placed to the left
cutvddo_216_216_* may be used to cut the VDDO to any covercell placed to the left

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2x dum01000_216_* may be used to cut the ALL power to any covercell placed to the left
2x sp01000_216_* or 1x sp02000_216_* will bridge ALL power in a butting covercell to left
filler center:
ONLY 1x sp02000_216_* and 1x sp01000_216_fc (in either order) may be placed in this slot.
No cutting is supported, and the filler placement is automatically handled in orbitIO
filler right:
cutvdd_216_216_* may be used to cut the VDD to any covercell placed to the right
cutvddo_216_216_* may be used to cut the VDDO to any covercell placed to the right
2x dum01000_216_* may be used to cut the ALL power to any covercell placed to the right
2x sp01000_216_* or 1x sp02000_216_* will bridge ALL power a butting covercell to right
Covercell:
lvcmos18_3s_left_156_fc
Pattern:

filler left 1:
cutcorepg_216_216_* may be used to cut VDD and VSS to any covercell placed to the left
sp15000_216_* will bridge ALL power in a butting covercell to the left
Note: Filler left 1 requires any cut/dum cell be placed to on the LEFTMOST edge of the slot, at
the covercell boundary. Any space left over can be filler with any size appropriate spacer cell.
Filler left 2 and filler left 3:

Use sp02000_216_* by default, or combine with filler left 1 to use a larger spacer if desired.
filler right:
2x sp01000_216_* or 1x sp02000_216_* will bridge ALL power in a butting covercell to right
Covercell:
Pattern:

Released

filler left 1:
2x sp01000_216_* or 1x sp02000_216_* will bridge ALL power a butting covercell to left
Filler right 1 and filler right 2:

Use sp02000_216_* by default, or combine with filler right 3 to use a larger spacer if desired.
filler right 3:
cutcorepg_216_216_* may be used to cut VDD and VSS to any covercell placed to the right
sp15000_216_* will bridge ALL power a butting covercell to right
Note: Filler right 3 requires any cut/dum cell be placed to on the RIGHT MOST edge of the slot,
at the covercell edge. Any remaining space can be filled with any size appropriate spacer cell.
17.2 Thermal diode usage rules

The thermal_diode_* cells provided in the pm20_00_216_fc library are 105um wide and require
three consecutive signal slots to be placed correctly.
The special requirement is that the CENTER of the three signal slots must be declared NO
CONNECT, as it contains no pin connection for the center signal. So for example, a thermal
diode placed across S1-S2-S3 would declare S2 as no-connect.
17.3 I/O abutment combination restrictions

In general, there are no restricted abutment combinations, except where
issues have been identified as below:
1) LUP.2.1u issue between certain IO abutments: prep 314481

With pads on left die edge, do not use these sequences:
top pad lvcmos18_ew or lvcmos18_atb_ew
bottom pad analog_atbl_ew or analog_atbl_ew
With pads on bottom die edge, do not use these sequences:

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right pad lvcmos18_ew or lvcmos18_atb_ew

left pad analog_atbl_ew or analog_atbl_ew
With pads on right die edge, do not use these sequences:
bottom pad lvcmos18_ew or lvcmos18_atb_ew
top pad analog_atbl_ew or analog_atbl_ew
With pads on top die edge, do not use these sequences:
left pad lvcmos18_ew or lvcmos18_atb_ew
right pad analog_atbl_ew or analog_atbl_ew
17.4 Digital std-cell placement guidelines near Digital I/O

Standard cells placed near any I/O may have some issues with latch-up due to strong injectors
from pad driver stages and ESD structures. Latch-up rules are generalized here to cover all
digital I/O libraries, but not any other MABC. Rules apply to:
Lvmcos/analog: PM20_00_216
LVDS-Rx: PM20_00_217
LVDS-Tx: PM20_00_225
Core Diode and Clamps: PM20_25_103
For all other MSDG supplied IP, refer to the appropriate eng-doc.
Latch-up rules are simple:
1. Digital std-cell must keep 15um away from all non-core edges of the I/Os
2. Digital std-cell are allowed to abut the core edge of I/Os (DRC not-withstanding)
Rule #1 always takes precedence over rule #2. Figure 2 illustrates the application of these rules:

Released
Figure 2 - Sample std-cell placement, respecting required latch-up rules

In the case of special applications (e.g. multi-row I/O covercell), where the I/O are inset from the
die edge, the I/O edge that normally butts the die-edge is to be treated as non-core, and the
keep-out spacing will apply.
18 I/O covercell usage rules

Covercell ESD performance has been evaluated for a number of common scenarios, allowing for
recommendations of the minimum required configurations needed to meet VBUS rules. Details of the
construction of the test-benches used for validation of VBUS can be found in the 28n covercells
document. A summary of the rules follows:
18.1 General covercell VBUS rules

o A correct VDDO power domain requires at least TWO instances of the following
combination s of covercells. The covercells due not need to physically abut, but VDDO
and VSS must be connected in package:
o Any combo of lvcmos18_7s* covers, adding up to two or more covers
o One or more lvcmos18_7s* covers with one or more lvcmos18_3s* cover s
o None of the covers need to be abutting on die, but can rely fully on a package
connection with VDDO and VSS Rbus < 0.1. Nonetheless it is always

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recommended to abut all covers in the same domain together in groups of at

least two, wherever possible.
o Not allowed: lvcmos18_3s* covers on their own cant form a valid VDDO domain
unless VBUS verification is performed
o A correct VDDO domain can also be constructed in a single covercell by swapping S4 for
a lvcmos18_vddo* pad.
o Only applies to lvcmos18_7s_vdd_312_fc lvcmos18_7s_vss_312_fc
o Not allowed: Swapping any other signal S1-S3 or S5-S7 for a VDDO pad is not
verified as sufficient for creating a correct VDDO domain. Otherwise VBUS
analysis is required
o A correct VDD domain requires at least THREE instances of the following combinations
of covercells when the domain DOES contain analog_atbl or analog_lv* type pads.
The covercells due not need to physically abut, but VDD and VSS must be connected in
package:
o Three or more lvcmos18_7s_vdd_312_fc covers
connection with VDD and VSS Rbus < 0.1. Nonetheless it is always
o Not allowed: Neither lvcmos18_7s_vss_312_fc covers, nor the lvcmos18_3s*
covers contain a VDD bump, and therefore MUST NOT be counted towards
meeting the three cover requirement. This requirement is driven by the need for
the vdd clamp to have access to VDD bumps in order to provide protection for
analog_atbl or analog_lv* type pads.
o A correct VDD domain only requires at least TWO instances of the following
combinations of covercells, when the domain DOES NOT CONTAIN analog_atbl or
analog_lv* type pads. The covercells due not need to physically abut, but VDD and
VSS must be connected in package.
o Three or more lvcmos18_7s_vdd_312_fc covers
connection with VDD and VSS Rbus < 0.1. Nonetheless it is always
18.2 Covercell and pad specific VBUS restrictions

o Any cover without a VDD bump is FORBIDDEN from containing:
o Not allowed: analog_atbl or analog_lv* type pads
o Applies to these covers:
Released
lvcmos18_7s_vss_312_fc
lvcmos18_3s_left_156_fc
18.3 Cut cell impacts on VBUS

If cut-cells are used according to the guidelines in 17.1, then the following additional VBUS rules
apply.
o A cutvddo_216_216* cell is able to break the VDDO domain on either side of the cut cell,
and for the purpose of VBUS, the covercells and pads on each side are considered to be
NOT ABUTTING. The VDDO domain can be reconnected in package if desired to satisfy
the general VBUS rules of 18.1.
o A cutvdd_216_216* cell is able to break the VDD domain on either side of the cut cell,
and for the purpose of VBUS, the covercells and pads on each side are considered to be
NOT ABUTTING. The VDD domain can be reconnected in package if desired to satisfy
the general VBUS rules of 18.1.
o A cutcorepg_216_216* cell is able to break the VDD AND VSS domain on either side of
the cut cell, and for the purpose of VBUS, the covercells and pads on each side are
considered to be NOT ABUTTING. The VDD domain can be reconnected in package if
desired to satisfy the general VBUS rules of 18.1. The VSS domain in general MUST
be reconnected in the package; otherwise back to back diodes to global VSS are
required! (see section 21 for b2b diode usage). Proper usage of the
cutcorepg_216_216* cells has additional requirements:
o The cell must connect to a VSS bump through the VSS_L port, and must connect
to a different VSS bump through the VSS_R port. The maximum VBUS between
the VSS_L-VSS bump and the VSS_R-VSS bump is 1V. This is taken care of
automatically by only using the cutcorepg cell in the following configurations:

Released
Figure 3 Valid configurations for using cutcorepg_216_216* cells

Figure 3 shows the two valid configurations for the cutcorepg_216_216* cells, with a schematic
representation of the VSS_L and VSS_R routing to the nearest covercell VSS bumps. The two
valid configurations are:
A. Any lvcmos18_7s* cover with the lvcmos18_3s_left_156_fc cover butting to the right.
The cutcorepg_216_216* cell is placed in the lvcmos18_3s_left_156_fc cover per the
guidance in section 17.1.
B. Any lvcmos18_7s* cover with the lvcmos18_3s_right_156_fc cover butting to the left.
The cutcorepg_216_216* cell is placed in the lvcmos18_3s_right_156_fc cover per the
guidance in section 17.1.
Using either of these configurations may result in an isolated VSS domain on die AND package if
the VSS domain is not reconnected in the package. To keep VSS isolation, special requirements
are in place, described in section 18.4.
18.4 Padring VSS isolation

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Any region which has isolated VSS requires special attention. There are two
scenarios:
A. VSS is isolated only on die, but reconnected to global VSS in the
package
B. VSS is isolated on the die AND in the package.
For scenario A, the following requirements apply:
- Insert 1x back-to-back diodes between isolated VSS and global VSS,
following guidelines in section 21.
For scenario B, the following requirements apply:

- Insert 4x back-to-back diodes between isolated VSS and global VSS,
following guidelines in section 21.
- Draw an NTN ring required around the entire isolated VSS region (s),
1um is sufficient, but a thicker ring will provide improved isolation. If
the isolated VSS region has multiple segments, e.g. MABC + std-cell +
IO all on isolated VSS, then each section can be either individually, or
collectively grouped inside an NTN ring. A single collective ring is
recommended for simplicity.
- NTN ring requires 1um spacing to all other structures except seal ring
- For isolated IO covercell, covercell needs to be moved in from die edge
by 2um or more (1um space + NTN ring thickness)
- back-to-back diodes can sit inside or outside of the NTN ring, since
they contain and integrated NTN ring already.
18.5 Covercell placement limitations
18.5.1 Abutment rules for IO cover

1. lvcmos18_3s_left_fc can only be placed:
A. Abutting to the left of lvcmos18_3s_right_fc
B. Abutting to the right of either lvcmos18_7s* covercell, as in Figure 3 Config (A)
2. lvcmos18_3s_right_fc can only be placed:

A. Abutting to the right of lvcmos18_3s_left_fc
B. Abutting to the left of either lvcmos18_7s* covercell, as in Figure 3 Config (B)

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3. None of the lvcmos18_7s/3s covers may abut PERPINDICULAR to one another (e.g.
trying to minimize space between covercells on adjacent edges of the die).
A. The MINIMUM space for butting the top of one cover from the side of another cover
is 10.9um
B. This requirement does not apply to lvcmos18_25s_corner_fc, which is specifically
designed for such abutment in the corner region.
18.5.2 Placement for core covercells

Core covercells have several placement restrictions:
A. Any core bump which contains VSS/VDD/dummy bump is not allowed to be placed
directly left/right or above/below to any other such bump - they must be separated
by a fill type core bump. Core bump are allowed to be placed next to each other
with corners touching. The recommended pattern is:
Figure 4 Standard pattern for core bumps

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B. A core bump must not abut to the side of an IO covercell (top and bottom are ok). This
is to avoid minimum spacing violations between the core bumps and the bumps in the IO
covercell. Due to irregular pattern and different pitch between core and IO covers,
achieving proper DRC clean alignment is not tested.
C. A fill type bump is allowed to abut the side of any IO covercell.
D. Core covercell butting core edge of IO covers has a special set of rules.
a. The core bump must be in line with the IO covercell. E.g. For IO covercell in R0
orientation with top-edge at x=0, y=1108.7; then core bump bottom-left corner is
also at {x=0,y=1108.7}, or {x=156, y=1108.7}.
b. The Core must have a similar orientation to the IO covercell, so that M9 pins are
continuous and prevent M9 spacing violations. E.g. If IO covercell is R0 or
R180, then core covercell is also R0 or R180. Similarly, if the IO covercell is
R90 or R270, then the core covercell is also R90 or R270.
c. It will be difficult or impossible, depending on the device, to have the core covers
aligned with the IO covers on all edges of the die. For cases where alignment is
not practical, keep at least a 10um gap (arbitrary) to allow AP to be routed using
Aprisa.
E. Core covercell near, but not-butting the core edge of IO cover has recommended use:
a. Method one: Connect using set_param_tie in Aprisa:
i. There is no need to align core covercell with IO covercell. User just
needs to make sure the M9 mesh pins inside both core covercell and IO
cover are aligned perfectly, taking VSS/VDD pin type in consideration.
ii. For the P/G connection between core covercell and EW version IO
covercell , we can also use AP to join the horizontal AP mesh pin in core
covercell and the horizontal M9 mesh pin in EW IO covercell.
b. Method two:
i. Use core_strip_interface_156_fc/core_strip_rotated_156_fc
ii. These are placed between the core covercell and IO covercell with a
specific gap between IO and cover.
iii. Gap must be a multiple of the core_strip* cell width
iv. Core cover boundary must be aligned with edge of IO cover boundary
Some extra notes:
There had been some discussion with assembly on having double rows of VDD and VSS bumps
to reduce the risk of short between VDD and VSS bumps in the packaging. This would mean
instead of alternating rows from VDD to VSS and repeat, it would go VDD VDD VSS VSS
and repeat. However, this was not feasible for Luxor as this increases the space between VDD
and VSS bumps such that the average IR drop increases significantly, discussed in prep 278069.
One caveat is that this discussion pertains to the core bumps with 156um x 156um tile size. With
a smaller tile size, the IR drop issues would lessen, and at the same time the double-rows would
provide more benefit.

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19 Corner bumps / rules

Bumps at the die corner are subject to restrictive rules on how close to the corner bumps may be, and
the types of bumps that may be used. At all times, the assembly design rules document is the golden
source for all corner related rules. Please refer to the section titled Bump Placement.
20 User Added Decaps

The io_util_28nm_fc library provides two flavors of 1.8V decap cells, and additionally, two varieties of
spacer cells, each in ns and ew orientations can be substituted into the padring for added decap.
Table 9 Decap and Spacer cell decap attributes

Cell Width Height Decap Value
C=4.7664pF,
decap18_35p23x22p55_m4 35.23 22.55
R=104.748
C=5.0876pF,
decap18_35p23x22p55_m6 35.23 22.55
R=98.3286
sp15000_216_ew 15 130 6.864pF
sp15000_216_ns 15 130 6.864pF
sp35000_216_ew 35 130 16.016pF
sp35000_216_ns 35 130 16.016pF
The decap* cells may be placed anywhere in the device core region between a 1.8V supply and
ground. Alternatively, they may be placed between a 0.9V supply and ground, with lowered varactor
cap. For voltage down to 0.9V, please derate effective capacitance by 3%.
Important 1: The decap18_35p23x22p55_m4 may NOT abut decap18_35p23x22p55_m6
Important 2: The decap* cells require a 16um device keep-out in all directions. This includes
IOs standard cells, and ABCs. Waiver is not possible as the high poly density of these caps
induces un-modeled variation in cells within this region. PO/OD fill and any metal inside the
keepout region are acceptable with no review or waiver.
The sp15/35* spacer cells may be substituted freely into any signal slot in an IO covercell. When
making such substitutions, the associated bump must be declared NO CONNECT.
The additional decap requirements for pads are largely driven by the SI simulations (SSO sims).
These sims may be generic, or specific to a particular interface. Some guidelines on decap amount
per interface are provided in section 11 Decap assumptions for SSO validity.
21 Core Clamp and Back to Back Diodes

These cells are to be instantiated as directed by TA when a specific interface or core domain requires
additional ESD protection on the top-level. Manual routing will need to be reviewed by MSL prior to
signoff.
General guidelines:

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Clamps are placed between supply and ground, and routing between nearest supply bump and
nearest ground bump must meet total VBUS of 1V at 2A using the ESD metal-sheet-resistance values.
The following clamps are available:
clamp_p9v_bigfet_fullsize_h Use in horizontal orientation. It is for 0.9V/1.0V supply only
clamp_p9v_bigfet_fullsize_v Use in vertical orientation. It is for 0.9V/1.0V supply only
Back to back diodes are placed between two isolated grounds which have cross-domain signaling. If
the grounds are only isolated on die, then a single b2b diode is required. If the grounds are also
isolated in the package, then 4 b2b diodes in parallel are required. Routing between nearest bump of
ground #1 and nearest bump of ground #2 must meet total VBUS of 1V at 2A using the ESD metal-
sheet-resistance values. The following diodes are available:
bb_diode_wCC_M8_h Use in horizontal orientation.
bb_diode_wCC_M8_v Use in vertical orientation.
22 Efuse
Efuse is released through component LW20_00_222_A. To use, please checkout the latest tag, and
refer to the appnote:
efuse_appnote_28n.doc
Vault:
http://bby-ms-svn05:10038/svn/LW20_00_222_A/
23 DTM
The DTM is released through component PM88_60_155_A and LW20_25_108_A. To use, please
checkout the latest tag, and refer to the appnote:
dtm_appnote_28n.doc
Vault:
DTM: http://bby-dd-svn02:20020/svn/PM88_60_155_A/
DTM ESD: http://bby-ms-svn05:10038/svn/LW20_25_108_A/
24 Sense pad
Sense pad implementation is very simple for 28nm, due to the addition of a large resistance inside the
analog_lv/hv* pads. For each supply or ground sense connection:
1. Instantiate analog_lv_ns or analog_lv_ew pad to sense a supply < 1.0V, or ground
2. Instantiate analog_hv_ns or analog_hv_ew pad to sense a supply > 1.0V, or ground

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3. Route metal from pad to nearest supply bump being sensed. Use a separate net from the supply
net to prevent adding VIA to the supply along the path. Add source dummy resistor between the
added net and sensed supply/ground to pass LVS.
There is no resistance or metal width requirement for any sense-pad routing. Figure 5 shows a
sample schematic for the sense pad:
Figure 5 - Sense Pad Schematic
25 PMON PM20_00_218
When the PMON connects to the required 1.8V supply clamps, it will cause ESD.1g
violations on 0.9V MOS device and the 1.8V clamp.
To waive (see prep 316478), the ATBH pads which connect to the PMON must use
5x 1A HV clamps (e.g. 5.x lvcmos18_vddo pads ) this corresponds to using 5x
lvcmos18_7s_vdd_312_fc or lvcmos18_7s_vss_312_fc covercells in any combination.
The 1.8V supply of the PMON itself only needs to meet the standard requirement of
having 2x 1A 1.8V clamps.
Each VDDO clamp must be in its own covercell, otherwise the ESD group will need
to do some extra analysis to validate the waiver.
The requirement is captured in the PMON integration guidelines: 272566
26 Seal ring Placement

The seal ring for a flip-chip device is also placed using the provided sealring_utils.aptcl script. The
appropriate foundry (TSMC) script is called giving the metal stack (i.e. 702) as an argument, which
selects the appropriate cell set to use for that stack. For 702 devices, there are a total of four different
cells that are placed during the sealring placement step for TSMC, as detailed in Table 10:
Table 10 List of Sealring and CDU cells

Library Cell Description
tsmc_csr_seal seal40n_tsmc_702 Standard sealring cell
Sealring cell used to fill gaps between
tsmc_csr_seal seal40n_fill_tsmc_702
seal40n_tsmc_702 and csr28n_*_tsmc_702
tsmc_csr_seal csr28n_1_tsmc_702 CSR for upper lef and bottom right corners
tsmc_csr_seal csr28n_2_tsmc_702 CSR for lower lef and upper right corners
The complete procedure for placing the CSR, sealring and route-guide is as follows:

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1) Populate latest sealring script from vault:

http://cad-pd-svn02:30121/svn/cad_pd_00247/trunk/sealring_utils.aptcl
2) Follow the procedure as given based on the chosen foundry:
TSMC Procedure
## Load local utility script
source scripts/sealring_utils.tcl
## Add CSR (for TSMC)

::cad::addCornerCell_28n_TSMC 702
##Add Sealring and CDU cells (for TSMC)

::cad::addSealRing_28n_TSMC 702
27 Layer-ID and Logo cells

Layer-id and logo placement is up to the designers discretion in flip-chip devices, as there are no pre-
allocated regions in which to place the layer-id and logo cells. Cells are common to both TSMC and
UMC. The suggested steps for setting up the logo and layer id are as follows:
1. Reserve a location sufficient for layerid cells, logo, and part-id. The recommended location would
be in the area next to one of the CSR cells, as there will be no covercells in the way, however the
layerid and logo can be placed anywhere. If placed where a covercell would normally go, the
covercell will need to be deleted.
a. Create routing/placement blockages over the desired area, on all metal layers
b. 10um keep-out around the cells is sufficient for DRC
2. Perform chip design as usual, up to and including detailed routing
3. Delete the blockage, add the logo & layerid cells in the desired area
4. The logo and layer ID cells do not have an exclude layer, necessary to pass DRC. Flip-chip devices
require the layer be provided manually, or violations to be reviewed for each chip. For 28nm the
flow is to skip exclude layer and review that BAD_LOGO violations appear only on layerid and
logo cells. All other DRC must be clean.
The placement of all of the layerid and logo cells is shown in Figure 6. In this case a core covercell has
been removed to make room for the layerid and logo cells:

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Figure 6 layer-id and logo placement

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7 Power
28 Max power density under IO covercell
For each I/O covercell, there is a standard cell region available. However, the power density in these
standard cell regions is significantly reduced compared to the core region. Power density is used to
measure the maximum current that can be supplied per square micron. It is used as a first order
estimation to avoid bump EM issue. Each bump has a maximum current determined by the minimum
bump pitch used on the die, and is given in the assembly design rules. For the 28nm 160um bump-
pitch (silicon dimension), the limits in these examples are taken as 80mA per bump. Although some
bumping houses allow higher current limits on VSS bumps, regardless: the VDD/VDDO bump will limit
the current/pair to 80mA/pair.
In order to achieve a reasonable power density underneath the I/O covercell region, core VDD/VSS
bumps are added to the center of the I/O covercell when designing the bump pattern. This section will
use the lvcmos18_7s*_312_fc I/O covercells as an example to show how the power density is
calculated. Layout designers should obey the power density number listed in this document as a
starting point to avoid exceeding the bump EM specification, obeying the number does not guarantee
meeting specification. The golden chip-level IR drop analysis tool (EPS) should be used to verify the
bump EM specification is met.
Also, a -20% scaling factor is applied in the limits below to avoid EM issue early in the floorplan stage.
If you think your design will need to exceed the maximum power density, please file a PREP to CAD to
request proper analysis.
Maximum Power Density shows the maximum power density for various I/O covercells. Maximum
current per pair is limited by the current of the VDD bump, and is dependent on the minimum pitch of
balls in your device (since larger pitch can accommodate larger balls). Please see the assembly
design rules doc to determine the maximum current/pair applicable to your device.
Table 11 Power density rating for fc type I/O covercells
I/O covercell 80mA/pair

limit
lvcmos18_7s_vss_312_fc 115.2
lvcmos18_7s_vdd_312_fc 115.2
lvcmos18_3s_lef_156_fc 225.9
lvcmos18_3s_right_156_fc 225.9
IMPORTANT NOTES:
1) The above limits are for planning purposes only. The golden sign-off tool for EM limits is
EPS, and no bump EM violations are allowed (no waiver will be granted period).
2) The layout designer needs to exclude the IO VDDO and VSS bumps from the power analysis
to get a meaningful result from EPS. There is no flow in place for how include the IO
VDDO+VSS bumps and produce a meaningful result.
28.1 Power Density Calculation

The following assumptions are made when calculating the power density. Since the following
assumptions are ideal and may be different from a realistic scenario, the calculated power density is

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only used for first order estimation. The golden chip-level IR drop analysis tool should be used to
calculate the current draw from each core VDD/VSS bump to verify the bump EM limit is met.
Even current distribution across the entire standard cell region underneath the I/O covercell.
Current will always be supplied by the closest core VDD/VSS bump.
All available standard cell regions are used to place standard cells.
IOs consume no power through VDD/VSS bumps (thus I/O area is excluded)
IO covers alternate in the padring between VDD and VSS type
Figure 7 shows how to calculate the area supplied by the I/O VDD/VSS bump within the I/O covercell.
In each covercell, the first two bump (S7 location) are divided in half, which assumes that the top half
is supplied by core VDD/VSS bump in region 1, and the bottom half is supplied by VDD/VSS bump in
the I/O covercell. For the lvcmos18_7s_*_312_fc covers in this example, the covercells are 1108.7um
high, the IOs (minimum case) are 130um tall, and the split S7 bumps are 88.9um in region 1. Thus the
height of region 2 is computed as Height = 1108.7um 130um 88.9um = 889.8um. Also, each cover
is 312um wide, giving 889.8umx312um of standard cell region per cover.
Here, the std-cell is only allowed to use the outer VDD/VSS bumps labeled Region 2 core PG pair,
the layout designer running EPS will exclude each VDDO:VSS pair as we mandate it is reserved for IO
power . Thus, for the calculation, there is only one pair of core VDD/VSS bump available for every two
covercells (VDD cover + VSS cover). As a result, there will be 889.8um x 624um supplied by one pair
of core VDD/VSS bump in the region 2 area of Figure 7. Assuming each bump pair can supply a
maximum of 80mA, this gives a power density of:
80mA / ( 889.8um x 612um) = 144mA/mm2
Based on this calculation, and subtracting 20% for added margin, layout designers should not place
any block that has a power density of higher then 115.2mA/mm2 underneath the 312um I/O covercell.
All the other I/O covercells use the same approach to calculate the power density.

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VSS
244.9um
Region 1
Region 2
Core PG Pair
IO PG IO PG
Pair Pair
889.8um
Region 2
130um
(lvcmos18)
Figure 7 Power density area calculation for lvcmos18 fc type covers

Calculation for 3s covers is slightly altered. It is assumed a pair of left and right covers are used
together, and have access to a single VDD bump. In total this gives 2x VSS 2X VDDO 1x VDD bumps.
Only 1 VSS bump is required to service the current needs of both VDDO bumps. This means one
VDD/VSS pair will service a region of (1108.7um - 130um) + 156um = 1134.7um, including the area of
the VDD bump in core.
29 I/O Power
The maximum power deliverable to the IOs is limited by the EM performance of the bumps. IO
covercells are nominally designed with a 1:1:7 VDDO:VSS:signal bump ratio. At 80mA per
VDDO:VSS bump pair, this sets an average EM limit per bump of 11.4mA (RMS).
29.1 Power per pad

The AC+DC power for each pad is dependent on load, frequency and drive strength. Detailed power
breakdowns for each library can be found in the eng-doc for each IO library. The worst case current
for each library is summarized below:

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Library Pad Mode VDD current (mA) VDDO current (mA) Note
PM20_00_216 lvcmos18* Rx 0.300 0.160 1
PM20_00_216 lvcmos18* Tx 0.154 8.600 2
PM20_00_217 lvds18_rx Rx 1.710 2.705 3
PM20_00_225 lvds18_tx Tx 0.037 25.480 4
PM20_00_225 lvds18_tx Tx 0.010 21.730 5
Notes:
1 Rx mode, MODE1, MODE0=11, 1.8V, 200MHz, 2V/ns input slew
2 Tx mode, MODE1, MODE0=11, 1.8V, 200MHz, 20pF
3 Receiver @ 2000 Mbps, 150fF load
4 lvds18_tx_ns @ 2Gbps, 2pF load
5 lvds18_tx_ns @ 400 Mbps, 5pF load
Max power can be calculated using P=V*I, using VDDO=1.98V, VDD=1.05V
29.2 Configurations violating bump EM limits

Due to per-bump EM limts. Currently, the only pad configurations that is not allowed is:
3x lvds18_tx + 1x lvcmos18 (output). Max current = 85.04mA per VDDO:VSS pair
This configuration violates the 80mA per bump EM limit. Other than the above, all configurations of
IOs are allowed when considering EM ONLY. This assumption is valid so long as the loads specified
in the above tables are respected. Therefore the following are the maximum loads per pad in a
covercell without triggering the need for additional EM audit:
Table 12 Max pad load to avoid bump EM audit
Pad Max Load For Frequency up To

lvcmos18* 20pF 200 MHz
lvds18_tx 2pF 1000 MHz
lvds18_tx 5pF 400 MHz
Note: Meeting the above limits for load, or having higher load and satisfactory EM audit does
not mean that SI is ok. Higher load at lower frequencies may require new uncertainties, and
such simulations have a significant lead time (>1 month before STA starts)!

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8 Package Design
The 28n v1_0 release is optimized around a 1-2-1 package target. The package design for 1-2-1
covercells is captured in the following preps:
266338: 28nm IO Covercell Feasibility
121_test_18_final_bump_ordering.mcm.gz
The v1_0 covercell set supports any package type with layer-count greater than 1-2-1, such as 2-2-2-2
or 3-2-3, however it is not optimized for the extra layers these packages provide. As such, any project
which requires higher density IO covercells targeting 2-2-2 or 3-2-3 packages will need to open a new
request prep referencing the 1-2-1 analysis above.
9 Padring Auditor Script for PD Padring Review

TA has developed a script to partially automate the padring review based on the iolm/net-connection
report generated by orbitIO. This script will provide early feedback on correct usage of pad-
substitution rules.
30 Running the Script (TA usage only)

The latest script and rules are located at:
/home/libdev_io/bin/padring_auditor/padring_auditor.pl
/home/libdev_io/bin/padring_auditor/28n/cell_list_28n
/home/libdev_io/bin/padring_auditor/28n/rules_28n.txt
To run, call:
./padring_auditor.pl v cell_list_28n rules_28n [iolm or net-connection report] >! results
31 Reviewing Results
The padring auditor script will run and review the contents of each covercell according to rules set in
the rules_28n.txt file. Each covercell may have different rules, e.g. for ew vs ns pads, or for special
cut or analog scenarios. If any one of the rules are met then the script will simply print the list of pads
it finds in the covercell, and state that the covercell is clean, e.g:
Added sp02000_216_ew analog_3_1
Added lvcmos18_vddo_ew analog_3_2
Added analog_atbh_ew analog_3_3
Added lvds18_vref_ew analog_3_4
Added analog_atbh_ew analog_3_5
Added cutcorepg_216_216_ew analog_3_8
---------> lvcmos18_3s_right_156_fc is clean

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If it sees anything strange, then it will report all of the rules that it tried to apply and how each failed.
Only a single rule ought to be targeted to evaluate any given covercell, so analyzing the results needs
to look at the right rule report. Do for example if the cover is on the left side of the die, review the rule
for ew pads, not ns pads. The rule in use will be given followed by how the pads are checked
against that rule, e.g:
Using rule = lvcmos18_3s_left_ew
lvds_2_5n: Slot and pad incompatible (lvds18_rx_noterm_ew in filler slot)
lvds_2_5n: Slot and pad incompatible (lvds18_rx_noterm_ew in signal slot)
lvds_2_5n: Slot and pad incompatible (lvds18_rx_noterm_ew in filler slot)
The script will list each pad that violates the rule, and describe the rule violated. The report format,
shown above is:
<covercell name> <rule not met> (<pad failing rule> <covercell slot rule was checking>)
There are several rules and sanity checks which are applied:
1) Slot and pad compatibility
2) Total pad width == covercell width
3) A signal pad is not centered in the slot
4) Unrecognized pad type (e.g. Analog with pad type not set to analog)
For additional information, please contact Tech-Access.
32 Known Limitations
The script has a few known feature limitations:
1. Does not provide feedback on correct abutment rules
2. Does not evaluate power domain or HPORTS
3. Does not evaluate ESD rules


28n v1 0 IO Usage Guidelines

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PMC 28nm I/O Usage Guidelines

28nm v1_0 I/O Usage Guidelines

Proprietary and Confidential to PMC-Sierra, Inc. 1

6.4.5 Covercell placement limitations.............................................................................................. 30

Proprietary and Confidential to PMC-Sierra, Inc. 4

Proprietary and Confidential to PMC-Sierra, Inc. 5

TABLE 1 I/O DIMENSIONS.............................................................................................................................................7

Proprietary and Confidential to PMC-Sierra, Inc. 6

Proprietary and Confidential to PMC-Sierra, Inc. 7

lvcmos18_vdd_ns pm20_00_216_fc 30 130

Proprietary and Confidential to PMC-Sierra, Inc. 8

o 314481 Request fix for LUP.2.1u violation in certain abutment combinations

Proprietary and Confidential to PMC-Sierra, Inc. 9

Proprietary and Confidential to PMC-Sierra, Inc. 10

6 Flip Chip Libraries

6.1 1.8V LVCMOS, & Analog I/O (library name: pm20_00_216_fc)

6.2 1.8V LVDS RX (library name: pm20_00_217_fc)

6.3 1.8V LVDS TX (library name: pm20_00_225_fc)

Proprietary and Confidential to PMC-Sierra, Inc. 11

6.4 Flip-Chip Utility (library name: io_util_28nm_fc)

6.5 TSMC CSR and Seal-ring (library name: tsmc_csr_seal)

Proprietary and Confidential to PMC-Sierra, Inc. 12

4 Supported Tools and Versions

Proprietary and Confidential to PMC-Sierra, Inc. 13

5 I/O interface timing

Proprietary and Confidential to PMC-Sierra, Inc. 14

Proprietary and Confidential to PMC-Sierra, Inc. 15

11 Decap assumptions for SSO validity

Luxor specific Interface Decap requirements:

Proprietary and Confidential to PMC-Sierra, Inc. 16

13 IO OCV Pessimism Removal

Proprietary and Confidential to PMC-Sierra, Inc. 17

# read LOCV based derate tables ::CAD::setup::read_locv_tables

# Ensure CRPR is enabled for hold settings TTimer/RemoveClockReconvergencePessimism

# Use CRPR threshold of 1ps unless there is a runtime issue

set_operating_conditions -analysis_type on_chip_variation

# Define OCV values

#Begin Added lines:

Proprietary and Confidential to PMC-Sierra, Inc. 18

Library PM number Eng-Doc See eng-doc

14.1 Drive strength selection

Proprietary and Confidential to PMC-Sierra, Inc. 19

6 Padring Layout Design rules

15 North-South and East-West pad variants

16 Description of I/O covercells

Covercell # Signal bumps Approval for v1_0 Notes

Proprietary and Confidential to PMC-Sierra, Inc. 20

The physical design of the covercells is illustrated below in Figure 1:

Figure 1 Approved IO Covercells, shown in orientation used on die left edge

17 Pad and cut-cell general rules

Proprietary and Confidential to PMC-Sierra, Inc. 21

2. Replace a signal pad with a power pad to increase ESD performance

analog* S1 though S7 S1 though S7 S1 though S3 S1 though S3 1

Proprietary and Confidential to PMC-Sierra, Inc. 22

17.1 Cut cell usage rules

Filler slot cut-cell and spacer compatibility:

Proprietary and Confidential to PMC-Sierra, Inc. 23

Filler slot cut-cell and spacer compatibility:

Filler left 2 and filler left 3:

Proprietary and Confidential to PMC-Sierra, Inc. 24

Filler slot cut-cell and spacer compatibility:

Filler right 1 and filler right 2: